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14#include <linux/io.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/jiffies.h>
18#include <linux/spinlock.h>
19#include <linux/interrupt.h>
20#include <linux/clockchips.h>
21
22#include <asm/time.h>
23
24#include <cs5536/cs5536_mfgpt.h>
25
26static DEFINE_RAW_SPINLOCK(mfgpt_lock);
27
28static u32 mfgpt_base;
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36
37void disable_mfgpt0_counter(void)
38{
39 outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
40}
41EXPORT_SYMBOL(disable_mfgpt0_counter);
42
43
44void enable_mfgpt0_counter(void)
45{
46 outw(0xe310, MFGPT0_SETUP);
47}
48EXPORT_SYMBOL(enable_mfgpt0_counter);
49
50static int mfgpt_timer_set_periodic(struct clock_event_device *evt)
51{
52 raw_spin_lock(&mfgpt_lock);
53
54 outw(COMPARE, MFGPT0_CMP2);
55 outw(0, MFGPT0_CNT);
56 enable_mfgpt0_counter();
57
58 raw_spin_unlock(&mfgpt_lock);
59 return 0;
60}
61
62static int mfgpt_timer_shutdown(struct clock_event_device *evt)
63{
64 if (clockevent_state_periodic(evt) || clockevent_state_oneshot(evt)) {
65 raw_spin_lock(&mfgpt_lock);
66 disable_mfgpt0_counter();
67 raw_spin_unlock(&mfgpt_lock);
68 }
69
70 return 0;
71}
72
73static struct clock_event_device mfgpt_clockevent = {
74 .name = "mfgpt",
75 .features = CLOCK_EVT_FEAT_PERIODIC,
76
77
78 .set_state_shutdown = mfgpt_timer_shutdown,
79 .set_state_periodic = mfgpt_timer_set_periodic,
80 .irq = CS5536_MFGPT_INTR,
81};
82
83static irqreturn_t timer_interrupt(int irq, void *dev_id)
84{
85 u32 basehi;
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93 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
94
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96 outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
97
98 mfgpt_clockevent.event_handler(&mfgpt_clockevent);
99
100 return IRQ_HANDLED;
101}
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106
107void __init setup_mfgpt0_timer(void)
108{
109 u32 basehi;
110 struct clock_event_device *cd = &mfgpt_clockevent;
111 unsigned int cpu = smp_processor_id();
112
113 cd->cpumask = cpumask_of(cpu);
114 clockevent_set_clock(cd, MFGPT_TICK_RATE);
115 cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
116 cd->max_delta_ticks = 0xffff;
117 cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
118 cd->min_delta_ticks = 0xf;
119
120
121 _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
122
123
124 _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
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127 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
128
129 clockevents_register_device(cd);
130
131 if (request_irq(CS5536_MFGPT_INTR, timer_interrupt,
132 IRQF_NOBALANCING | IRQF_TIMER, "timer", NULL))
133 pr_err("Failed to register timer interrupt\n");
134}
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141static u64 mfgpt_read(struct clocksource *cs)
142{
143 unsigned long flags;
144 int count;
145 u32 jifs;
146 static int old_count;
147 static u32 old_jifs;
148
149 raw_spin_lock_irqsave(&mfgpt_lock, flags);
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163 jifs = jiffies;
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165 count = inw(MFGPT0_CNT);
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177 if (count < old_count && jifs == old_jifs)
178 count = old_count;
179
180 old_count = count;
181 old_jifs = jifs;
182
183 raw_spin_unlock_irqrestore(&mfgpt_lock, flags);
184
185 return (u64) (jifs * COMPARE) + count;
186}
187
188static struct clocksource clocksource_mfgpt = {
189 .name = "mfgpt",
190 .rating = 120,
191 .read = mfgpt_read,
192 .mask = CLOCKSOURCE_MASK(32),
193};
194
195int __init init_mfgpt_clocksource(void)
196{
197 if (num_possible_cpus() > 1)
198 return 0;
199
200 return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
201}
202
203arch_initcall(init_mfgpt_clocksource);
204