linux/arch/mips/pci/pci-lantiq.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *
   4 *  Copyright (C) 2010 John Crispin <john@phrozen.org>
   5 */
   6
   7#include <linux/types.h>
   8#include <linux/pci.h>
   9#include <linux/kernel.h>
  10#include <linux/init.h>
  11#include <linux/delay.h>
  12#include <linux/mm.h>
  13#include <linux/vmalloc.h>
  14#include <linux/clk.h>
  15#include <linux/of_platform.h>
  16#include <linux/of_gpio.h>
  17#include <linux/of_irq.h>
  18#include <linux/of_pci.h>
  19
  20#include <asm/addrspace.h>
  21
  22#include <lantiq_soc.h>
  23#include <lantiq_irq.h>
  24
  25#include "pci-lantiq.h"
  26
  27#define PCI_CR_FCI_ADDR_MAP0            0x00C0
  28#define PCI_CR_FCI_ADDR_MAP1            0x00C4
  29#define PCI_CR_FCI_ADDR_MAP2            0x00C8
  30#define PCI_CR_FCI_ADDR_MAP3            0x00CC
  31#define PCI_CR_FCI_ADDR_MAP4            0x00D0
  32#define PCI_CR_FCI_ADDR_MAP5            0x00D4
  33#define PCI_CR_FCI_ADDR_MAP6            0x00D8
  34#define PCI_CR_FCI_ADDR_MAP7            0x00DC
  35#define PCI_CR_CLK_CTRL                 0x0000
  36#define PCI_CR_PCI_MOD                  0x0030
  37#define PCI_CR_PC_ARB                   0x0080
  38#define PCI_CR_FCI_ADDR_MAP11hg         0x00E4
  39#define PCI_CR_BAR11MASK                0x0044
  40#define PCI_CR_BAR12MASK                0x0048
  41#define PCI_CR_BAR13MASK                0x004C
  42#define PCI_CS_BASE_ADDR1               0x0010
  43#define PCI_CR_PCI_ADDR_MAP11           0x0064
  44#define PCI_CR_FCI_BURST_LENGTH         0x00E8
  45#define PCI_CR_PCI_EOI                  0x002C
  46#define PCI_CS_STS_CMD                  0x0004
  47
  48#define PCI_MASTER0_REQ_MASK_2BITS      8
  49#define PCI_MASTER1_REQ_MASK_2BITS      10
  50#define PCI_MASTER2_REQ_MASK_2BITS      12
  51#define INTERNAL_ARB_ENABLE_BIT         0
  52
  53#define LTQ_CGU_IFCCR           0x0018
  54#define LTQ_CGU_PCICR           0x0034
  55
  56#define ltq_pci_w32(x, y)       ltq_w32((x), ltq_pci_membase + (y))
  57#define ltq_pci_r32(x)          ltq_r32(ltq_pci_membase + (x))
  58
  59#define ltq_pci_cfg_w32(x, y)   ltq_w32((x), ltq_pci_mapped_cfg + (y))
  60#define ltq_pci_cfg_r32(x)      ltq_r32(ltq_pci_mapped_cfg + (x))
  61
  62__iomem void *ltq_pci_mapped_cfg;
  63static __iomem void *ltq_pci_membase;
  64
  65static int reset_gpio;
  66static struct clk *clk_pci, *clk_external;
  67static struct resource pci_io_resource;
  68static struct resource pci_mem_resource;
  69static struct pci_ops pci_ops = {
  70        .read   = ltq_pci_read_config_dword,
  71        .write  = ltq_pci_write_config_dword
  72};
  73
  74static struct pci_controller pci_controller = {
  75        .pci_ops        = &pci_ops,
  76        .mem_resource   = &pci_mem_resource,
  77        .mem_offset     = 0x00000000UL,
  78        .io_resource    = &pci_io_resource,
  79        .io_offset      = 0x00000000UL,
  80};
  81
  82static inline u32 ltq_calc_bar11mask(void)
  83{
  84        u32 mem, bar11mask;
  85
  86        /* BAR11MASK value depends on available memory on system. */
  87        mem = get_num_physpages() * PAGE_SIZE;
  88        bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
  89
  90        return bar11mask;
  91}
  92
  93static int ltq_pci_startup(struct platform_device *pdev)
  94{
  95        struct device_node *node = pdev->dev.of_node;
  96        const __be32 *req_mask, *bus_clk;
  97        u32 temp_buffer;
  98
  99        /* get our clocks */
 100        clk_pci = clk_get(&pdev->dev, NULL);
 101        if (IS_ERR(clk_pci)) {
 102                dev_err(&pdev->dev, "failed to get pci clock\n");
 103                return PTR_ERR(clk_pci);
 104        }
 105
 106        clk_external = clk_get(&pdev->dev, "external");
 107        if (IS_ERR(clk_external)) {
 108                clk_put(clk_pci);
 109                dev_err(&pdev->dev, "failed to get external pci clock\n");
 110                return PTR_ERR(clk_external);
 111        }
 112
 113        /* read the bus speed that we want */
 114        bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
 115        if (bus_clk)
 116                clk_set_rate(clk_pci, *bus_clk);
 117
 118        /* and enable the clocks */
 119        clk_enable(clk_pci);
 120        if (of_find_property(node, "lantiq,external-clock", NULL))
 121                clk_enable(clk_external);
 122        else
 123                clk_disable(clk_external);
 124
 125        /* setup reset gpio used by pci */
 126        reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
 127        if (gpio_is_valid(reset_gpio)) {
 128                int ret = devm_gpio_request(&pdev->dev,
 129                                                reset_gpio, "pci-reset");
 130                if (ret) {
 131                        dev_err(&pdev->dev,
 132                                "failed to request gpio %d\n", reset_gpio);
 133                        return ret;
 134                }
 135                gpio_direction_output(reset_gpio, 1);
 136        }
 137
 138        /* enable auto-switching between PCI and EBU */
 139        ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
 140
 141        /* busy, i.e. configuration is not done, PCI access has to be retried */
 142        ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
 143        wmb();
 144        /* BUS Master/IO/MEM access */
 145        ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 146
 147        /* enable external 2 PCI masters */
 148        temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
 149        /* setup the request mask */
 150        req_mask = of_get_property(node, "req-mask", NULL);
 151        if (req_mask)
 152                temp_buffer &= ~((*req_mask & 0xf) << 16);
 153        else
 154                temp_buffer &= ~0xf0000;
 155        /* enable internal arbiter */
 156        temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 157        /* enable internal PCI master reqest */
 158        temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
 159
 160        /* enable EBU request */
 161        temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
 162
 163        /* enable all external masters request */
 164        temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 165        ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
 166        wmb();
 167
 168        /* setup BAR memory regions */
 169        ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
 170        ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
 171        ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
 172        ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
 173        ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
 174        ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
 175        ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 176        ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 177        ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 178        ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
 179        ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
 180        ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
 181        /* both TX and RX endian swap are enabled */
 182        ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
 183        wmb();
 184        ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
 185                PCI_CR_BAR12MASK);
 186        ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
 187                PCI_CR_BAR13MASK);
 188        /*use 8 dw burst length */
 189        ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 190        ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 191        wmb();
 192
 193        /* setup irq line */
 194        ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
 195        ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
 196
 197        /* toggle reset pin */
 198        if (gpio_is_valid(reset_gpio)) {
 199                __gpio_set_value(reset_gpio, 0);
 200                wmb();
 201                mdelay(1);
 202                __gpio_set_value(reset_gpio, 1);
 203        }
 204        return 0;
 205}
 206
 207static int ltq_pci_probe(struct platform_device *pdev)
 208{
 209        struct resource *res_cfg, *res_bridge;
 210
 211        pci_clear_flags(PCI_PROBE_ONLY);
 212
 213        res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 214        ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
 215        if (IS_ERR(ltq_pci_membase))
 216                return PTR_ERR(ltq_pci_membase);
 217
 218        res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 219        ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
 220        if (IS_ERR(ltq_pci_mapped_cfg))
 221                return PTR_ERR(ltq_pci_mapped_cfg);
 222
 223        ltq_pci_startup(pdev);
 224
 225        pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
 226        register_pci_controller(&pci_controller);
 227        return 0;
 228}
 229
 230static const struct of_device_id ltq_pci_match[] = {
 231        { .compatible = "lantiq,pci-xway" },
 232        {},
 233};
 234
 235static struct platform_driver ltq_pci_driver = {
 236        .probe = ltq_pci_probe,
 237        .driver = {
 238                .name = "pci-xway",
 239                .of_match_table = ltq_pci_match,
 240        },
 241};
 242
 243int __init pcibios_init(void)
 244{
 245        int ret = platform_driver_register(&ltq_pci_driver);
 246        if (ret)
 247                pr_info("pci-xway: Error registering platform driver!");
 248        return ret;
 249}
 250
 251arch_initcall(pcibios_init);
 252