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10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/irqdomain.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_pci.h>
20#include <linux/platform_device.h>
21
22#include <asm/mach-ralink/rt3883.h>
23#include <asm/mach-ralink/ralink_regs.h>
24
25#define RT3883_MEMORY_BASE 0x00000000
26#define RT3883_MEMORY_SIZE 0x02000000
27
28#define RT3883_PCI_REG_PCICFG 0x00
29#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
30#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
31#define RT3883_PCICFG_PCIRST BIT(1)
32#define RT3883_PCI_REG_PCIRAW 0x04
33#define RT3883_PCI_REG_PCIINT 0x08
34#define RT3883_PCI_REG_PCIENA 0x0c
35
36#define RT3883_PCI_REG_CFGADDR 0x20
37#define RT3883_PCI_REG_CFGDATA 0x24
38#define RT3883_PCI_REG_MEMBASE 0x28
39#define RT3883_PCI_REG_IOBASE 0x2c
40#define RT3883_PCI_REG_ARBCTL 0x80
41
42#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
43#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
44#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
45#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
46#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
47#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
48#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
49
50#define RT3883_PCI_MODE_NONE 0
51#define RT3883_PCI_MODE_PCI BIT(0)
52#define RT3883_PCI_MODE_PCIE BIT(1)
53#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
54
55#define RT3883_PCI_IRQ_COUNT 32
56
57#define RT3883_P2P_BR_DEVNUM 1
58
59struct rt3883_pci_controller {
60 void __iomem *base;
61
62 struct device_node *intc_of_node;
63 struct irq_domain *irq_domain;
64
65 struct pci_controller pci_controller;
66 struct resource io_res;
67 struct resource mem_res;
68
69 bool pcie_ready;
70};
71
72static inline struct rt3883_pci_controller *
73pci_bus_to_rt3883_controller(struct pci_bus *bus)
74{
75 struct pci_controller *hose;
76
77 hose = (struct pci_controller *) bus->sysdata;
78 return container_of(hose, struct rt3883_pci_controller, pci_controller);
79}
80
81static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
82 unsigned reg)
83{
84 return ioread32(rpc->base + reg);
85}
86
87static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
88 u32 val, unsigned reg)
89{
90 iowrite32(val, rpc->base + reg);
91}
92
93static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
94 unsigned int func, unsigned int where)
95{
96 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
97 0x80000000;
98}
99
100static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
101 unsigned bus, unsigned slot,
102 unsigned func, unsigned reg)
103{
104 u32 address;
105 u32 ret;
106
107 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
108
109 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
110 ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
111
112 return ret;
113}
114
115static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
116 unsigned bus, unsigned slot,
117 unsigned func, unsigned reg, u32 val)
118{
119 u32 address;
120
121 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
122
123 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
124 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
125}
126
127static void rt3883_pci_irq_handler(struct irq_desc *desc)
128{
129 struct rt3883_pci_controller *rpc;
130 u32 pending;
131
132 rpc = irq_desc_get_handler_data(desc);
133
134 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
135 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
136
137 if (!pending) {
138 spurious_interrupt();
139 return;
140 }
141
142 while (pending) {
143 unsigned bit = __ffs(pending);
144
145 generic_handle_domain_irq(rpc->irq_domain, bit);
146
147 pending &= ~BIT(bit);
148 }
149}
150
151static void rt3883_pci_irq_unmask(struct irq_data *d)
152{
153 struct rt3883_pci_controller *rpc;
154 u32 t;
155
156 rpc = irq_data_get_irq_chip_data(d);
157
158 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
159 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
160
161 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
162}
163
164static void rt3883_pci_irq_mask(struct irq_data *d)
165{
166 struct rt3883_pci_controller *rpc;
167 u32 t;
168
169 rpc = irq_data_get_irq_chip_data(d);
170
171 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
172 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
173
174 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
175}
176
177static struct irq_chip rt3883_pci_irq_chip = {
178 .name = "RT3883 PCI",
179 .irq_mask = rt3883_pci_irq_mask,
180 .irq_unmask = rt3883_pci_irq_unmask,
181 .irq_mask_ack = rt3883_pci_irq_mask,
182};
183
184static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
185 irq_hw_number_t hw)
186{
187 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
188 irq_set_chip_data(irq, d->host_data);
189
190 return 0;
191}
192
193static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
194 .map = rt3883_pci_irq_map,
195 .xlate = irq_domain_xlate_onecell,
196};
197
198static int rt3883_pci_irq_init(struct device *dev,
199 struct rt3883_pci_controller *rpc)
200{
201 int irq;
202
203 irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
204 if (irq == 0) {
205 dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
206 return -EINVAL;
207 }
208
209
210 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
211
212 rpc->irq_domain =
213 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
214 &rt3883_pci_irq_domain_ops,
215 rpc);
216 if (!rpc->irq_domain) {
217 dev_err(dev, "unable to add IRQ domain\n");
218 return -ENODEV;
219 }
220
221 irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
222
223 return 0;
224}
225
226static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
227 int where, int size, u32 *val)
228{
229 struct rt3883_pci_controller *rpc;
230 u32 address;
231 u32 data;
232
233 rpc = pci_bus_to_rt3883_controller(bus);
234
235 if (!rpc->pcie_ready && bus->number == 1)
236 return PCIBIOS_DEVICE_NOT_FOUND;
237
238 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
239 PCI_FUNC(devfn), where);
240
241 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
242 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
243
244 switch (size) {
245 case 1:
246 *val = (data >> ((where & 3) << 3)) & 0xff;
247 break;
248 case 2:
249 *val = (data >> ((where & 3) << 3)) & 0xffff;
250 break;
251 case 4:
252 *val = data;
253 break;
254 }
255
256 return PCIBIOS_SUCCESSFUL;
257}
258
259static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
260 int where, int size, u32 val)
261{
262 struct rt3883_pci_controller *rpc;
263 u32 address;
264 u32 data;
265
266 rpc = pci_bus_to_rt3883_controller(bus);
267
268 if (!rpc->pcie_ready && bus->number == 1)
269 return PCIBIOS_DEVICE_NOT_FOUND;
270
271 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
272 PCI_FUNC(devfn), where);
273
274 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
275 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
276
277 switch (size) {
278 case 1:
279 data = (data & ~(0xff << ((where & 3) << 3))) |
280 (val << ((where & 3) << 3));
281 break;
282 case 2:
283 data = (data & ~(0xffff << ((where & 3) << 3))) |
284 (val << ((where & 3) << 3));
285 break;
286 case 4:
287 data = val;
288 break;
289 }
290
291 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
292
293 return PCIBIOS_SUCCESSFUL;
294}
295
296static struct pci_ops rt3883_pci_ops = {
297 .read = rt3883_pci_config_read,
298 .write = rt3883_pci_config_write,
299};
300
301static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
302{
303 u32 syscfg1;
304 u32 rstctrl;
305 u32 clkcfg1;
306 u32 t;
307
308 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
309 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
310 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
311
312 if (mode & RT3883_PCI_MODE_PCIE) {
313 rstctrl |= RT3883_RSTCTRL_PCIE;
314 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
315
316
317 syscfg1 &= ~(0x30);
318 syscfg1 |= (2 << 4);
319 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
320
321 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
322 t &= ~BIT(31);
323 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
324
325 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
326 t &= 0x80ffffff;
327 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
328
329 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
330 t |= 0xa << 24;
331 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
332
333 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
334 t |= BIT(31);
335 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
336
337 msleep(50);
338
339 rstctrl &= ~RT3883_RSTCTRL_PCIE;
340 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
341 }
342
343 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
344
345 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
346
347 if (mode & RT3883_PCI_MODE_PCI) {
348 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
349 rstctrl &= ~RT3883_RSTCTRL_PCI;
350 }
351
352 if (mode & RT3883_PCI_MODE_PCIE) {
353 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
354 rstctrl &= ~RT3883_RSTCTRL_PCIE;
355 }
356
357 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
358 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
359 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
360
361 msleep(500);
362
363
364
365
366
367 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
368 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
369
370
371 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
372 msleep(500);
373
374 if (mode & RT3883_PCI_MODE_PCIE) {
375 msleep(500);
376
377 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
378
379 rpc->pcie_ready = t & BIT(0);
380
381 if (!rpc->pcie_ready) {
382
383 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
384 t |= RT3883_RSTCTRL_PCIE;
385 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
386 t &= ~RT3883_RSTCTRL_PCIE;
387 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
388
389
390 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
391 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
392 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
393
394 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
395 t &= ~0xf000c080;
396 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
397 }
398 }
399
400
401 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
402}
403
404static int rt3883_pci_probe(struct platform_device *pdev)
405{
406 struct rt3883_pci_controller *rpc;
407 struct device *dev = &pdev->dev;
408 struct device_node *np = dev->of_node;
409 struct resource *res;
410 struct device_node *child;
411 u32 val;
412 int err;
413 int mode;
414
415 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
416 if (!rpc)
417 return -ENOMEM;
418
419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
420 rpc->base = devm_ioremap_resource(dev, res);
421 if (IS_ERR(rpc->base))
422 return PTR_ERR(rpc->base);
423
424
425 for_each_child_of_node(np, child) {
426 if (of_get_property(child, "interrupt-controller", NULL)) {
427 rpc->intc_of_node = child;
428 break;
429 }
430 }
431
432 if (!rpc->intc_of_node) {
433 dev_err(dev, "%pOF has no %s child node",
434 np, "interrupt controller");
435 return -EINVAL;
436 }
437
438
439 for_each_child_of_node(np, child) {
440 if (of_node_is_type(child, "pci")) {
441 rpc->pci_controller.of_node = child;
442 break;
443 }
444 }
445
446 if (!rpc->pci_controller.of_node) {
447 dev_err(dev, "%pOF has no %s child node",
448 np, "PCI host bridge");
449 err = -EINVAL;
450 goto err_put_intc_node;
451 }
452
453 mode = RT3883_PCI_MODE_NONE;
454 for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
455 int devfn;
456
457 if (!of_node_is_type(child, "pci"))
458 continue;
459
460 devfn = of_pci_get_devfn(child);
461 if (devfn < 0)
462 continue;
463
464 switch (PCI_SLOT(devfn)) {
465 case 1:
466 mode |= RT3883_PCI_MODE_PCIE;
467 break;
468
469 case 17:
470 case 18:
471 mode |= RT3883_PCI_MODE_PCI;
472 break;
473 }
474 }
475
476 if (mode == RT3883_PCI_MODE_NONE) {
477 dev_err(dev, "unable to determine PCI mode\n");
478 err = -EINVAL;
479 goto err_put_hb_node;
480 }
481
482 dev_info(dev, "mode:%s%s\n",
483 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
484 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
485
486 rt3883_pci_preinit(rpc, mode);
487
488 rpc->pci_controller.pci_ops = &rt3883_pci_ops;
489 rpc->pci_controller.io_resource = &rpc->io_res;
490 rpc->pci_controller.mem_resource = &rpc->mem_res;
491
492
493 pci_load_of_ranges(&rpc->pci_controller,
494 rpc->pci_controller.of_node);
495
496 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
497 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
498
499 ioport_resource.start = rpc->io_res.start;
500 ioport_resource.end = rpc->io_res.end;
501
502
503 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
504 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
505 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
506 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
507 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
508
509
510 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
511 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
512 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
513 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
514 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
515
516 err = rt3883_pci_irq_init(dev, rpc);
517 if (err)
518 goto err_put_hb_node;
519
520
521 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
522 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
523 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
524
525
526 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
527 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
528 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
529
530 if (mode == RT3883_PCI_MODE_PCIE) {
531 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
532 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
533
534 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
535 PCI_BASE_ADDRESS_0,
536 RT3883_MEMORY_BASE);
537
538 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
539 PCI_BASE_ADDRESS_0);
540 } else {
541 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
542 PCI_IO_BASE, 0x00000101);
543 }
544
545 register_pci_controller(&rpc->pci_controller);
546
547 return 0;
548
549err_put_hb_node:
550 of_node_put(rpc->pci_controller.of_node);
551err_put_intc_node:
552 of_node_put(rpc->intc_of_node);
553 return err;
554}
555
556int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
557{
558 return of_irq_parse_and_map_pci(dev, slot, pin);
559}
560
561int pcibios_plat_dev_init(struct pci_dev *dev)
562{
563 return 0;
564}
565
566static const struct of_device_id rt3883_pci_ids[] = {
567 { .compatible = "ralink,rt3883-pci" },
568 {},
569};
570
571static struct platform_driver rt3883_pci_driver = {
572 .probe = rt3883_pci_probe,
573 .driver = {
574 .name = "rt3883-pci",
575 .of_match_table = of_match_ptr(rt3883_pci_ids),
576 },
577};
578
579static int __init rt3883_pci_init(void)
580{
581 return platform_driver_register(&rt3883_pci_driver);
582}
583
584postcore_initcall(rt3883_pci_init);
585
