1# SPDX-License-Identifier: GPL-2.0-only 2comment "Processor Features" 3 4config CPU_BIG_ENDIAN 5 def_bool !CPU_LITTLE_ENDIAN 6 7config CPU_LITTLE_ENDIAN 8 bool "Little endian" 9 default y 10 11config FPU 12 bool "FPU support" 13 default n 14 help 15 If FPU ISA is used in user space, this configuration shall be Y to 16 enable required support in kernel such as fpu context switch and 17 fpu exception handler. 18 19 If no FPU ISA is used in user space, say N. 20 21config LAZY_FPU 22 bool "lazy FPU support" 23 depends on FPU 24 default y 25 help 26 Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can 27 enhance system performance by reducing the context switch 28 frequency of the FPU register. 29 30 For normal case, say Y. 31 32config SUPPORT_DENORMAL_ARITHMETIC 33 bool "Denormal arithmetic support" 34 depends on FPU 35 default n 36 help 37 Say Y here to enable arithmetic of denormalized number. Enabling 38 this feature can enhance the precision for tininess number. 39 However, performance loss in float point calculations is 40 possibly significant due to additional FPU exception. 41 42 If the calculated tolerance for tininess number is not critical, 43 say N to prevent performance loss. 44 45config HWZOL 46 bool "hardware zero overhead loop support" 47 depends on CPU_D10 || CPU_D15 48 default n 49 help 50 A set of Zero-Overhead Loop mechanism is provided to reduce the 51 instruction fetch and execution overhead of loop-control instructions. 52 It will save 3 registers($LB, $LC, $LE) for context saving if say Y. 53 You don't need to save these registers if you can make sure your user 54 program doesn't use these registers. 55 56 If unsure, say N. 57 58config CPU_CACHE_ALIASING 59 bool "Aliasing cache" 60 depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3 61 default y 62 help 63 If this CPU is using VIPT data cache and its cache way size is larger 64 than page size, say Y. If it is using PIPT data cache, say N. 65 66 If unsure, say Y. 67 68choice 69 prompt "minimum CPU type" 70 default CPU_V3 71 help 72 The data cache of N15/D15 is implemented as PIPT and it will not cause 73 the cache aliasing issue. The rest cpus(N13, N10 and D10) are 74 implemented as VIPT data cache. It may cause the cache aliasing issue 75 if its cache way size is larger than page size. You can specify the 76 CPU type directly or choose CPU_V3 if unsure. 77 78 A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. 79 A kernel built for N15 is able to run on N15 or D15. 80 A kernel built for D10 is able to run on D10 or D15. 81 A kernel built for D15 is able to run on D15. 82 A kernel built for N13 is able to run on N15, N13 or D15. 83 84config CPU_N15 85 bool "AndesCore N15" 86config CPU_N13 87 bool "AndesCore N13" 88 select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB 89config CPU_N10 90 bool "AndesCore N10" 91 select CPU_CACHE_ALIASING 92config CPU_D15 93 bool "AndesCore D15" 94config CPU_D10 95 bool "AndesCore D10" 96 select CPU_CACHE_ALIASING 97config CPU_V3 98 bool "AndesCore v3 compatible" 99 select CPU_CACHE_ALIASING 100endchoice 101choice 102 prompt "Paging -- page size " 103 default ANDES_PAGE_SIZE_4KB 104config ANDES_PAGE_SIZE_4KB 105 bool "use 4KB page size" 106config ANDES_PAGE_SIZE_8KB 107 bool "use 8KB page size" 108endchoice 109 110config CPU_ICACHE_DISABLE 111 bool "Disable I-Cache" 112 help 113 Say Y here to disable the processor instruction cache. Unless 114 you have a reason not to or are unsure, say N. 115 116config CPU_DCACHE_DISABLE 117 bool "Disable D-Cache" 118 help 119 Say Y here to disable the processor data cache. Unless 120 you have a reason not to or are unsure, say N. 121 122config CPU_DCACHE_WRITETHROUGH 123 bool "Force write through D-cache" 124 depends on !CPU_DCACHE_DISABLE 125 help 126 Say Y here to use the data cache in writethrough mode. Unless you 127 specifically require this or are unsure, say N. 128 129config WBNA 130 bool "WBNA" 131 default n 132 help 133 Say Y here to enable write-back memory with no-write-allocation policy. 134 135config ALIGNMENT_TRAP 136 bool "Kernel support unaligned access handling by sw" 137 depends on PROC_FS 138 default n 139 help 140 Andes processors cannot load/store information which is not 141 naturally aligned on the bus, i.e., a 4 byte load must start at an 142 address divisible by 4. On 32-bit Andes processors, these non-aligned 143 load/store instructions will be emulated in software if you say Y 144 here, which has a severe performance impact. With an IP-only 145 configuration it is safe to say N, otherwise say Y. 146 147config HW_SUPPORT_UNALIGNMENT_ACCESS 148 bool "Kernel support unaligned access handling by hw" 149 depends on !ALIGNMENT_TRAP 150 default n 151 help 152 Andes processors load/store world/half-word instructions can access 153 unaligned memory locations without generating the Data Alignment 154 Check exceptions. With an IP-only configuration it is safe to say N, 155 otherwise say Y. 156 157config HIGHMEM 158 bool "High Memory Support" 159 depends on MMU && !CPU_CACHE_ALIASING 160 select KMAP_LOCAL 161 help 162 The address space of Andes processors is only 4 Gigabytes large 163 and it has to accommodate user address space, kernel address 164 space as well as some memory mapped IO. That means that, if you 165 have a large amount of physical memory and/or IO, not all of the 166 memory can be "permanently mapped" by the kernel. The physical 167 memory that is not permanently mapped is called "high memory". 168 169 Depending on the selected kernel/user memory split, minimum 170 vmalloc space and actual amount of RAM, you may not need this 171 option which should result in a slightly faster kernel. 172 173 If unsure, say N. 174 175config CACHE_L2 176 bool "Support L2 cache" 177 default y 178 help 179 Say Y here to enable L2 cache if your SoC are integrated with L2CC. 180 If unsure, say N. 181 182config HW_PRE 183 bool "Enable hardware prefetcher" 184 default y 185 help 186 Say Y here to enable hardware prefetcher feature. 187 Only when CPU_VER.REV >= 0x09 can support. 188 189menu "Memory configuration" 190 191choice 192 prompt "Memory split" 193 depends on MMU 194 default VMSPLIT_3G_OPT 195 help 196 Select the desired split between kernel and user memory. 197 198 If you are not absolutely sure what you are doing, leave this 199 option alone! 200 201 config VMSPLIT_3G 202 bool "3G/1G user/kernel split" 203 config VMSPLIT_3G_OPT 204 bool "3G/1G user/kernel split (for full 1G low memory)" 205 config VMSPLIT_2G 206 bool "2G/2G user/kernel split" 207 config VMSPLIT_1G 208 bool "1G/3G user/kernel split" 209endchoice 210 211config PAGE_OFFSET 212 hex 213 default 0x40000000 if VMSPLIT_1G 214 default 0x80000000 if VMSPLIT_2G 215 default 0xB0000000 if VMSPLIT_3G_OPT 216 default 0xC0000000 217 218endmenu 219