LXR linux/arch/nds32/include/asm/io.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2// Copyright (C) 2005-2017 Andes Technology Corporation
   3
   4#ifndef __ASM_NDS32_IO_H
   5#define __ASM_NDS32_IO_H
   6
   7#include <linux/types.h>
   8
   9#define __raw_writeb __raw_writeb
  10static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  11{
  12        asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
  13}
  14
  15#define __raw_writew __raw_writew
  16static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  17{
  18        asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
  19}
  20
  21#define __raw_writel __raw_writel
  22static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  23{
  24        asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
  25}
  26
  27#define __raw_readb __raw_readb
  28static inline u8 __raw_readb(const volatile void __iomem *addr)
  29{
  30        u8 val;
  31
  32        asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
  33        return val;
  34}
  35
  36#define __raw_readw __raw_readw
  37static inline u16 __raw_readw(const volatile void __iomem *addr)
  38{
  39        u16 val;
  40
  41        asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
  42        return val;
  43}
  44
  45#define __raw_readl __raw_readl
  46static inline u32 __raw_readl(const volatile void __iomem *addr)
  47{
  48        u32 val;
  49
  50        asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
  51        return val;
  52}
  53
  54#define __iormb()               rmb()
  55#define __iowmb()               wmb()
  56
  57/*
  58 * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
  59 * are not guaranteed to provide ordering against spinlocks or memory
  60 * accesses.
  61 */
  62
  63#define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
  64#define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
  65#define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
  66#define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
  67#define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
  68#define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
  69
  70/*
  71 * {read,write}{b,w,l,q}() access little endian memory and return result in
  72 * native endianness.
  73 */
  74#define readb(c)        ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
  75#define readw(c)        ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
  76#define readl(c)        ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
  77
  78#define writeb(v,c)     ({ __iowmb(); writeb_relaxed((v),(c)); })
  79#define writew(v,c)     ({ __iowmb(); writew_relaxed((v),(c)); })
  80#define writel(v,c)     ({ __iowmb(); writel_relaxed((v),(c)); })
  81
  82#include <asm-generic/io.h>
  83
  84#endif /* __ASM_NDS32_IO_H */
  85