1
2
3
4
5
6
7
8
9
10
11
12
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/seq_file.h>
19#include <linux/pagemap.h>
20#include <linux/sched.h>
21#include <linux/sched/mm.h>
22#include <asm/pdc.h>
23#include <asm/cache.h>
24#include <asm/cacheflush.h>
25#include <asm/tlbflush.h>
26#include <asm/page.h>
27#include <asm/processor.h>
28#include <asm/sections.h>
29#include <asm/shmparam.h>
30
31int split_tlb __ro_after_init;
32int dcache_stride __ro_after_init;
33int icache_stride __ro_after_init;
34EXPORT_SYMBOL(dcache_stride);
35
36void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
37EXPORT_SYMBOL(flush_dcache_page_asm);
38void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
39void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
40
41
42
43
44
45
46
47DEFINE_SPINLOCK(pa_tlb_flush_lock);
48
49
50DEFINE_SPINLOCK(pa_swapper_pg_lock);
51
52#if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
53int pa_serialize_tlb_flushes __ro_after_init;
54#endif
55
56struct pdc_cache_info cache_info __ro_after_init;
57#ifndef CONFIG_PA20
58static struct pdc_btlb_info btlb_info __ro_after_init;
59#endif
60
61#ifdef CONFIG_SMP
62void
63flush_data_cache(void)
64{
65 on_each_cpu(flush_data_cache_local, NULL, 1);
66}
67void
68flush_instruction_cache(void)
69{
70 on_each_cpu(flush_instruction_cache_local, NULL, 1);
71}
72#endif
73
74void
75flush_cache_all_local(void)
76{
77 flush_instruction_cache_local(NULL);
78 flush_data_cache_local(NULL);
79}
80EXPORT_SYMBOL(flush_cache_all_local);
81
82
83#define pfn_va(pfn) __va(PFN_PHYS(pfn))
84
85void
86update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
87{
88 unsigned long pfn = pte_pfn(*ptep);
89 struct page *page;
90
91
92
93
94 if (!pfn_valid(pfn))
95 return;
96
97 page = pfn_to_page(pfn);
98 if (page_mapping_file(page) &&
99 test_bit(PG_dcache_dirty, &page->flags)) {
100 flush_kernel_dcache_page_addr(pfn_va(pfn));
101 clear_bit(PG_dcache_dirty, &page->flags);
102 } else if (parisc_requires_coherency())
103 flush_kernel_dcache_page_addr(pfn_va(pfn));
104}
105
106void
107show_cache_info(struct seq_file *m)
108{
109 char buf[32];
110
111 seq_printf(m, "I-cache\t\t: %ld KB\n",
112 cache_info.ic_size/1024 );
113 if (cache_info.dc_loop != 1)
114 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
115 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
116 cache_info.dc_size/1024,
117 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
118 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
119 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
120 seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
121 cache_info.it_size,
122 cache_info.dt_size,
123 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
124 );
125
126#ifndef CONFIG_PA20
127
128 if (btlb_info.max_size==0) {
129 seq_printf(m, "BTLB\t\t: not supported\n" );
130 } else {
131 seq_printf(m,
132 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
133 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
134 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
135 btlb_info.max_size, (int)4096,
136 btlb_info.max_size>>8,
137 btlb_info.fixed_range_info.num_i,
138 btlb_info.fixed_range_info.num_d,
139 btlb_info.fixed_range_info.num_comb,
140 btlb_info.variable_range_info.num_i,
141 btlb_info.variable_range_info.num_d,
142 btlb_info.variable_range_info.num_comb
143 );
144 }
145#endif
146}
147
148void __init
149parisc_cache_init(void)
150{
151 if (pdc_cache_info(&cache_info) < 0)
152 panic("parisc_cache_init: pdc_cache_info failed");
153
154#if 0
155 printk("ic_size %lx dc_size %lx it_size %lx\n",
156 cache_info.ic_size,
157 cache_info.dc_size,
158 cache_info.it_size);
159
160 printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
161 cache_info.dc_base,
162 cache_info.dc_stride,
163 cache_info.dc_count,
164 cache_info.dc_loop);
165
166 printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
167 *(unsigned long *) (&cache_info.dc_conf),
168 cache_info.dc_conf.cc_alias,
169 cache_info.dc_conf.cc_block,
170 cache_info.dc_conf.cc_line,
171 cache_info.dc_conf.cc_shift);
172 printk(" wt %d sh %d cst %d hv %d\n",
173 cache_info.dc_conf.cc_wt,
174 cache_info.dc_conf.cc_sh,
175 cache_info.dc_conf.cc_cst,
176 cache_info.dc_conf.cc_hv);
177
178 printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
179 cache_info.ic_base,
180 cache_info.ic_stride,
181 cache_info.ic_count,
182 cache_info.ic_loop);
183
184 printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
185 cache_info.it_sp_base,
186 cache_info.it_sp_stride,
187 cache_info.it_sp_count,
188 cache_info.it_loop,
189 cache_info.it_off_base,
190 cache_info.it_off_stride,
191 cache_info.it_off_count);
192
193 printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
194 cache_info.dt_sp_base,
195 cache_info.dt_sp_stride,
196 cache_info.dt_sp_count,
197 cache_info.dt_loop,
198 cache_info.dt_off_base,
199 cache_info.dt_off_stride,
200 cache_info.dt_off_count);
201
202 printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
203 *(unsigned long *) (&cache_info.ic_conf),
204 cache_info.ic_conf.cc_alias,
205 cache_info.ic_conf.cc_block,
206 cache_info.ic_conf.cc_line,
207 cache_info.ic_conf.cc_shift);
208 printk(" wt %d sh %d cst %d hv %d\n",
209 cache_info.ic_conf.cc_wt,
210 cache_info.ic_conf.cc_sh,
211 cache_info.ic_conf.cc_cst,
212 cache_info.ic_conf.cc_hv);
213
214 printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
215 cache_info.dt_conf.tc_sh,
216 cache_info.dt_conf.tc_page,
217 cache_info.dt_conf.tc_cst,
218 cache_info.dt_conf.tc_aid,
219 cache_info.dt_conf.tc_sr);
220
221 printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
222 cache_info.it_conf.tc_sh,
223 cache_info.it_conf.tc_page,
224 cache_info.it_conf.tc_cst,
225 cache_info.it_conf.tc_aid,
226 cache_info.it_conf.tc_sr);
227#endif
228
229 split_tlb = 0;
230 if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
231 if (cache_info.dt_conf.tc_sh == 2)
232 printk(KERN_WARNING "Unexpected TLB configuration. "
233 "Will flush I/D separately (could be optimized).\n");
234
235 split_tlb = 1;
236 }
237
238
239
240
241
242
243
244#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
245 dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
246 icache_stride = CAFL_STRIDE(cache_info.ic_conf);
247#undef CAFL_STRIDE
248
249#ifndef CONFIG_PA20
250 if (pdc_btlb_info(&btlb_info) < 0) {
251 memset(&btlb_info, 0, sizeof btlb_info);
252 }
253#endif
254
255 if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
256 PDC_MODEL_NVA_UNSUPPORTED) {
257 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
258#if 0
259 panic("SMP kernel required to avoid non-equivalent aliasing");
260#endif
261 }
262}
263
264void __init disable_sr_hashing(void)
265{
266 int srhash_type, retval;
267 unsigned long space_bits;
268
269 switch (boot_cpu_data.cpu_type) {
270 case pcx:
271 BUG();
272 return;
273
274 case pcxs:
275 case pcxt:
276 case pcxt_:
277 srhash_type = SRHASH_PCXST;
278 break;
279
280 case pcxl:
281 srhash_type = SRHASH_PCXL;
282 break;
283
284 case pcxl2:
285 return;
286
287 default:
288 srhash_type = SRHASH_PA20;
289 break;
290 }
291
292 disable_sr_hashing_asm(srhash_type);
293
294 retval = pdc_spaceid_bits(&space_bits);
295
296 if (retval < 0 && retval != PDC_BAD_OPTION)
297 panic("pdc_spaceid_bits call failed.\n");
298 if (space_bits != 0)
299 panic("SpaceID hashing is still on!\n");
300}
301
302static inline void
303__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
304 unsigned long physaddr)
305{
306 preempt_disable();
307 flush_dcache_page_asm(physaddr, vmaddr);
308 if (vma->vm_flags & VM_EXEC)
309 flush_icache_page_asm(physaddr, vmaddr);
310 preempt_enable();
311}
312
313static inline void
314__purge_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
315 unsigned long physaddr)
316{
317 preempt_disable();
318 purge_dcache_page_asm(physaddr, vmaddr);
319 if (vma->vm_flags & VM_EXEC)
320 flush_icache_page_asm(physaddr, vmaddr);
321 preempt_enable();
322}
323
324void flush_dcache_page(struct page *page)
325{
326 struct address_space *mapping = page_mapping_file(page);
327 struct vm_area_struct *mpnt;
328 unsigned long offset;
329 unsigned long addr, old_addr = 0;
330 pgoff_t pgoff;
331
332 if (mapping && !mapping_mapped(mapping)) {
333 set_bit(PG_dcache_dirty, &page->flags);
334 return;
335 }
336
337 flush_kernel_dcache_page_addr(page_address(page));
338
339 if (!mapping)
340 return;
341
342 pgoff = page->index;
343
344
345
346
347
348
349 flush_dcache_mmap_lock(mapping);
350 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
351 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
352 addr = mpnt->vm_start + offset;
353
354
355
356
357
358
359
360
361
362
363 flush_tlb_page(mpnt, addr);
364 if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
365 != (addr & (SHM_COLOUR - 1))) {
366 __flush_cache_page(mpnt, addr, page_to_phys(page));
367 if (parisc_requires_coherency() && old_addr)
368 printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file);
369 old_addr = addr;
370 }
371 }
372 flush_dcache_mmap_unlock(mapping);
373}
374EXPORT_SYMBOL(flush_dcache_page);
375
376
377EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
378EXPORT_SYMBOL(flush_data_cache_local);
379EXPORT_SYMBOL(flush_kernel_icache_range_asm);
380
381#define FLUSH_THRESHOLD 0x80000
382static unsigned long parisc_cache_flush_threshold __ro_after_init = FLUSH_THRESHOLD;
383
384#define FLUSH_TLB_THRESHOLD (16*1024)
385static unsigned long parisc_tlb_flush_threshold __ro_after_init = ~0UL;
386
387void __init parisc_setup_cache_timing(void)
388{
389 unsigned long rangetime, alltime;
390 unsigned long size;
391 unsigned long threshold;
392
393 alltime = mfctl(16);
394 flush_data_cache();
395 alltime = mfctl(16) - alltime;
396
397 size = (unsigned long)(_end - _text);
398 rangetime = mfctl(16);
399 flush_kernel_dcache_range((unsigned long)_text, size);
400 rangetime = mfctl(16) - rangetime;
401
402 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
403 alltime, size, rangetime);
404
405 threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
406 if (threshold > cache_info.dc_size)
407 threshold = cache_info.dc_size;
408 if (threshold)
409 parisc_cache_flush_threshold = threshold;
410 printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
411 parisc_cache_flush_threshold/1024);
412
413
414
415
416
417 if (num_online_cpus() > 1 && !parisc_requires_coherency()) {
418 threshold = max(cache_info.it_size, cache_info.dt_size);
419 threshold *= PAGE_SIZE;
420 threshold /= num_online_cpus();
421 goto set_tlb_threshold;
422 }
423
424 size = (unsigned long)_end - (unsigned long)_text;
425 rangetime = mfctl(16);
426 flush_tlb_kernel_range((unsigned long)_text, (unsigned long)_end);
427 rangetime = mfctl(16) - rangetime;
428
429 alltime = mfctl(16);
430 flush_tlb_all();
431 alltime = mfctl(16) - alltime;
432
433 printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",
434 alltime, size, rangetime);
435
436 threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);
437 printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",
438 threshold/1024);
439
440set_tlb_threshold:
441 if (threshold > FLUSH_TLB_THRESHOLD)
442 parisc_tlb_flush_threshold = threshold;
443 else
444 parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
445
446 printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
447 parisc_tlb_flush_threshold/1024);
448}
449
450extern void purge_kernel_dcache_page_asm(unsigned long);
451extern void clear_user_page_asm(void *, unsigned long);
452extern void copy_user_page_asm(void *, void *, unsigned long);
453
454void flush_kernel_dcache_page_addr(void *addr)
455{
456 unsigned long flags;
457
458 flush_kernel_dcache_page_asm(addr);
459 purge_tlb_start(flags);
460 pdtlb_kernel(addr);
461 purge_tlb_end(flags);
462}
463EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
464
465void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
466 struct page *pg)
467{
468
469
470
471
472 preempt_disable();
473 flush_dcache_page_asm(__pa(vfrom), vaddr);
474 copy_page_asm(vto, vfrom);
475 preempt_enable();
476}
477EXPORT_SYMBOL(copy_user_page);
478
479
480
481
482
483int __flush_tlb_range(unsigned long sid, unsigned long start,
484 unsigned long end)
485{
486 unsigned long flags;
487
488 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
489 end - start >= parisc_tlb_flush_threshold) {
490 flush_tlb_all();
491 return 1;
492 }
493
494
495
496
497 while (start < end) {
498 purge_tlb_start(flags);
499 mtsp(sid, 1);
500 pdtlb(start);
501 pitlb(start);
502 purge_tlb_end(flags);
503 start += PAGE_SIZE;
504 }
505 return 0;
506}
507
508static void cacheflush_h_tmp_function(void *dummy)
509{
510 flush_cache_all_local();
511}
512
513void flush_cache_all(void)
514{
515 on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
516}
517
518static inline unsigned long mm_total_size(struct mm_struct *mm)
519{
520 struct vm_area_struct *vma;
521 unsigned long usize = 0;
522
523 for (vma = mm->mmap; vma; vma = vma->vm_next)
524 usize += vma->vm_end - vma->vm_start;
525 return usize;
526}
527
528static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
529{
530 pte_t *ptep = NULL;
531
532 if (!pgd_none(*pgd)) {
533 p4d_t *p4d = p4d_offset(pgd, addr);
534 if (!p4d_none(*p4d)) {
535 pud_t *pud = pud_offset(p4d, addr);
536 if (!pud_none(*pud)) {
537 pmd_t *pmd = pmd_offset(pud, addr);
538 if (!pmd_none(*pmd))
539 ptep = pte_offset_map(pmd, addr);
540 }
541 }
542 }
543 return ptep;
544}
545
546void flush_cache_mm(struct mm_struct *mm)
547{
548 struct vm_area_struct *vma;
549 pgd_t *pgd;
550
551
552
553 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
554 mm_total_size(mm) >= parisc_cache_flush_threshold) {
555 if (mm->context)
556 flush_tlb_all();
557 flush_cache_all();
558 return;
559 }
560
561 if (mm->context == mfsp(3)) {
562 for (vma = mm->mmap; vma; vma = vma->vm_next) {
563 flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
564 if (vma->vm_flags & VM_EXEC)
565 flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
566 flush_tlb_range(vma, vma->vm_start, vma->vm_end);
567 }
568 return;
569 }
570
571 pgd = mm->pgd;
572 for (vma = mm->mmap; vma; vma = vma->vm_next) {
573 unsigned long addr;
574
575 for (addr = vma->vm_start; addr < vma->vm_end;
576 addr += PAGE_SIZE) {
577 unsigned long pfn;
578 pte_t *ptep = get_ptep(pgd, addr);
579 if (!ptep)
580 continue;
581 pfn = pte_pfn(*ptep);
582 if (!pfn_valid(pfn))
583 continue;
584 if (unlikely(mm->context)) {
585 flush_tlb_page(vma, addr);
586 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
587 } else {
588 __purge_cache_page(vma, addr, PFN_PHYS(pfn));
589 }
590 }
591 }
592}
593
594void flush_cache_range(struct vm_area_struct *vma,
595 unsigned long start, unsigned long end)
596{
597 pgd_t *pgd;
598 unsigned long addr;
599
600 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
601 end - start >= parisc_cache_flush_threshold) {
602 if (vma->vm_mm->context)
603 flush_tlb_range(vma, start, end);
604 flush_cache_all();
605 return;
606 }
607
608 if (vma->vm_mm->context == mfsp(3)) {
609 flush_user_dcache_range_asm(start, end);
610 if (vma->vm_flags & VM_EXEC)
611 flush_user_icache_range_asm(start, end);
612 flush_tlb_range(vma, start, end);
613 return;
614 }
615
616 pgd = vma->vm_mm->pgd;
617 for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
618 unsigned long pfn;
619 pte_t *ptep = get_ptep(pgd, addr);
620 if (!ptep)
621 continue;
622 pfn = pte_pfn(*ptep);
623 if (pfn_valid(pfn)) {
624 if (unlikely(vma->vm_mm->context)) {
625 flush_tlb_page(vma, addr);
626 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
627 } else {
628 __purge_cache_page(vma, addr, PFN_PHYS(pfn));
629 }
630 }
631 }
632}
633
634void
635flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
636{
637 if (pfn_valid(pfn)) {
638 if (likely(vma->vm_mm->context)) {
639 flush_tlb_page(vma, vmaddr);
640 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
641 } else {
642 __purge_cache_page(vma, vmaddr, PFN_PHYS(pfn));
643 }
644 }
645}
646
647void flush_kernel_vmap_range(void *vaddr, int size)
648{
649 unsigned long start = (unsigned long)vaddr;
650 unsigned long end = start + size;
651
652 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
653 (unsigned long)size >= parisc_cache_flush_threshold) {
654 flush_tlb_kernel_range(start, end);
655 flush_data_cache();
656 return;
657 }
658
659 flush_kernel_dcache_range_asm(start, end);
660 flush_tlb_kernel_range(start, end);
661}
662EXPORT_SYMBOL(flush_kernel_vmap_range);
663
664void invalidate_kernel_vmap_range(void *vaddr, int size)
665{
666 unsigned long start = (unsigned long)vaddr;
667 unsigned long end = start + size;
668
669 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
670 (unsigned long)size >= parisc_cache_flush_threshold) {
671 flush_tlb_kernel_range(start, end);
672 flush_data_cache();
673 return;
674 }
675
676 purge_kernel_dcache_range_asm(start, end);
677 flush_tlb_kernel_range(start, end);
678}
679EXPORT_SYMBOL(invalidate_kernel_vmap_range);
680