LXR linux/arch/powerpc/include/asm/cpm1.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * MPC8xx Communication Processor Module.
   4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   5 *
   6 * This file contains structures and information for the communication
   7 * processor channels.  Some CPM control and status is available
   8 * through the MPC8xx internal memory map.  See immap.h for details.
   9 * This file only contains what I need for the moment, not the total
  10 * CPM capabilities.  I (or someone else) will add definitions as they
  11 * are needed.  -- Dan
  12 *
  13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  14 * bytes of the DP RAM and relocates the I2C parameter area to the
  15 * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  16 * or other use.
  17 */
  18#ifndef __CPM1__
  19#define __CPM1__
  20
  21#include <linux/init.h>
  22#include <asm/8xx_immap.h>
  23#include <asm/ptrace.h>
  24#include <asm/cpm.h>
  25
  26/* CPM Command register.
  27*/
  28#define CPM_CR_RST      ((ushort)0x8000)
  29#define CPM_CR_OPCODE   ((ushort)0x0f00)
  30#define CPM_CR_CHAN     ((ushort)0x00f0)
  31#define CPM_CR_FLG      ((ushort)0x0001)
  32
  33/* Channel numbers.
  34*/
  35#define CPM_CR_CH_SCC1          ((ushort)0x0000)
  36#define CPM_CR_CH_I2C           ((ushort)0x0001)        /* I2C and IDMA1 */
  37#define CPM_CR_CH_SCC2          ((ushort)0x0004)
  38#define CPM_CR_CH_SPI           ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
  39#define CPM_CR_CH_TIMER         CPM_CR_CH_SPI
  40#define CPM_CR_CH_SCC3          ((ushort)0x0008)
  41#define CPM_CR_CH_SMC1          ((ushort)0x0009)        /* SMC1 / DSP1 */
  42#define CPM_CR_CH_SCC4          ((ushort)0x000c)
  43#define CPM_CR_CH_SMC2          ((ushort)0x000d)        /* SMC2 / DSP2 */
  44
  45#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  46
  47/* Export the base address of the communication processor registers
  48 * and dual port ram.
  49 */
  50extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
  51
  52#define cpm_dpalloc cpm_muram_alloc
  53#define cpm_dpfree cpm_muram_free
  54#define cpm_dpram_addr cpm_muram_addr
  55#define cpm_dpram_phys cpm_muram_dma
  56
  57extern void cpm_setbrg(uint brg, uint rate);
  58
  59extern void __init cpm_load_patch(cpm8xx_t *cp);
  60
  61extern void cpm_reset(void);
  62
  63/* Parameter RAM offsets.
  64*/
  65#define PROFF_SCC1      ((uint)0x0000)
  66#define PROFF_IIC       ((uint)0x0080)
  67#define PROFF_SCC2      ((uint)0x0100)
  68#define PROFF_SPI       ((uint)0x0180)
  69#define PROFF_SCC3      ((uint)0x0200)
  70#define PROFF_SMC1      ((uint)0x0280)
  71#define PROFF_DSP1      ((uint)0x02c0)
  72#define PROFF_SCC4      ((uint)0x0300)
  73#define PROFF_SMC2      ((uint)0x0380)
  74
  75/* Define enough so I can at least use the serial port as a UART.
  76 * The MBX uses SMC1 as the host serial port.
  77 */
  78typedef struct smc_uart {
  79        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
  80        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
  81        u_char  smc_rfcr;       /* Rx function code */
  82        u_char  smc_tfcr;       /* Tx function code */
  83        ushort  smc_mrblr;      /* Max receive buffer length */
  84        uint    smc_rstate;     /* Internal */
  85        uint    smc_idp;        /* Internal */
  86        ushort  smc_rbptr;      /* Internal */
  87        ushort  smc_ibc;        /* Internal */
  88        uint    smc_rxtmp;      /* Internal */
  89        uint    smc_tstate;     /* Internal */
  90        uint    smc_tdp;        /* Internal */
  91        ushort  smc_tbptr;      /* Internal */
  92        ushort  smc_tbc;        /* Internal */
  93        uint    smc_txtmp;      /* Internal */
  94        ushort  smc_maxidl;     /* Maximum idle characters */
  95        ushort  smc_tmpidl;     /* Temporary idle counter */
  96        ushort  smc_brklen;     /* Last received break length */
  97        ushort  smc_brkec;      /* rcv'd break condition counter */
  98        ushort  smc_brkcr;      /* xmt break count register */
  99        ushort  smc_rmask;      /* Temporary bit mask */
 100        char    res1[8];        /* Reserved */
 101        ushort  smc_rpbase;     /* Relocation pointer */
 102} smc_uart_t;
 103
 104/* Function code bits.
 105*/
 106#define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 107
 108/* SMC uart mode register.
 109*/
 110#define SMCMR_REN       ((ushort)0x0001)
 111#define SMCMR_TEN       ((ushort)0x0002)
 112#define SMCMR_DM        ((ushort)0x000c)
 113#define SMCMR_SM_GCI    ((ushort)0x0000)
 114#define SMCMR_SM_UART   ((ushort)0x0020)
 115#define SMCMR_SM_TRANS  ((ushort)0x0030)
 116#define SMCMR_SM_MASK   ((ushort)0x0030)
 117#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 118#define SMCMR_REVD      SMCMR_PM_EVEN
 119#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 120#define SMCMR_BS        SMCMR_PEN
 121#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 122#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 123#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 124
 125/* SMC2 as Centronics parallel printer.  It is half duplex, in that
 126 * it can only receive or transmit.  The parameter ram values for
 127 * each direction are either unique or properly overlap, so we can
 128 * include them in one structure.
 129 */
 130typedef struct smc_centronics {
 131        ushort  scent_rbase;
 132        ushort  scent_tbase;
 133        u_char  scent_cfcr;
 134        u_char  scent_smask;
 135        ushort  scent_mrblr;
 136        uint    scent_rstate;
 137        uint    scent_r_ptr;
 138        ushort  scent_rbptr;
 139        ushort  scent_r_cnt;
 140        uint    scent_rtemp;
 141        uint    scent_tstate;
 142        uint    scent_t_ptr;
 143        ushort  scent_tbptr;
 144        ushort  scent_t_cnt;
 145        uint    scent_ttemp;
 146        ushort  scent_max_sl;
 147        ushort  scent_sl_cnt;
 148        ushort  scent_character1;
 149        ushort  scent_character2;
 150        ushort  scent_character3;
 151        ushort  scent_character4;
 152        ushort  scent_character5;
 153        ushort  scent_character6;
 154        ushort  scent_character7;
 155        ushort  scent_character8;
 156        ushort  scent_rccm;
 157        ushort  scent_rccr;
 158} smc_cent_t;
 159
 160/* Centronics Status Mask Register.
 161*/
 162#define SMC_CENT_F      ((u_char)0x08)
 163#define SMC_CENT_PE     ((u_char)0x04)
 164#define SMC_CENT_S      ((u_char)0x02)
 165
 166/* SMC Event and Mask register.
 167*/
 168#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 169#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 170#define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 171#define SMCM_BSY        ((unsigned char)0x04)
 172#define SMCM_TX         ((unsigned char)0x02)
 173#define SMCM_RX         ((unsigned char)0x01)
 174
 175/* Baud rate generators.
 176*/
 177#define CPM_BRG_RST             ((uint)0x00020000)
 178#define CPM_BRG_EN              ((uint)0x00010000)
 179#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 180#define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 181#define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 182#define CPM_BRG_ATB             ((uint)0x00002000)
 183#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 184#define CPM_BRG_DIV16           ((uint)0x00000001)
 185
 186/* SI Clock Route Register
 187*/
 188#define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 189#define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 190#define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 191#define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 192#define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 193#define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 194#define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 195#define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 196
 197/* SCCs.
 198*/
 199#define SCC_GSMRH_IRP           ((uint)0x00040000)
 200#define SCC_GSMRH_GDE           ((uint)0x00010000)
 201#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 202#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 203#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 204#define SCC_GSMRH_REVD          ((uint)0x00002000)
 205#define SCC_GSMRH_TRX           ((uint)0x00001000)
 206#define SCC_GSMRH_TTX           ((uint)0x00000800)
 207#define SCC_GSMRH_CDP           ((uint)0x00000400)
 208#define SCC_GSMRH_CTSP          ((uint)0x00000200)
 209#define SCC_GSMRH_CDS           ((uint)0x00000100)
 210#define SCC_GSMRH_CTSS          ((uint)0x00000080)
 211#define SCC_GSMRH_TFL           ((uint)0x00000040)
 212#define SCC_GSMRH_RFW           ((uint)0x00000020)
 213#define SCC_GSMRH_TXSY          ((uint)0x00000010)
 214#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 215#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 216#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 217#define SCC_GSMRH_RTSM          ((uint)0x00000002)
 218#define SCC_GSMRH_RSYN          ((uint)0x00000001)
 219
 220#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 221#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 222#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 223#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 224#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 225#define SCC_GSMRL_TCI           ((uint)0x10000000)
 226#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 227#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 228#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 229#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 230#define SCC_GSMRL_RINV          ((uint)0x02000000)
 231#define SCC_GSMRL_TINV          ((uint)0x01000000)
 232#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 233#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 234#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 235#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 236#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 237#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 238#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 239#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 240#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 241#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 242#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 243#define SCC_GSMRL_TEND          ((uint)0x00040000)
 244#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 245#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 246#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 247#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 248#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 249#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 250#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 251#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 252#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 253#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 254#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 255#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 256#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 257#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 258#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 259#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 260#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 261#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 262#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 263#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 264#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 265#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 266#define SCC_GSMRL_ENR           ((uint)0x00000020)
 267#define SCC_GSMRL_ENT           ((uint)0x00000010)
 268#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 269#define SCC_GSMRL_MODE_QMC      ((uint)0x0000000a)
 270#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 271#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 272#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 273#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 274#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 275#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 276#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 277#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 278#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 279
 280#define SCC_TODR_TOD            ((ushort)0x8000)
 281
 282/* SCC Event and Mask register.
 283*/
 284#define SCCM_TXE        ((unsigned char)0x10)
 285#define SCCM_BSY        ((unsigned char)0x04)
 286#define SCCM_TX         ((unsigned char)0x02)
 287#define SCCM_RX         ((unsigned char)0x01)
 288
 289typedef struct scc_param {
 290        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 291        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 292        u_char  scc_rfcr;       /* Rx function code */
 293        u_char  scc_tfcr;       /* Tx function code */
 294        ushort  scc_mrblr;      /* Max receive buffer length */
 295        uint    scc_rstate;     /* Internal */
 296        uint    scc_idp;        /* Internal */
 297        ushort  scc_rbptr;      /* Internal */
 298        ushort  scc_ibc;        /* Internal */
 299        uint    scc_rxtmp;      /* Internal */
 300        uint    scc_tstate;     /* Internal */
 301        uint    scc_tdp;        /* Internal */
 302        ushort  scc_tbptr;      /* Internal */
 303        ushort  scc_tbc;        /* Internal */
 304        uint    scc_txtmp;      /* Internal */
 305        uint    scc_rcrc;       /* Internal */
 306        uint    scc_tcrc;       /* Internal */
 307} sccp_t;
 308
 309/* Function code bits.
 310*/
 311#define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 312
 313/* CPM Ethernet through SCCx.
 314 */
 315typedef struct scc_enet {
 316        sccp_t  sen_genscc;
 317        uint    sen_cpres;      /* Preset CRC */
 318        uint    sen_cmask;      /* Constant mask for CRC */
 319        uint    sen_crcec;      /* CRC Error counter */
 320        uint    sen_alec;       /* alignment error counter */
 321        uint    sen_disfc;      /* discard frame counter */
 322        ushort  sen_pads;       /* Tx short frame pad character */
 323        ushort  sen_retlim;     /* Retry limit threshold */
 324        ushort  sen_retcnt;     /* Retry limit counter */
 325        ushort  sen_maxflr;     /* maximum frame length register */
 326        ushort  sen_minflr;     /* minimum frame length register */
 327        ushort  sen_maxd1;      /* maximum DMA1 length */
 328        ushort  sen_maxd2;      /* maximum DMA2 length */
 329        ushort  sen_maxd;       /* Rx max DMA */
 330        ushort  sen_dmacnt;     /* Rx DMA counter */
 331        ushort  sen_maxb;       /* Max BD byte count */
 332        ushort  sen_gaddr1;     /* Group address filter */
 333        ushort  sen_gaddr2;
 334        ushort  sen_gaddr3;
 335        ushort  sen_gaddr4;
 336        uint    sen_tbuf0data0; /* Save area 0 - current frame */
 337        uint    sen_tbuf0data1; /* Save area 1 - current frame */
 338        uint    sen_tbuf0rba;   /* Internal */
 339        uint    sen_tbuf0crc;   /* Internal */
 340        ushort  sen_tbuf0bcnt;  /* Internal */
 341        ushort  sen_paddrh;     /* physical address (MSB) */
 342        ushort  sen_paddrm;
 343        ushort  sen_paddrl;     /* physical address (LSB) */
 344        ushort  sen_pper;       /* persistence */
 345        ushort  sen_rfbdptr;    /* Rx first BD pointer */
 346        ushort  sen_tfbdptr;    /* Tx first BD pointer */
 347        ushort  sen_tlbdptr;    /* Tx last BD pointer */
 348        uint    sen_tbuf1data0; /* Save area 0 - current frame */
 349        uint    sen_tbuf1data1; /* Save area 1 - current frame */
 350        uint    sen_tbuf1rba;   /* Internal */
 351        uint    sen_tbuf1crc;   /* Internal */
 352        ushort  sen_tbuf1bcnt;  /* Internal */
 353        ushort  sen_txlen;      /* Tx Frame length counter */
 354        ushort  sen_iaddr1;     /* Individual address filter */
 355        ushort  sen_iaddr2;
 356        ushort  sen_iaddr3;
 357        ushort  sen_iaddr4;
 358        ushort  sen_boffcnt;    /* Backoff counter */
 359
 360        /* NOTE: Some versions of the manual have the following items
 361         * incorrectly documented.  Below is the proper order.
 362         */
 363        ushort  sen_taddrh;     /* temp address (MSB) */
 364        ushort  sen_taddrm;
 365        ushort  sen_taddrl;     /* temp address (LSB) */
 366} scc_enet_t;
 367
 368/* SCC Event register as used by Ethernet.
 369*/
 370#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 371#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 372#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 373#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 374#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 375#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 376
 377/* SCC Mode Register (PMSR) as used by Ethernet.
 378*/
 379#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 380#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 381#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 382#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 383#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 384#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 385#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 386#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 387#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 388#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 389#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 390#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 391#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 392
 393/* SCC as UART
 394*/
 395typedef struct scc_uart {
 396        sccp_t  scc_genscc;
 397        char    res1[8];        /* Reserved */
 398        ushort  scc_maxidl;     /* Maximum idle chars */
 399        ushort  scc_idlc;       /* temp idle counter */
 400        ushort  scc_brkcr;      /* Break count register */
 401        ushort  scc_parec;      /* receive parity error counter */
 402        ushort  scc_frmec;      /* receive framing error counter */
 403        ushort  scc_nosec;      /* receive noise counter */
 404        ushort  scc_brkec;      /* receive break condition counter */
 405        ushort  scc_brkln;      /* last received break length */
 406        ushort  scc_uaddr1;     /* UART address character 1 */
 407        ushort  scc_uaddr2;     /* UART address character 2 */
 408        ushort  scc_rtemp;      /* Temp storage */
 409        ushort  scc_toseq;      /* Transmit out of sequence char */
 410        ushort  scc_char1;      /* control character 1 */
 411        ushort  scc_char2;      /* control character 2 */
 412        ushort  scc_char3;      /* control character 3 */
 413        ushort  scc_char4;      /* control character 4 */
 414        ushort  scc_char5;      /* control character 5 */
 415        ushort  scc_char6;      /* control character 6 */
 416        ushort  scc_char7;      /* control character 7 */
 417        ushort  scc_char8;      /* control character 8 */
 418        ushort  scc_rccm;       /* receive control character mask */
 419        ushort  scc_rccr;       /* receive control character register */
 420        ushort  scc_rlbc;       /* receive last break character */
 421} scc_uart_t;
 422
 423/* SCC Event and Mask registers when it is used as a UART.
 424*/
 425#define UART_SCCM_GLR           ((ushort)0x1000)
 426#define UART_SCCM_GLT           ((ushort)0x0800)
 427#define UART_SCCM_AB            ((ushort)0x0200)
 428#define UART_SCCM_IDL           ((ushort)0x0100)
 429#define UART_SCCM_GRA           ((ushort)0x0080)
 430#define UART_SCCM_BRKE          ((ushort)0x0040)
 431#define UART_SCCM_BRKS          ((ushort)0x0020)
 432#define UART_SCCM_CCR           ((ushort)0x0008)
 433#define UART_SCCM_BSY           ((ushort)0x0004)
 434#define UART_SCCM_TX            ((ushort)0x0002)
 435#define UART_SCCM_RX            ((ushort)0x0001)
 436
 437/* The SCC PMSR when used as a UART.
 438*/
 439#define SCU_PSMR_FLC            ((ushort)0x8000)
 440#define SCU_PSMR_SL             ((ushort)0x4000)
 441#define SCU_PSMR_CL             ((ushort)0x3000)
 442#define SCU_PSMR_UM             ((ushort)0x0c00)
 443#define SCU_PSMR_FRZ            ((ushort)0x0200)
 444#define SCU_PSMR_RZS            ((ushort)0x0100)
 445#define SCU_PSMR_SYN            ((ushort)0x0080)
 446#define SCU_PSMR_DRT            ((ushort)0x0040)
 447#define SCU_PSMR_PEN            ((ushort)0x0010)
 448#define SCU_PSMR_RPM            ((ushort)0x000c)
 449#define SCU_PSMR_REVP           ((ushort)0x0008)
 450#define SCU_PSMR_TPM            ((ushort)0x0003)
 451#define SCU_PSMR_TEVP           ((ushort)0x0002)
 452
 453/* CPM Transparent mode SCC.
 454 */
 455typedef struct scc_trans {
 456        sccp_t  st_genscc;
 457        uint    st_cpres;       /* Preset CRC */
 458        uint    st_cmask;       /* Constant mask for CRC */
 459} scc_trans_t;
 460
 461/* IIC parameter RAM.
 462*/
 463typedef struct iic {
 464        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
 465        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
 466        u_char  iic_rfcr;       /* Rx function code */
 467        u_char  iic_tfcr;       /* Tx function code */
 468        ushort  iic_mrblr;      /* Max receive buffer length */
 469        uint    iic_rstate;     /* Internal */
 470        uint    iic_rdp;        /* Internal */
 471        ushort  iic_rbptr;      /* Internal */
 472        ushort  iic_rbc;        /* Internal */
 473        uint    iic_rxtmp;      /* Internal */
 474        uint    iic_tstate;     /* Internal */
 475        uint    iic_tdp;        /* Internal */
 476        ushort  iic_tbptr;      /* Internal */
 477        ushort  iic_tbc;        /* Internal */
 478        uint    iic_txtmp;      /* Internal */
 479        char    res1[4];        /* Reserved */
 480        ushort  iic_rpbase;     /* Relocation pointer */
 481        char    res2[2];        /* Reserved */
 482} iic_t;
 483
 484/*
 485 * RISC Controller Configuration Register definitons
 486 */
 487#define RCCR_TIME       0x8000                  /* RISC Timer Enable */
 488#define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)       /* RISC Timer Period */
 489#define RCCR_TIME_MASK  0x00FF                  /* not RISC Timer related bits */
 490
 491/* RISC Timer Parameter RAM offset */
 492#define PROFF_RTMR      ((uint)0x01B0)
 493
 494typedef struct risc_timer_pram {
 495        unsigned short  tm_base;        /* RISC Timer Table Base Address */
 496        unsigned short  tm_ptr;         /* RISC Timer Table Pointer (internal) */
 497        unsigned short  r_tmr;          /* RISC Timer Mode Register */
 498        unsigned short  r_tmv;          /* RISC Timer Valid Register */
 499        unsigned long   tm_cmd;         /* RISC Timer Command Register */
 500        unsigned long   tm_cnt;         /* RISC Timer Internal Count */
 501} rt_pram_t;
 502
 503/* Bits in RISC Timer Command Register */
 504#define TM_CMD_VALID    0x80000000      /* Valid - Enables the timer */
 505#define TM_CMD_RESTART  0x40000000      /* Restart - for automatic restart */
 506#define TM_CMD_PWM      0x20000000      /* Run in Pulse Width Modulation Mode */
 507#define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
 508#define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
 509
 510/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 511 * channels or devices.  All of these are presented to the PPC core
 512 * as a single interrupt.  The CPM interrupt handler dispatches its
 513 * own handlers, in a similar fashion to the PPC core handler.  We
 514 * use the table as defined in the manuals (i.e. no special high
 515 * priority and SCC1 == SCCa, etc...).
 516 */
 517#define CPMVEC_NR               32
 518#define CPMVEC_PIO_PC15         ((ushort)0x1f)
 519#define CPMVEC_SCC1             ((ushort)0x1e)
 520#define CPMVEC_SCC2             ((ushort)0x1d)
 521#define CPMVEC_SCC3             ((ushort)0x1c)
 522#define CPMVEC_SCC4             ((ushort)0x1b)
 523#define CPMVEC_PIO_PC14         ((ushort)0x1a)
 524#define CPMVEC_TIMER1           ((ushort)0x19)
 525#define CPMVEC_PIO_PC13         ((ushort)0x18)
 526#define CPMVEC_PIO_PC12         ((ushort)0x17)
 527#define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
 528#define CPMVEC_IDMA1            ((ushort)0x15)
 529#define CPMVEC_IDMA2            ((ushort)0x14)
 530#define CPMVEC_TIMER2           ((ushort)0x12)
 531#define CPMVEC_RISCTIMER        ((ushort)0x11)
 532#define CPMVEC_I2C              ((ushort)0x10)
 533#define CPMVEC_PIO_PC11         ((ushort)0x0f)
 534#define CPMVEC_PIO_PC10         ((ushort)0x0e)
 535#define CPMVEC_TIMER3           ((ushort)0x0c)
 536#define CPMVEC_PIO_PC9          ((ushort)0x0b)
 537#define CPMVEC_PIO_PC8          ((ushort)0x0a)
 538#define CPMVEC_PIO_PC7          ((ushort)0x09)
 539#define CPMVEC_TIMER4           ((ushort)0x07)
 540#define CPMVEC_PIO_PC6          ((ushort)0x06)
 541#define CPMVEC_SPI              ((ushort)0x05)
 542#define CPMVEC_SMC1             ((ushort)0x04)
 543#define CPMVEC_SMC2             ((ushort)0x03)
 544#define CPMVEC_PIO_PC5          ((ushort)0x02)
 545#define CPMVEC_PIO_PC4          ((ushort)0x01)
 546#define CPMVEC_ERROR            ((ushort)0x00)
 547
 548/* CPM interrupt configuration vector.
 549*/
 550#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
 551#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 552#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 553#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
 554#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
 555#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
 556#define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
 557#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
 558
 559#define CPM_PIN_INPUT     0
 560#define CPM_PIN_OUTPUT    1
 561#define CPM_PIN_PRIMARY   0
 562#define CPM_PIN_SECONDARY 2
 563#define CPM_PIN_GPIO      4
 564#define CPM_PIN_OPENDRAIN 8
 565#define CPM_PIN_FALLEDGE  16
 566#define CPM_PIN_ANYEDGE   0
 567
 568enum cpm_port {
 569        CPM_PORTA,
 570        CPM_PORTB,
 571        CPM_PORTC,
 572        CPM_PORTD,
 573        CPM_PORTE,
 574};
 575
 576void cpm1_set_pin(enum cpm_port port, int pin, int flags);
 577
 578enum cpm_clk_dir {
 579        CPM_CLK_RX,
 580        CPM_CLK_TX,
 581        CPM_CLK_RTX
 582};
 583
 584enum cpm_clk_target {
 585        CPM_CLK_SCC1,
 586        CPM_CLK_SCC2,
 587        CPM_CLK_SCC3,
 588        CPM_CLK_SCC4,
 589        CPM_CLK_SMC1,
 590        CPM_CLK_SMC2,
 591};
 592
 593enum cpm_clk {
 594        CPM_BRG1,       /* Baud Rate Generator  1 */
 595        CPM_BRG2,       /* Baud Rate Generator  2 */
 596        CPM_BRG3,       /* Baud Rate Generator  3 */
 597        CPM_BRG4,       /* Baud Rate Generator  4 */
 598        CPM_CLK1,       /* Clock  1 */
 599        CPM_CLK2,       /* Clock  2 */
 600        CPM_CLK3,       /* Clock  3 */
 601        CPM_CLK4,       /* Clock  4 */
 602        CPM_CLK5,       /* Clock  5 */
 603        CPM_CLK6,       /* Clock  6 */
 604        CPM_CLK7,       /* Clock  7 */
 605        CPM_CLK8,       /* Clock  8 */
 606};
 607
 608int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
 609int cpm1_gpiochip_add16(struct device *dev);
 610int cpm1_gpiochip_add32(struct device *dev);
 611
 612#endif /* __CPM1__ */
 613