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8#ifndef _ASM_POWERPC_OPAL_H
9#define _ASM_POWERPC_OPAL_H
10
11#include <asm/opal-api.h>
12
13#ifndef __ASSEMBLY__
14
15#include <linux/notifier.h>
16
17
18#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
19
20
21#define OPAL_BUSY_DELAY_MS 10
22
23
24extern struct kobject *opal_kobj;
25
26
27extern struct device_node *opal_node;
28
29
30int64_t opal_invalid_call(void);
31int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
32 uint64_t lpcr);
33int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
34 uint64_t addr, uint64_t PE_mask);
35int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
36 uint64_t PE_handle);
37int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
38 uint64_t rate_phys, uint32_t size);
39
40int64_t opal_console_write(int64_t term_number, __be64 *length,
41 const uint8_t *buffer);
42int64_t opal_console_read(int64_t term_number, __be64 *length,
43 uint8_t *buffer);
44int64_t opal_console_write_buffer_space(int64_t term_number,
45 __be64 *length);
46int64_t opal_console_flush(int64_t term_number);
47int64_t opal_rtc_read(__be32 *year_month_day,
48 __be64 *hour_minute_second_millisecond);
49int64_t opal_rtc_write(uint32_t year_month_day,
50 uint64_t hour_minute_second_millisecond);
51int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
52int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
53 uint32_t hour_min);
54int64_t opal_cec_power_down(uint64_t request);
55int64_t opal_cec_reboot(void);
56int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
57int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
58int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
59int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
60int64_t opal_poll_events(__be64 *outstanding_event_mask);
61int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
62 uint64_t tce_mem_size);
63int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
64 uint64_t tce_mem_size);
65int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
66 uint64_t offset, uint8_t *data);
67int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
68 uint64_t offset, __be16 *data);
69int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
70 uint64_t offset, __be32 *data);
71int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
72 uint64_t offset, uint8_t data);
73int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
74 uint64_t offset, uint16_t data);
75int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
76 uint64_t offset, uint32_t data);
77int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
78int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
79int64_t opal_register_exception_handler(uint64_t opal_exception,
80 uint64_t handler_address,
81 uint64_t glue_cache_line);
82int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
83 uint8_t *freeze_state,
84 __be16 *pci_error_type,
85 __be64 *phb_status);
86int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
87 uint64_t eeh_action_token);
88int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
89 uint64_t eeh_action_token);
90int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
91 uint32_t func, uint64_t addr, uint64_t mask);
92int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
93
94
95
96int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
97 uint16_t window_num, uint16_t enable);
98int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
99 uint16_t window_num,
100 uint64_t starting_real_address,
101 uint64_t starting_pci_address,
102 uint64_t size);
103int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
104 uint16_t window_type, uint16_t window_num,
105 uint16_t segment_num);
106int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
107 uint64_t ivt_addr, uint64_t ivt_len,
108 uint64_t reject_array_addr,
109 uint64_t peltv_addr);
110int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
111 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
112 uint8_t pe_action);
113int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
114 uint8_t state);
115int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
116int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
117 uint32_t state);
118int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
119 uint8_t *p_bit, uint8_t *q_bit);
120int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
121 uint8_t p_bit, uint8_t q_bit);
122int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
123int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
124 uint32_t xive_num);
125int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
126 __be32 *interrupt_source_number);
127int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
128 uint8_t msi_range, __be32 *msi_address,
129 __be32 *message_data);
130int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
131 uint32_t xive_num, uint8_t msi_range,
132 __be64 *msi_address, __be32 *message_data);
133int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
134int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
135int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
136int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
137 uint16_t tce_levels, uint64_t tce_table_addr,
138 uint64_t tce_table_size, uint64_t tce_page_size);
139int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
140 uint16_t dma_window_number, uint64_t pci_start_addr,
141 uint64_t pci_mem_size);
142int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
143
144int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
145 uint64_t diag_buffer_len);
146int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
147 uint64_t diag_buffer_len);
148int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
149 uint64_t diag_buffer_len);
150int64_t opal_pci_fence_phb(uint64_t phb_id);
151int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
152int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
153int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
154int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
155int64_t opal_get_dpo_status(__be64 *dpo_timeout);
156int64_t opal_set_system_attention_led(uint8_t led_action);
157int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
158 __be16 *pci_error_type, __be16 *severity);
159int64_t opal_pci_poll(uint64_t id);
160int64_t opal_return_cpu(void);
161int64_t opal_check_token(uint64_t token);
162int64_t opal_reinit_cpus(uint64_t flags);
163
164int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
165int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
166
167int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
168 uint32_t addr, uint32_t data, uint32_t sz);
169int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
170 uint32_t addr, __be32 *data, uint32_t sz);
171
172int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
173int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
174int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
175int64_t opal_send_ack_elog(uint64_t log_id);
176void opal_resend_pending_logs(void);
177
178int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
179int64_t opal_manage_flash(uint8_t op);
180int64_t opal_update_flash(uint64_t blk_list);
181int64_t opal_dump_init(uint8_t dump_type);
182int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
183int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
184int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
185int64_t opal_dump_ack(uint32_t dump_id);
186int64_t opal_dump_resend_notification(void);
187
188int64_t opal_get_msg(uint64_t buffer, uint64_t size);
189int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
190 uint64_t num_lines);
191int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
192int64_t opal_sync_host_reboot(void);
193int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
194 uint64_t length);
195int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
196 uint64_t length);
197int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
198int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
199int64_t opal_handle_hmi(void);
200int64_t opal_handle_hmi2(__be64 *out_flags);
201int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
202int64_t opal_unregister_dump_region(uint32_t id);
203int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
204int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
205int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
206int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
207int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
208int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
209 uint64_t msg_len);
210int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
211 uint64_t *msg_len);
212int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
213 struct opal_i2c_request *oreq);
214int64_t opal_prd_msg(struct opal_prd_msg *msg);
215int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
216 __be64 *led_value, __be64 *max_led_type);
217int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
218 const u64 led_value, __be64 *max_led_type);
219
220int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
221 uint64_t size, uint64_t token);
222int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
223 uint64_t size, uint64_t token);
224int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
225 uint64_t token);
226int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
227int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
228int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
229int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
230 uint64_t data);
231int64_t opal_pci_poll2(uint64_t id, uint64_t data);
232
233int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
234int64_t opal_int_set_cppr(uint8_t cppr);
235int64_t opal_int_eoi(uint32_t xirr);
236int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
237int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
238 uint32_t pe_num, uint32_t tce_size,
239 uint64_t dma_addr, uint32_t npages);
240int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
241int64_t opal_xive_reset(uint64_t version);
242int64_t opal_xive_get_irq_info(uint32_t girq,
243 __be64 *out_flags,
244 __be64 *out_eoi_page,
245 __be64 *out_trig_page,
246 __be32 *out_esb_shift,
247 __be32 *out_src_chip);
248int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
249 uint8_t *out_prio, __be32 *out_lirq);
250int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
251 uint32_t lirq);
252int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
253 __be64 *out_qpage,
254 __be64 *out_qsize,
255 __be64 *out_qeoi_page,
256 __be32 *out_escalate_irq,
257 __be64 *out_qflags);
258int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
259 uint64_t qpage,
260 uint64_t qsize,
261 uint64_t qflags);
262int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
263int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
264int64_t opal_xive_free_vp_block(uint64_t vp);
265int64_t opal_xive_get_vp_info(uint64_t vp,
266 __be64 *out_flags,
267 __be64 *out_cam_value,
268 __be64 *out_report_cl_pair,
269 __be32 *out_chip_id);
270int64_t opal_xive_set_vp_info(uint64_t vp,
271 uint64_t flags,
272 uint64_t report_cl_pair);
273int64_t opal_xive_allocate_irq_raw(uint32_t chip_id);
274int64_t opal_xive_free_irq(uint32_t girq);
275int64_t opal_xive_sync(uint32_t type, uint32_t id);
276int64_t opal_xive_dump(uint32_t type, uint32_t id);
277int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
278 __be32 *out_qtoggle,
279 __be32 *out_qindex);
280int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
281 uint32_t qtoggle,
282 uint32_t qindex);
283int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
284
285int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
286 uint64_t cpu_pir);
287int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
288int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
289
290int opal_get_powercap(u32 handle, int token, u32 *pcap);
291int opal_set_powercap(u32 handle, int token, u32 pcap);
292int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
293int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
294int opal_sensor_group_clear(u32 group_hndl, int token);
295int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
296int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
297
298int opal_secvar_get(const char *key, uint64_t key_len, u8 *data,
299 uint64_t *data_size);
300int opal_secvar_get_next(const char *key, uint64_t *key_len,
301 uint64_t key_buf_size);
302int opal_secvar_enqueue_update(const char *key, uint64_t key_len, u8 *data,
303 uint64_t data_size);
304
305s64 opal_mpipl_update(enum opal_mpipl_ops op, u64 src, u64 dest, u64 size);
306s64 opal_mpipl_register_tag(enum opal_mpipl_tags tag, u64 addr);
307s64 opal_mpipl_query_tag(enum opal_mpipl_tags tag, __be64 *addr);
308
309s64 opal_signal_system_reset(s32 cpu);
310s64 opal_quiesce(u64 shutdown_type, s32 cpu);
311
312
313extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
314 int depth, void *data);
315extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
316 const char *uname, int depth, void *data);
317extern void opal_configure_cores(void);
318
319extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
320extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
321extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
322extern int opal_flush_chars(uint32_t vtermno, bool wait);
323extern int opal_flush_console(uint32_t vtermno);
324
325extern void hvc_opal_init_early(void);
326
327extern int opal_notifier_register(struct notifier_block *nb);
328extern int opal_notifier_unregister(struct notifier_block *nb);
329
330extern int opal_message_notifier_register(enum opal_msg_type msg_type,
331 struct notifier_block *nb);
332extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
333 struct notifier_block *nb);
334extern void opal_notifier_enable(void);
335extern void opal_notifier_disable(void);
336extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
337
338extern int opal_async_get_token_interruptible(void);
339extern int opal_async_release_token(int token);
340extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
341extern int opal_async_wait_response_interruptible(uint64_t token,
342 struct opal_msg *msg);
343extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
344extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
345extern int sensor_group_enable(u32 grp_hndl, bool enable);
346
347struct rtc_time;
348extern time64_t opal_get_boot_time(void);
349extern void opal_nvram_init(void);
350extern void opal_flash_update_init(void);
351extern void opal_flash_update_print_message(void);
352extern int opal_elog_init(void);
353extern void opal_platform_dump_init(void);
354extern void opal_sys_param_init(void);
355extern void opal_msglog_init(void);
356extern void opal_msglog_sysfs_init(void);
357extern int opal_async_comp_init(void);
358extern int opal_sensor_init(void);
359extern int opal_hmi_handler_init(void);
360extern int opal_event_init(void);
361int opal_power_control_init(void);
362
363extern int opal_machine_check(struct pt_regs *regs);
364extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
365extern int opal_hmi_exception_early(struct pt_regs *regs);
366extern int opal_hmi_exception_early2(struct pt_regs *regs);
367extern int opal_handle_hmi_exception(struct pt_regs *regs);
368
369extern void opal_shutdown(void);
370extern int opal_resync_timebase(void);
371
372extern void opal_lpc_init(void);
373
374extern void opal_kmsg_init(void);
375
376extern int opal_event_request(unsigned int opal_event_nr);
377
378struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
379 unsigned long vmalloc_size);
380void opal_free_sg_list(struct opal_sg_list *sg);
381
382extern int opal_error_code(int rc);
383
384ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
385
386static inline int opal_get_async_rc(struct opal_msg msg)
387{
388 if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
389 return OPAL_PARAMETER;
390 else
391 return be64_to_cpu(msg.params[1]);
392}
393
394void opal_wake_poller(void);
395
396void opal_powercap_init(void);
397void opal_psr_init(void);
398void opal_sensor_groups_init(void);
399
400#endif
401
402#endif
403
