linux/arch/powerpc/include/asm/pci-bridge.h
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   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2#ifndef _ASM_POWERPC_PCI_BRIDGE_H
   3#define _ASM_POWERPC_PCI_BRIDGE_H
   4#ifdef __KERNEL__
   5/*
   6 */
   7#include <linux/pci.h>
   8#include <linux/list.h>
   9#include <linux/ioport.h>
  10#include <linux/numa.h>
  11
  12struct device_node;
  13
  14/*
  15 * PCI controller operations
  16 */
  17struct pci_controller_ops {
  18        void            (*dma_dev_setup)(struct pci_dev *pdev);
  19        void            (*dma_bus_setup)(struct pci_bus *bus);
  20        bool            (*iommu_bypass_supported)(struct pci_dev *pdev,
  21                                u64 mask);
  22
  23        int             (*probe_mode)(struct pci_bus *bus);
  24
  25        /* Called when pci_enable_device() is called. Returns true to
  26         * allow assignment/enabling of the device. */
  27        bool            (*enable_device_hook)(struct pci_dev *pdev);
  28
  29        void            (*disable_device)(struct pci_dev *pdev);
  30
  31        void            (*release_device)(struct pci_dev *pdev);
  32
  33        /* Called during PCI resource reassignment */
  34        resource_size_t (*window_alignment)(struct pci_bus *bus,
  35                                            unsigned long type);
  36        void            (*setup_bridge)(struct pci_bus *bus,
  37                                        unsigned long type);
  38        void            (*reset_secondary_bus)(struct pci_dev *pdev);
  39
  40#ifdef CONFIG_PCI_MSI
  41        int             (*setup_msi_irqs)(struct pci_dev *pdev,
  42                                          int nvec, int type);
  43        void            (*teardown_msi_irqs)(struct pci_dev *pdev);
  44#endif
  45
  46        void            (*shutdown)(struct pci_controller *hose);
  47};
  48
  49/*
  50 * Structure of a PCI controller (host bridge)
  51 */
  52struct pci_controller {
  53        struct pci_bus *bus;
  54        char is_dynamic;
  55#ifdef CONFIG_PPC64
  56        int node;
  57#endif
  58        struct device_node *dn;
  59        struct list_head list_node;
  60        struct device *parent;
  61
  62        int first_busno;
  63        int last_busno;
  64        int self_busno;
  65        struct resource busn;
  66
  67        void __iomem *io_base_virt;
  68#ifdef CONFIG_PPC64
  69        void __iomem *io_base_alloc;
  70#endif
  71        resource_size_t io_base_phys;
  72        resource_size_t pci_io_size;
  73
  74        /* Some machines have a special region to forward the ISA
  75         * "memory" cycles such as VGA memory regions. Left to 0
  76         * if unsupported
  77         */
  78        resource_size_t isa_mem_phys;
  79        resource_size_t isa_mem_size;
  80
  81        struct pci_controller_ops controller_ops;
  82        struct pci_ops *ops;
  83        unsigned int __iomem *cfg_addr;
  84        void __iomem *cfg_data;
  85
  86        /*
  87         * Used for variants of PCI indirect handling and possible quirks:
  88         *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  89         *  EXT_REG - provides access to PCI-e extended registers
  90         *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  91         *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  92         *   to determine which bus number to match on when generating type0
  93         *   config cycles
  94         *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  95         *   hanging if we don't have link and try to do config cycles to
  96         *   anything but the PHB.  Only allow talking to the PHB if this is
  97         *   set.
  98         *  BIG_ENDIAN - cfg_addr is a big endian register
  99         *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
 100         *   the PLB4.  Effectively disable MRM commands by setting this.
 101         *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
 102         *   link status is in a RC PCIe cfg register (vs being a SoC register)
 103         */
 104#define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
 105#define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
 106#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
 107#define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
 108#define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
 109#define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
 110#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
 111        u32 indirect_type;
 112        /* Currently, we limit ourselves to 1 IO range and 3 mem
 113         * ranges since the common pci_bus structure can't handle more
 114         */
 115        struct resource io_resource;
 116        struct resource mem_resources[3];
 117        resource_size_t mem_offset[3];
 118        int global_number;              /* PCI domain number */
 119
 120        resource_size_t dma_window_base_cur;
 121        resource_size_t dma_window_size;
 122
 123#ifdef CONFIG_PPC64
 124        unsigned long buid;
 125        struct pci_dn *pci_data;
 126#endif  /* CONFIG_PPC64 */
 127
 128        void *private_data;
 129
 130        /* IRQ domain hierarchy */
 131        struct irq_domain       *dev_domain;
 132        struct irq_domain       *msi_domain;
 133        struct fwnode_handle    *fwnode;
 134};
 135
 136/* These are used for config access before all the PCI probing
 137   has been done. */
 138extern int early_read_config_byte(struct pci_controller *hose, int bus,
 139                        int dev_fn, int where, u8 *val);
 140extern int early_read_config_word(struct pci_controller *hose, int bus,
 141                        int dev_fn, int where, u16 *val);
 142extern int early_read_config_dword(struct pci_controller *hose, int bus,
 143                        int dev_fn, int where, u32 *val);
 144extern int early_write_config_byte(struct pci_controller *hose, int bus,
 145                        int dev_fn, int where, u8 val);
 146extern int early_write_config_word(struct pci_controller *hose, int bus,
 147                        int dev_fn, int where, u16 val);
 148extern int early_write_config_dword(struct pci_controller *hose, int bus,
 149                        int dev_fn, int where, u32 val);
 150
 151extern int early_find_capability(struct pci_controller *hose, int bus,
 152                                 int dev_fn, int cap);
 153
 154extern void setup_indirect_pci(struct pci_controller* hose,
 155                               resource_size_t cfg_addr,
 156                               resource_size_t cfg_data, u32 flags);
 157
 158extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
 159                                int offset, int len, u32 *val);
 160
 161extern int __indirect_read_config(struct pci_controller *hose,
 162                                  unsigned char bus_number, unsigned int devfn,
 163                                  int offset, int len, u32 *val);
 164
 165extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
 166                                 int offset, int len, u32 val);
 167
 168static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 169{
 170        return bus->sysdata;
 171}
 172
 173#ifndef CONFIG_PPC64
 174
 175extern int pci_device_from_OF_node(struct device_node *node,
 176                                   u8 *bus, u8 *devfn);
 177extern void pci_create_OF_bus_map(void);
 178
 179#else   /* CONFIG_PPC64 */
 180
 181/*
 182 * PCI stuff, for nodes representing PCI devices, pointed to
 183 * by device_node->data.
 184 */
 185struct iommu_table;
 186
 187struct pci_dn {
 188        int     flags;
 189#define PCI_DN_FLAG_IOV_VF      0x01
 190#define PCI_DN_FLAG_DEAD        0x02    /* Device has been hot-removed */
 191
 192        int     busno;                  /* pci bus number */
 193        int     devfn;                  /* pci device and function number */
 194        int     vendor_id;              /* Vendor ID */
 195        int     device_id;              /* Device ID */
 196        int     class_code;             /* Device class code */
 197
 198        struct  pci_dn *parent;
 199        struct  pci_controller *phb;    /* for pci devices */
 200        struct  iommu_table_group *table_group; /* for phb's or bridges */
 201
 202        int     pci_ext_config_space;   /* for pci devices */
 203#ifdef CONFIG_EEH
 204        struct eeh_dev *edev;           /* eeh device */
 205#endif
 206#define IODA_INVALID_PE         0xFFFFFFFF
 207        unsigned int pe_number;
 208#ifdef CONFIG_PCI_IOV
 209        u16     vfs_expanded;           /* number of VFs IOV BAR expanded */
 210        u16     num_vfs;                /* number of VFs enabled*/
 211        unsigned int *pe_num_map;       /* PE# for the first VF PE or array */
 212        bool    m64_single_mode;        /* Use M64 BAR in Single Mode */
 213#define IODA_INVALID_M64        (-1)
 214        int     (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */
 215        int     last_allow_rc;                  /* Only used on pseries */
 216#endif /* CONFIG_PCI_IOV */
 217        int     mps;                    /* Maximum Payload Size */
 218        struct list_head child_list;
 219        struct list_head list;
 220        struct resource holes[PCI_SRIOV_NUM_BARS];
 221};
 222
 223/* Get the pointer to a device_node's pci_dn */
 224#define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 225
 226extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
 227                                           int devfn);
 228extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
 229extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
 230                                               struct device_node *dn);
 231extern void pci_remove_device_node_info(struct device_node *dn);
 232
 233#ifdef CONFIG_PCI_IOV
 234struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
 235void remove_sriov_vf_pdns(struct pci_dev *pdev);
 236#endif
 237
 238static inline int pci_device_from_OF_node(struct device_node *np,
 239                                          u8 *bus, u8 *devfn)
 240{
 241        if (!PCI_DN(np))
 242                return -ENODEV;
 243        *bus = PCI_DN(np)->busno;
 244        *devfn = PCI_DN(np)->devfn;
 245        return 0;
 246}
 247
 248#if defined(CONFIG_EEH)
 249static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
 250{
 251        return pdn ? pdn->edev : NULL;
 252}
 253#else
 254#define pdn_to_eeh_dev(x)       (NULL)
 255#endif
 256
 257/** Find the bus corresponding to the indicated device node */
 258extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
 259
 260/** Remove all of the PCI devices under this bus */
 261extern void pci_hp_remove_devices(struct pci_bus *bus);
 262
 263/** Discover new pci devices under this bus, and add them */
 264extern void pci_hp_add_devices(struct pci_bus *bus);
 265
 266extern int pcibios_unmap_io_space(struct pci_bus *bus);
 267extern int pcibios_map_io_space(struct pci_bus *bus);
 268
 269#ifdef CONFIG_NUMA
 270#define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 271#else
 272#define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = NUMA_NO_NODE)
 273#endif
 274
 275#endif  /* CONFIG_PPC64 */
 276
 277/* Get the PCI host controller for an OF device */
 278extern struct pci_controller *pci_find_hose_for_OF_device(
 279                        struct device_node* node);
 280
 281extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
 282
 283/* Fill up host controller resources from the OF node */
 284extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 285                        struct device_node *dev, int primary);
 286
 287/* Allocate & free a PCI host bridge structure */
 288extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 289extern void pcibios_free_controller(struct pci_controller *phb);
 290extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
 291
 292#ifdef CONFIG_PCI
 293extern int pcibios_vaddr_is_ioport(void __iomem *address);
 294#else
 295static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 296{
 297        return 0;
 298}
 299#endif  /* CONFIG_PCI */
 300
 301#endif  /* __KERNEL__ */
 302#endif  /* _ASM_POWERPC_PCI_BRIDGE_H */
 303
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