LXR linux/arch/powerpc/include/asm/reg

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Contains register definitions common to PowerPC 8xx CPUs.  Notice
   4 */
   5#ifndef _ASM_POWERPC_REG_8xx_H
   6#define _ASM_POWERPC_REG_8xx_H
   7
   8/* Cache control on the MPC8xx is provided through some additional
   9 * special purpose registers.
  10 */
  11#define SPRN_IC_CST     560     /* Instruction cache control/status */
  12#define SPRN_IC_ADR     561     /* Address needed for some commands */
  13#define SPRN_IC_DAT     562     /* Read-only data register */
  14#define SPRN_DC_CST     568     /* Data cache control/status */
  15#define SPRN_DC_ADR     569     /* Address needed for some commands */
  16#define SPRN_DC_DAT     570     /* Read-only data register */
  17
  18/* Misc Debug */
  19#define SPRN_DPDR       630
  20#define SPRN_MI_CAM     816
  21#define SPRN_MI_RAM0    817
  22#define SPRN_MI_RAM1    818
  23#define SPRN_MD_CAM     824
  24#define SPRN_MD_RAM0    825
  25#define SPRN_MD_RAM1    826
  26
  27/* Special MSR manipulation registers */
  28#define SPRN_EIE        80      /* External interrupt enable (EE=1, RI=1) */
  29#define SPRN_EID        81      /* External interrupt disable (EE=0, RI=1) */
  30#define SPRN_NRI        82      /* Non recoverable interrupt (EE=0, RI=0) */
  31
  32/* Debug registers */
  33#define SPRN_CMPA       144
  34#define SPRN_COUNTA     150
  35#define SPRN_CMPE       152
  36#define SPRN_CMPF       153
  37#define SPRN_LCTRL1     156
  38#define   LCTRL1_CTE_GT         0xc0000000
  39#define   LCTRL1_CTF_LT         0x14000000
  40#define   LCTRL1_CRWE_RW        0x00000000
  41#define   LCTRL1_CRWE_RO        0x00040000
  42#define   LCTRL1_CRWE_WO        0x000c0000
  43#define   LCTRL1_CRWF_RW        0x00000000
  44#define   LCTRL1_CRWF_RO        0x00010000
  45#define   LCTRL1_CRWF_WO        0x00030000
  46#define SPRN_LCTRL2     157
  47#define   LCTRL2_LW0EN          0x80000000
  48#define   LCTRL2_LW0LA_E        0x00000000
  49#define   LCTRL2_LW0LA_F        0x04000000
  50#define   LCTRL2_LW0LA_EandF    0x08000000
  51#define   LCTRL2_LW0LADC        0x02000000
  52#define   LCTRL2_SLW0EN         0x00000002
  53#ifdef CONFIG_PPC_8xx
  54#define SPRN_ICTRL      158
  55#endif
  56#define SPRN_BAR        159
  57
  58/* Commands.  Only the first few are available to the instruction cache.
  59*/
  60#define IDC_ENABLE      0x02000000      /* Cache enable */
  61#define IDC_DISABLE     0x04000000      /* Cache disable */
  62#define IDC_LDLCK       0x06000000      /* Load and lock */
  63#define IDC_UNLINE      0x08000000      /* Unlock line */
  64#define IDC_UNALL       0x0a000000      /* Unlock all */
  65#define IDC_INVALL      0x0c000000      /* Invalidate all */
  66
  67#define DC_FLINE        0x0e000000      /* Flush data cache line */
  68#define DC_SFWT         0x01000000      /* Set forced writethrough mode */
  69#define DC_CFWT         0x03000000      /* Clear forced writethrough mode */
  70#define DC_SLES         0x05000000      /* Set little endian swap mode */
  71#define DC_CLES         0x07000000      /* Clear little endian swap mode */
  72
  73/* Status.
  74*/
  75#define IDC_ENABLED     0x80000000      /* Cache is enabled */
  76#define IDC_CERR1       0x00200000      /* Cache error 1 */
  77#define IDC_CERR2       0x00100000      /* Cache error 2 */
  78#define IDC_CERR3       0x00080000      /* Cache error 3 */
  79
  80#define DC_DFWT         0x40000000      /* Data cache is forced write through */
  81#define DC_LES          0x20000000      /* Caches are little endian mode */
  82
  83#endif /* _ASM_POWERPC_REG_8xx_H */
  84