LXR linux/arch/powerpc/include/asm/tsi108.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * common routine and memory layout for Tundra TSI108(Grendel) host bridge
   4 * memory controller.
   5 *
   6 * Author: Jacob Pan (jacob.pan@freescale.com)
   7 *         Alex Bounine (alexandreb@tundra.com)
   8 *
   9 * Copyright 2004-2006 Freescale Semiconductor, Inc.
  10 */
  11
  12#ifndef __PPC_KERNEL_TSI108_H
  13#define __PPC_KERNEL_TSI108_H
  14
  15#include <asm/pci-bridge.h>
  16
  17/* Size of entire register space */
  18#define TSI108_REG_SIZE         (0x10000)
  19
  20/* Sizes of register spaces for individual blocks */
  21#define TSI108_HLP_SIZE         0x1000
  22#define TSI108_PCI_SIZE         0x1000
  23#define TSI108_CLK_SIZE         0x1000
  24#define TSI108_PB_SIZE          0x1000
  25#define TSI108_SD_SIZE          0x1000
  26#define TSI108_DMA_SIZE         0x1000
  27#define TSI108_ETH_SIZE         0x1000
  28#define TSI108_I2C_SIZE         0x400
  29#define TSI108_MPIC_SIZE        0x400
  30#define TSI108_UART0_SIZE       0x200
  31#define TSI108_GPIO_SIZE        0x200
  32#define TSI108_UART1_SIZE       0x200
  33
  34/* Offsets within Tsi108(A) CSR space for individual blocks */
  35#define TSI108_HLP_OFFSET       0x0000
  36#define TSI108_PCI_OFFSET       0x1000
  37#define TSI108_CLK_OFFSET       0x2000
  38#define TSI108_PB_OFFSET        0x3000
  39#define TSI108_SD_OFFSET        0x4000
  40#define TSI108_DMA_OFFSET       0x5000
  41#define TSI108_ETH_OFFSET       0x6000
  42#define TSI108_I2C_OFFSET       0x7000
  43#define TSI108_MPIC_OFFSET      0x7400
  44#define TSI108_UART0_OFFSET     0x7800
  45#define TSI108_GPIO_OFFSET      0x7A00
  46#define TSI108_UART1_OFFSET     0x7C00
  47
  48/* Tsi108 registers used by common code components */
  49#define TSI108_PCI_CSR          (0x004)
  50#define TSI108_PCI_IRP_CFG_CTL  (0x180)
  51#define TSI108_PCI_IRP_STAT     (0x184)
  52#define TSI108_PCI_IRP_ENABLE   (0x188)
  53#define TSI108_PCI_IRP_INTAD    (0x18C)
  54
  55#define TSI108_PCI_IRP_STAT_P_INT       (0x00400000)
  56#define TSI108_PCI_IRP_ENABLE_P_INT     (0x00400000)
  57
  58#define TSI108_CG_PWRUP_STATUS  (0x234)
  59
  60#define TSI108_PB_ISR           (0x00C)
  61#define TSI108_PB_ERRCS         (0x404)
  62#define TSI108_PB_AERR          (0x408)
  63
  64#define TSI108_PB_ERRCS_ES              (1 << 1)
  65#define TSI108_PB_ISR_PBS_RD_ERR        (1 << 8)
  66
  67#define TSI108_PCI_CFG_SIZE             (0x01000000)
  68
  69/*
  70 * PHY Configuration Options
  71 *
  72 * Specify "bcm54xx" in the compatible property of your device tree phy
  73 * nodes if your board uses the Broadcom PHYs
  74 */
  75#define TSI108_PHY_MV88E        0       /* Marvel 88Exxxx PHY */
  76#define TSI108_PHY_BCM54XX      1       /* Broadcom BCM54xx PHY */
  77
  78/* Global variables */
  79
  80extern u32 tsi108_pci_cfg_base;
  81/* Exported functions */
  82
  83extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
  84                                      int offset, int len, u32 val);
  85extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
  86                                     int offset, int len, u32 * val);
  87extern void tsi108_clear_pci_error(u32 pci_cfg_base);
  88
  89extern phys_addr_t get_csrbase(void);
  90
  91typedef struct {
  92        u32 regs;               /* hw registers base address */
  93        u32 phyregs;            /* phy registers base address */
  94        u16 phy;                /* phy address */
  95        u16 irq_num;            /* irq number */
  96        u8 mac_addr[6];         /* phy mac address */
  97        u16 phy_type;   /* type of phy on board */
  98} hw_info;
  99
 100extern u32 get_vir_csrbase(void);
 101extern u32 tsi108_csr_vir_base;
 102
 103static inline u32 tsi108_read_reg(u32 reg_offset)
 104{
 105        return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
 106}
 107
 108static inline void tsi108_write_reg(u32 reg_offset, u32 val)
 109{
 110        out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
 111}
 112
 113#endif                          /* __PPC_KERNEL_TSI108_H */
 114