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8
9#include "isa207-common.h"
10
11PMU_FORMAT_ATTR(event, "config:0-49");
12PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
13PMU_FORMAT_ATTR(mark, "config:8");
14PMU_FORMAT_ATTR(combine, "config:11");
15PMU_FORMAT_ATTR(unit, "config:12-15");
16PMU_FORMAT_ATTR(pmc, "config:16-19");
17PMU_FORMAT_ATTR(cache_sel, "config:20-23");
18PMU_FORMAT_ATTR(sample_mode, "config:24-28");
19PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
20PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
21PMU_FORMAT_ATTR(thresh_start, "config:36-39");
22PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
23
24static struct attribute *isa207_pmu_format_attr[] = {
25 &format_attr_event.attr,
26 &format_attr_pmcxsel.attr,
27 &format_attr_mark.attr,
28 &format_attr_combine.attr,
29 &format_attr_unit.attr,
30 &format_attr_pmc.attr,
31 &format_attr_cache_sel.attr,
32 &format_attr_sample_mode.attr,
33 &format_attr_thresh_sel.attr,
34 &format_attr_thresh_stop.attr,
35 &format_attr_thresh_start.attr,
36 &format_attr_thresh_cmp.attr,
37 NULL,
38};
39
40struct attribute_group isa207_pmu_format_group = {
41 .name = "format",
42 .attrs = isa207_pmu_format_attr,
43};
44
45static inline bool event_is_fab_match(u64 event)
46{
47
48 event &= 0xff0fe;
49
50
51 return (event == 0x30056 || event == 0x4f052);
52}
53
54static bool is_event_valid(u64 event)
55{
56 u64 valid_mask = EVENT_VALID_MASK;
57
58 if (cpu_has_feature(CPU_FTR_ARCH_31))
59 valid_mask = p10_EVENT_VALID_MASK;
60 else if (cpu_has_feature(CPU_FTR_ARCH_300))
61 valid_mask = p9_EVENT_VALID_MASK;
62
63 return !(event & ~valid_mask);
64}
65
66static inline bool is_event_marked(u64 event)
67{
68 if (event & EVENT_IS_MARKED)
69 return true;
70
71 return false;
72}
73
74static unsigned long sdar_mod_val(u64 event)
75{
76 if (cpu_has_feature(CPU_FTR_ARCH_31))
77 return p10_SDAR_MODE(event);
78
79 return p9_SDAR_MODE(event);
80}
81
82static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
83{
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
102 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
103 else if (sdar_mod_val(event))
104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT;
105 else
106 *mmcra |= MMCRA_SDAR_MODE_DCACHE;
107 } else
108 *mmcra |= MMCRA_SDAR_MODE_TLB;
109}
110
111static u64 p10_thresh_cmp_val(u64 value)
112{
113 int exp = 0;
114 u64 result = value;
115
116 if (!value)
117 return value;
118
119
120
121
122
123
124
125
126
127
128 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
129 if (value > 261120)
130 value = 261120;
131 while ((64 - __builtin_clzl(value)) > 8) {
132 exp++;
133 value >>= 2;
134 }
135
136
137
138
139
140
141 if (!(value & 0xC0) && exp)
142 result = 0;
143 else
144 result = (exp << 8) | value;
145 }
146 return result;
147}
148
149static u64 thresh_cmp_val(u64 value)
150{
151 if (cpu_has_feature(CPU_FTR_ARCH_31))
152 value = p10_thresh_cmp_val(value);
153
154
155
156
157
158 if (cpu_has_feature(CPU_FTR_ARCH_300))
159 return value << p9_MMCRA_THR_CMP_SHIFT;
160 else
161 return value << MMCRA_THR_CMP_SHIFT;
162}
163
164static unsigned long combine_from_event(u64 event)
165{
166 if (cpu_has_feature(CPU_FTR_ARCH_300))
167 return p9_EVENT_COMBINE(event);
168
169 return EVENT_COMBINE(event);
170}
171
172static unsigned long combine_shift(unsigned long pmc)
173{
174 if (cpu_has_feature(CPU_FTR_ARCH_300))
175 return p9_MMCR1_COMBINE_SHIFT(pmc);
176
177 return MMCR1_COMBINE_SHIFT(pmc);
178}
179
180static inline bool event_is_threshold(u64 event)
181{
182 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
183}
184
185static bool is_thresh_cmp_valid(u64 event)
186{
187 unsigned int cmp, exp;
188
189 if (cpu_has_feature(CPU_FTR_ARCH_31))
190 return p10_thresh_cmp_val(event) != 0;
191
192
193
194
195
196
197 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
198 exp = cmp >> 7;
199
200 if (exp && (cmp & 0x60) == 0)
201 return false;
202
203 return true;
204}
205
206static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
207{
208 unsigned int cache;
209
210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
211 return cache;
212}
213
214static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
215{
216 u64 ret = PERF_MEM_NA;
217
218 switch(idx) {
219 case 0:
220
221 break;
222 case 1:
223 ret = PH(LVL, L1);
224 break;
225 case 2:
226 ret = PH(LVL, L2);
227 break;
228 case 3:
229 ret = PH(LVL, L3);
230 break;
231 case 4:
232 if (sub_idx <= 1)
233 ret = PH(LVL, LOC_RAM);
234 else if (sub_idx > 1 && sub_idx <= 2)
235 ret = PH(LVL, REM_RAM1);
236 else
237 ret = PH(LVL, REM_RAM2);
238 ret |= P(SNOOP, HIT);
239 break;
240 case 5:
241 ret = PH(LVL, REM_CCE1);
242 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
243 ret |= P(SNOOP, HIT);
244 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
245 ret |= P(SNOOP, HITM);
246 break;
247 case 6:
248 ret = PH(LVL, REM_CCE2);
249 if ((sub_idx == 0) || (sub_idx == 2))
250 ret |= P(SNOOP, HIT);
251 else if ((sub_idx == 1) || (sub_idx == 3))
252 ret |= P(SNOOP, HITM);
253 break;
254 case 7:
255 ret = PM(LVL, L1);
256 break;
257 }
258
259 return ret;
260}
261
262void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
263 struct pt_regs *regs)
264{
265 u64 idx;
266 u32 sub_idx;
267 u64 sier;
268 u64 val;
269
270
271 if (!(flags & PPMU_HAS_SIER)) {
272 dsrc->val = 0;
273 return;
274 }
275
276 sier = mfspr(SPRN_SIER);
277 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
278 if (val != 1 && val != 2 && !(val == 7 && cpu_has_feature(CPU_FTR_ARCH_31)))
279 return;
280
281 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
282 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
283
284 dsrc->val = isa207_find_source(idx, sub_idx);
285 if (val == 7) {
286 u64 mmcra;
287 u32 op_type;
288
289
290
291
292
293
294
295
296 mmcra = mfspr(SPRN_MMCRA);
297
298 op_type = (mmcra >> MMCRA_SAMP_ELIG_SHIFT) & MMCRA_SAMP_ELIG_MASK;
299 switch (op_type) {
300 case 5:
301 dsrc->val |= P(OP, LOAD);
302 break;
303 case 7:
304 dsrc->val |= P(OP, STORE);
305 break;
306 default:
307 dsrc->val |= P(OP, NA);
308 break;
309 }
310 } else {
311 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
312 }
313}
314
315void isa207_get_mem_weight(u64 *weight, u64 type)
316{
317 union perf_sample_weight *weight_fields;
318 u64 weight_lat;
319 u64 mmcra = mfspr(SPRN_MMCRA);
320 u64 exp = MMCRA_THR_CTR_EXP(mmcra);
321 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
322 u64 sier = mfspr(SPRN_SIER);
323 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
324
325 if (cpu_has_feature(CPU_FTR_ARCH_31))
326 mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
327
328 if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31)))
329 weight_lat = 0;
330 else
331 weight_lat = mantissa << (2 * exp);
332
333
334
335
336
337
338
339
340
341
342
343 weight_fields = (union perf_sample_weight *)weight;
344 if (type & PERF_SAMPLE_WEIGHT)
345 weight_fields->full = weight_lat;
346 else {
347 weight_fields->var1_dw = (u32)weight_lat;
348 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
349 weight_fields->var2_w = P10_SIER2_FINISH_CYC(mfspr(SPRN_SIER2));
350 weight_fields->var3_w = P10_SIER2_DISPATCH_CYC(mfspr(SPRN_SIER2));
351 }
352 }
353}
354
355int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1)
356{
357 unsigned int unit, pmc, cache, ebb;
358 unsigned long mask, value;
359
360 mask = value = 0;
361
362 if (!is_event_valid(event))
363 return -1;
364
365 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
366 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
367 if (cpu_has_feature(CPU_FTR_ARCH_31))
368 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
369 p10_EVENT_CACHE_SEL_MASK;
370 else
371 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
372 EVENT_CACHE_SEL_MASK;
373 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
374
375 if (pmc) {
376 u64 base_event;
377
378 if (pmc > 6)
379 return -1;
380
381
382 base_event = event & ~EVENT_LINUX_MASK;
383
384 if (pmc >= 5 && base_event != 0x500fa &&
385 base_event != 0x600f4)
386 return -1;
387
388 mask |= CNST_PMC_MASK(pmc);
389 value |= CNST_PMC_VAL(pmc);
390
391
392
393
394
395
396
397 if (pmc >= 5)
398 goto ebb_bhrb;
399 }
400
401 if (pmc <= 4) {
402
403
404
405
406
407
408 mask |= CNST_NC_MASK;
409 value |= CNST_NC_VAL;
410 }
411
412 if (unit >= 6 && unit <= 9) {
413 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
414 if (unit == 6) {
415 mask |= CNST_L2L3_GROUP_MASK;
416 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
417 }
418 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
419 mask |= CNST_CACHE_GROUP_MASK;
420 value |= CNST_CACHE_GROUP_VAL(event & 0xff);
421
422 mask |= CNST_CACHE_PMC4_MASK;
423 if (pmc == 4)
424 value |= CNST_CACHE_PMC4_VAL;
425 } else if (cache & 0x7) {
426
427
428
429
430
431
432
433
434
435 return -1;
436 }
437
438 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
439 mask |= CNST_L1_QUAL_MASK;
440 value |= CNST_L1_QUAL_VAL(cache);
441 }
442
443 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
444 mask |= CNST_RADIX_SCOPE_GROUP_MASK;
445 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
446 }
447
448 if (is_event_marked(event)) {
449 mask |= CNST_SAMPLE_MASK;
450 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
451 }
452
453 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
454 if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) {
455 mask |= CNST_THRESH_CTL_SEL_MASK;
456 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
457 mask |= p10_CNST_THRESH_CMP_MASK;
458 value |= p10_CNST_THRESH_CMP_VAL(p10_thresh_cmp_val(event_config1));
459 }
460 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
461 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
462 mask |= CNST_THRESH_MASK;
463 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
464 }
465 } else {
466
467
468
469
470 if (event_is_fab_match(event)) {
471 mask |= CNST_FAB_MATCH_MASK;
472 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
473 } else {
474 if (!is_thresh_cmp_valid(event))
475 return -1;
476
477 mask |= CNST_THRESH_MASK;
478 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
479 }
480 }
481
482ebb_bhrb:
483 if (!pmc && ebb)
484
485 return -1;
486
487 if (event & EVENT_WANTS_BHRB) {
488 if (!ebb)
489
490 return -1;
491
492 mask |= CNST_IFM_MASK;
493 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
494 }
495
496
497
498
499
500
501 mask |= CNST_EBB_MASK;
502 value |= CNST_EBB_VAL(ebb);
503
504 *maskp = mask;
505 *valp = value;
506
507 return 0;
508}
509
510int isa207_compute_mmcr(u64 event[], int n_ev,
511 unsigned int hwc[], struct mmcr_regs *mmcr,
512 struct perf_event *pevents[], u32 flags)
513{
514 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
515 unsigned long mmcr3;
516 unsigned int pmc, pmc_inuse;
517 int i;
518
519 pmc_inuse = 0;
520
521
522 for (i = 0; i < n_ev; ++i) {
523 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
524 if (pmc)
525 pmc_inuse |= 1 << pmc;
526 }
527
528 mmcra = mmcr1 = mmcr2 = mmcr3 = 0;
529
530
531
532
533
534 if (cpu_has_feature(CPU_FTR_ARCH_31))
535 mmcra |= MMCRA_BHRB_DISABLE;
536
537
538 for (i = 0; i < n_ev; ++i) {
539 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
540 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
541 combine = combine_from_event(event[i]);
542 psel = event[i] & EVENT_PSEL_MASK;
543
544 if (!pmc) {
545 for (pmc = 1; pmc <= 4; ++pmc) {
546 if (!(pmc_inuse & (1 << pmc)))
547 break;
548 }
549
550 pmc_inuse |= 1 << pmc;
551 }
552
553 if (pmc <= 4) {
554 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
555 mmcr1 |= combine << combine_shift(pmc);
556 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
557 }
558
559
560 mmcra_sdar_mode(event[i], &mmcra);
561
562 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
563 cache = dc_ic_rld_quad_l1_sel(event[i]);
564 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
565 } else {
566 if (event[i] & EVENT_IS_L1) {
567 cache = dc_ic_rld_quad_l1_sel(event[i]);
568 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
569 }
570 }
571
572
573 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
574 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
575 p10_EVENT_RADIX_SCOPE_QUAL_MASK;
576 mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
577 }
578
579 if (is_event_marked(event[i])) {
580 mmcra |= MMCRA_SAMPLE_ENABLE;
581
582 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
583 if (val) {
584 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
585 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
586 }
587 }
588
589
590
591
592
593 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
594 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
595 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
596 } else {
597 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
598 mmcra |= val << MMCRA_THR_CTL_SHIFT;
599 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
600 mmcra |= val << MMCRA_THR_SEL_SHIFT;
601 if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
602 val = (event[i] >> EVENT_THR_CMP_SHIFT) &
603 EVENT_THR_CMP_MASK;
604 mmcra |= thresh_cmp_val(val);
605 } else if (flags & PPMU_HAS_ATTR_CONFIG1) {
606 val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) &
607 p10_EVENT_THR_CMP_MASK;
608 mmcra |= thresh_cmp_val(val);
609 }
610 }
611
612 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
613 val = (event[i] >> p10_L2L3_EVENT_SHIFT) &
614 p10_EVENT_L2L3_SEL_MASK;
615 mmcr2 |= val << p10_L2L3_SEL_SHIFT;
616 }
617
618 if (event[i] & EVENT_WANTS_BHRB) {
619 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
620 mmcra |= val << MMCRA_IFM_SHIFT;
621 }
622
623
624 if (cpu_has_feature(CPU_FTR_ARCH_31) &&
625 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB)))
626 mmcra &= ~MMCRA_BHRB_DISABLE;
627
628 if (pevents[i]->attr.exclude_user)
629 mmcr2 |= MMCR2_FCP(pmc);
630
631 if (pevents[i]->attr.exclude_hv)
632 mmcr2 |= MMCR2_FCH(pmc);
633
634 if (pevents[i]->attr.exclude_kernel) {
635 if (cpu_has_feature(CPU_FTR_HVMODE))
636 mmcr2 |= MMCR2_FCH(pmc);
637 else
638 mmcr2 |= MMCR2_FCS(pmc);
639 }
640
641 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
642 if (pmc <= 4) {
643 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) &
644 p10_EVENT_MMCR3_MASK;
645 mmcr3 |= val << MMCR3_SHIFT(pmc);
646 }
647 }
648
649 hwc[i] = pmc - 1;
650 }
651
652
653 mmcr->mmcr0 = 0;
654
655
656 if (pmc_inuse & 2)
657 mmcr->mmcr0 = MMCR0_PMC1CE;
658
659 if (pmc_inuse & 0x7c)
660 mmcr->mmcr0 |= MMCR0_PMCjCE;
661
662
663 if (!(pmc_inuse & 0x60))
664 mmcr->mmcr0 |= MMCR0_FC56;
665
666
667
668
669
670
671 if (cpu_has_feature(CPU_FTR_ARCH_31))
672 mmcr->mmcr0 |= MMCR0_PMCCEXT;
673
674 mmcr->mmcr1 = mmcr1;
675 mmcr->mmcra = mmcra;
676 mmcr->mmcr2 = mmcr2;
677 mmcr->mmcr3 = mmcr3;
678
679 return 0;
680}
681
682void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
683{
684 if (pmc <= 3)
685 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
686}
687
688static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
689{
690 int i, j;
691
692 for (i = 0; i < size; ++i) {
693 if (event < ev_alt[i][0])
694 break;
695
696 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j)
697 if (event == ev_alt[i][j])
698 return i;
699 }
700
701 return -1;
702}
703
704int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
705 const unsigned int ev_alt[][MAX_ALT])
706{
707 int i, j, num_alt = 0;
708 u64 alt_event;
709
710 alt[num_alt++] = event;
711 i = find_alternative(event, ev_alt, size);
712 if (i >= 0) {
713
714 for (j = 0; j < MAX_ALT; ++j) {
715 alt_event = ev_alt[i][j];
716 if (alt_event && alt_event != event)
717 alt[num_alt++] = alt_event;
718 }
719 }
720
721 if (flags & PPMU_ONLY_COUNT_RUN) {
722
723
724
725
726 j = num_alt;
727 for (i = 0; i < num_alt; ++i) {
728 switch (alt[i]) {
729 case 0x1e:
730 alt[j++] = 0x600f4;
731 break;
732 case 0x600f4:
733 alt[j++] = 0x1e;
734 break;
735 case 0x2:
736 alt[j++] = 0x500fa;
737 break;
738 case 0x500fa:
739 alt[j++] = 0x2;
740 break;
741 }
742 }
743 num_alt = j;
744 }
745
746 return num_alt;
747}
748
749int isa3XX_check_attr_config(struct perf_event *ev)
750{
751 u64 val, sample_mode;
752 u64 event = ev->attr.config;
753
754 val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
755 sample_mode = val & 0x3;
756
757
758
759
760
761 if (sample_mode == 0x3)
762 return -EINVAL;
763
764
765
766
767
768 switch (val) {
769 case 0x5:
770 case 0x9:
771 case 0xD:
772 case 0x19:
773 case 0x1D:
774 case 0x1A:
775 case 0x1E:
776 return -EINVAL;
777 }
778
779
780
781
782
783
784 val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
785 if (((val & 0xF0) == 0xF0) || ((val & 0xF) == 0xF))
786 return -EINVAL;
787
788 return 0;
789}
790