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7#include <linux/kernel.h>
8#include <linux/perf_event.h>
9#include <linux/string.h>
10#include <asm/reg.h>
11#include <asm/cputable.h>
12
13#include "internal.h"
14
15
16
17
18#define PM_PMC_SH 20
19#define PM_PMC_MSK 0x7
20#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21#define PM_UNIT_SH 16
22#define PM_UNIT_MSK 0xf
23#define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH)
24#define PM_LLAV 0x8000
25#define PM_LLA 0x4000
26#define PM_BYTE_SH 12
27#define PM_BYTE_MSK 3
28#define PM_SUBUNIT_SH 8
29#define PM_SUBUNIT_MSK 7
30#define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
31#define PM_PMCSEL_MSK 0xff
32#define PM_BUSEVENT_MSK 0xf3700
33
34
35
36
37#define MMCR1_TTM0SEL_SH 60
38#define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
39#define MMCR1_TTMSEL_MSK 0xf
40#define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
41#define MMCR1_NESTSEL_SH 45
42#define MMCR1_NESTSEL_MSK 0x7
43#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
44#define MMCR1_PMC1_LLA (1ul << 44)
45#define MMCR1_PMC1_LLA_VALUE (1ul << 39)
46#define MMCR1_PMC1_ADDR_SEL (1ul << 35)
47#define MMCR1_PMC1SEL_SH 24
48#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
49#define MMCR1_PMCSEL_MSK 0xff
50
51
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53
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60
61
62
63static unsigned char direct_event_is_marked[0x60 >> 1] = {
64 0,
65 0,
66 0,
67 0x07,
68 0x04,
69 0x06,
70 0,
71 0,
72 0x02,
73 0x08,
74 0,
75 0,
76 0x0c,
77 0x0f,
78 0x01,
79 0,
80 0,
81 0,
82 0,
83 0,
84 0x15,
85 0,
86 0,
87 0,
88 0x4f,
89 0x7f,
90 0x4f,
91 0x5f,
92 0x6f,
93 0x4f,
94 0,
95 0x08,
96 0x1f,
97 0x1f,
98 0x1f,
99 0x1f,
100 0x1f,
101 0x1f,
102 0x1f,
103 0x1f,
104 0,
105 0x05,
106 0x1c,
107 0x02,
108 0,
109 0,
110 0,
111 0,
112};
113
114
115
116
117
118static u32 marked_bus_events[16] = {
119 0x01000000,
120 0x00010000,
121 0, 0, 0, 0,
122 0x00000088,
123 0x000000c0,
124 0x04010000,
125 0xff010000u,
126 0,
127 0x00000010,
128 0,
129 0x00000022,
130 0, 0
131};
132
133
134
135
136
137static int power6_marked_instr_event(u64 event)
138{
139 int pmc, psel, ptype;
140 int bit, byte, unit;
141 u32 mask;
142
143 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
144 psel = (event & PM_PMCSEL_MSK) >> 1;
145 if (pmc >= 5)
146 return 0;
147
148 bit = -1;
149 if (psel < sizeof(direct_event_is_marked)) {
150 ptype = direct_event_is_marked[psel];
151 if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
152 return 0;
153 ptype >>= 4;
154 if (ptype == 0)
155 return 1;
156 if (ptype == 1)
157 bit = 0;
158 else
159 bit = ptype ^ (pmc - 1);
160 } else if ((psel & 0x48) == 0x40)
161 bit = psel & 7;
162
163 if (!(event & PM_BUSEVENT_MSK) || bit == -1)
164 return 0;
165
166 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
167 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
168 mask = marked_bus_events[unit];
169 return (mask >> (byte * 8 + bit)) & 1;
170}
171
172
173
174
175static int p6_compute_mmcr(u64 event[], int n_ev,
176 unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[],
177 u32 flags __maybe_unused)
178{
179 unsigned long mmcr1 = 0;
180 unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
181 int i;
182 unsigned int pmc, ev, b, u, s, psel;
183 unsigned int ttmset = 0;
184 unsigned int pmc_inuse = 0;
185
186 if (n_ev > 6)
187 return -1;
188 for (i = 0; i < n_ev; ++i) {
189 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
190 if (pmc) {
191 if (pmc_inuse & (1 << (pmc - 1)))
192 return -1;
193 pmc_inuse |= 1 << (pmc - 1);
194 }
195 }
196 for (i = 0; i < n_ev; ++i) {
197 ev = event[i];
198 pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
199 if (pmc) {
200 --pmc;
201 } else {
202
203 for (pmc = 0; pmc < 4; ++pmc)
204 if (!(pmc_inuse & (1 << pmc)))
205 break;
206 if (pmc >= 4)
207 return -1;
208 pmc_inuse |= 1 << pmc;
209 }
210 hwc[i] = pmc;
211 psel = ev & PM_PMCSEL_MSK;
212 if (ev & PM_BUSEVENT_MSK) {
213
214 b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
215 u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
216
217 if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
218 return -1;
219 mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
220 ttmset |= 1 << b;
221 if (u == 5) {
222
223 s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
224 if ((ttmset & 0x10) &&
225 MMCR1_NESTSEL(mmcr1) != s)
226 return -1;
227 ttmset |= 0x10;
228 mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
229 }
230 if (0x30 <= psel && psel <= 0x3d) {
231
232 if (b >= 2)
233 mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
234 }
235
236 if (pmc >= 2 && (psel & 0x90) == 0x80)
237 psel ^= 0x20;
238 }
239 if (ev & PM_LLA) {
240 mmcr1 |= MMCR1_PMC1_LLA >> pmc;
241 if (ev & PM_LLAV)
242 mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
243 }
244 if (power6_marked_instr_event(event[i]))
245 mmcra |= MMCRA_SAMPLE_ENABLE;
246 if (pmc < 4)
247 mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
248 }
249 mmcr->mmcr0 = 0;
250 if (pmc_inuse & 1)
251 mmcr->mmcr0 = MMCR0_PMC1CE;
252 if (pmc_inuse & 0xe)
253 mmcr->mmcr0 |= MMCR0_PMCjCE;
254 mmcr->mmcr1 = mmcr1;
255 mmcr->mmcra = mmcra;
256 return 0;
257}
258
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263
264
265
266
267
268
269static int p6_get_constraint(u64 event, unsigned long *maskp,
270 unsigned long *valp, u64 event_config1 __maybe_unused)
271{
272 int pmc, byte, sh, subunit;
273 unsigned long mask = 0, value = 0;
274
275 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
276 if (pmc) {
277 if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
278 return -1;
279 sh = (pmc - 1) * 2;
280 mask |= 2 << sh;
281 value |= 1 << sh;
282 }
283 if (event & PM_BUSEVENT_MSK) {
284 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
285 sh = byte * 4 + (16 - PM_UNIT_SH);
286 mask |= PM_UNIT_MSKS << sh;
287 value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
288 if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
289 subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
290 mask |= (unsigned long)PM_SUBUNIT_MSK << 32;
291 value |= (unsigned long)subunit << 32;
292 }
293 }
294 if (pmc <= 4) {
295 mask |= 0x8000;
296 value |= 0x1000;
297 }
298 *maskp = mask;
299 *valp = value;
300 return 0;
301}
302
303static int p6_limited_pmc_event(u64 event)
304{
305 int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
306
307 return pmc == 5 || pmc == 6;
308}
309
310#define MAX_ALT 4
311
312static const unsigned int event_alternatives[][MAX_ALT] = {
313 { 0x0130e8, 0x2000f6, 0x3000fc },
314 { 0x080080, 0x10000d, 0x30000c, 0x4000f0 },
315 { 0x080088, 0x200054, 0x3000f0 },
316 { 0x10000a, 0x2000f4, 0x600005 },
317 { 0x10000b, 0x2000f5 },
318 { 0x10000e, 0x400010 },
319 { 0x100010, 0x4000f8 },
320 { 0x10001a, 0x200010 },
321 { 0x100026, 0x3000f8 },
322 { 0x100054, 0x2000f0 },
323 { 0x100056, 0x2000fc },
324 { 0x1000f0, 0x40000a },
325 { 0x1000f8, 0x200008 },
326 { 0x1000fc, 0x400006 },
327 { 0x20000e, 0x400007 },
328 { 0x200012, 0x300012 },
329 { 0x2000f2, 0x3000f2 },
330 { 0x2000f8, 0x300010 },
331 { 0x2000fe, 0x300056 },
332 { 0x2d0030, 0x30001a },
333 { 0x30000a, 0x400018 },
334 { 0x3000f6, 0x40000e },
335 { 0x3000fe, 0x400056 },
336};
337
338
339
340
341
342static int find_alternatives_list(u64 event)
343{
344 int i, j;
345 unsigned int alt;
346
347 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
348 if (event < event_alternatives[i][0])
349 return -1;
350 for (j = 0; j < MAX_ALT; ++j) {
351 alt = event_alternatives[i][j];
352 if (!alt || event < alt)
353 break;
354 if (event == alt)
355 return i;
356 }
357 }
358 return -1;
359}
360
361static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
362{
363 int i, j, nlim;
364 unsigned int psel, pmc;
365 unsigned int nalt = 1;
366 u64 aevent;
367
368 alt[0] = event;
369 nlim = p6_limited_pmc_event(event);
370
371
372 i = find_alternatives_list(event);
373 if (i >= 0) {
374
375 for (j = 0; j < MAX_ALT; ++j) {
376 aevent = event_alternatives[i][j];
377 if (!aevent)
378 break;
379 if (aevent != event)
380 alt[nalt++] = aevent;
381 nlim += p6_limited_pmc_event(aevent);
382 }
383
384 } else {
385
386
387 psel = event & (PM_PMCSEL_MSK & ~1);
388 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
389 if (pmc && (psel == 0x32 || psel == 0x34))
390 alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
391 ((5 - pmc) << PM_PMC_SH);
392
393
394 if (pmc && (psel == 0x38 || psel == 0x3a))
395 alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
396 ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
397 }
398
399 if (flags & PPMU_ONLY_COUNT_RUN) {
400
401
402
403
404
405
406
407
408
409
410 j = nalt;
411 for (i = 0; i < nalt; ++i) {
412 switch (alt[i]) {
413 case 0x1e:
414 alt[j++] = 0x600005;
415 ++nlim;
416 break;
417 case 0x10000a:
418 alt[j++] = 0x1e;
419 break;
420 case 2:
421 alt[j++] = 0x500009;
422 ++nlim;
423 break;
424 case 0x500009:
425 alt[j++] = 2;
426 break;
427 case 0x10000e:
428 alt[j++] = 0x4000f4;
429 break;
430 case 0x4000f4:
431 alt[j++] = 0x10000e;
432 break;
433 }
434 }
435 nalt = j;
436 }
437
438 if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
439
440 j = 0;
441 for (i = 0; i < nalt; ++i) {
442 if (!p6_limited_pmc_event(alt[i])) {
443 alt[j] = alt[i];
444 ++j;
445 }
446 }
447 nalt = j;
448 } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
449
450 j = 0;
451 for (i = 0; i < nalt; ++i) {
452 if (p6_limited_pmc_event(alt[i])) {
453 alt[j] = alt[i];
454 ++j;
455 }
456 }
457 nalt = j;
458 }
459
460 return nalt;
461}
462
463static void p6_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
464{
465
466 if (pmc <= 3)
467 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
468}
469
470static int power6_generic_events[] = {
471 [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
472 [PERF_COUNT_HW_INSTRUCTIONS] = 2,
473 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x280030,
474 [PERF_COUNT_HW_CACHE_MISSES] = 0x30000c,
475 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x410a0,
476 [PERF_COUNT_HW_BRANCH_MISSES] = 0x400052,
477};
478
479#define C(x) PERF_COUNT_HW_CACHE_##x
480
481
482
483
484
485
486
487static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
488 [C(L1D)] = {
489 [C(OP_READ)] = { 0x280030, 0x80080 },
490 [C(OP_WRITE)] = { 0x180032, 0x80088 },
491 [C(OP_PREFETCH)] = { 0x810a4, 0 },
492 },
493 [C(L1I)] = {
494 [C(OP_READ)] = { 0, 0x100056 },
495 [C(OP_WRITE)] = { -1, -1 },
496 [C(OP_PREFETCH)] = { 0x4008c, 0 },
497 },
498 [C(LL)] = {
499 [C(OP_READ)] = { 0x150730, 0x250532 },
500 [C(OP_WRITE)] = { 0x250432, 0x150432 },
501 [C(OP_PREFETCH)] = { 0x810a6, 0 },
502 },
503 [C(DTLB)] = {
504 [C(OP_READ)] = { 0, 0x20000e },
505 [C(OP_WRITE)] = { -1, -1 },
506 [C(OP_PREFETCH)] = { -1, -1 },
507 },
508 [C(ITLB)] = {
509 [C(OP_READ)] = { 0, 0x420ce },
510 [C(OP_WRITE)] = { -1, -1 },
511 [C(OP_PREFETCH)] = { -1, -1 },
512 },
513 [C(BPU)] = {
514 [C(OP_READ)] = { 0x430e6, 0x400052 },
515 [C(OP_WRITE)] = { -1, -1 },
516 [C(OP_PREFETCH)] = { -1, -1 },
517 },
518 [C(NODE)] = {
519 [C(OP_READ)] = { -1, -1 },
520 [C(OP_WRITE)] = { -1, -1 },
521 [C(OP_PREFETCH)] = { -1, -1 },
522 },
523};
524
525static struct power_pmu power6_pmu = {
526 .name = "POWER6",
527 .n_counter = 6,
528 .max_alternatives = MAX_ALT,
529 .add_fields = 0x1555,
530 .test_adder = 0x3000,
531 .compute_mmcr = p6_compute_mmcr,
532 .get_constraint = p6_get_constraint,
533 .get_alternatives = p6_get_alternatives,
534 .disable_pmc = p6_disable_pmc,
535 .limited_pmc_event = p6_limited_pmc_event,
536 .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
537 .n_generic = ARRAY_SIZE(power6_generic_events),
538 .generic_events = power6_generic_events,
539 .cache_events = &power6_cache_events,
540};
541
542int init_power6_pmu(void)
543{
544 if (!cur_cpu_spec->oprofile_cpu_type ||
545 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
546 return -ENODEV;
547
548 return register_power_pmu(&power6_pmu);
549}
550