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18#undef DEBUG
19
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <asm/time.h>
24#include <asm/prom.h>
25#include <asm/machdep.h>
26#include <asm/mpc52xx.h>
27
28static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
29 { .compatible = "fsl,mpc5200-gpio", },
30 { .compatible = "mpc5200-gpio", },
31 {}
32};
33
34
35#define MEDIA5200_IRQ_ENABLE (0x40c)
36#define MEDIA5200_IRQ_STATUS (0x410)
37#define MEDIA5200_NUM_IRQS (6)
38#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
39
40struct media5200_irq {
41 void __iomem *regs;
42 spinlock_t lock;
43 struct irq_domain *irqhost;
44};
45struct media5200_irq media5200_irq;
46
47static void media5200_irq_unmask(struct irq_data *d)
48{
49 unsigned long flags;
50 u32 val;
51
52 spin_lock_irqsave(&media5200_irq.lock, flags);
53 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
54 val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
55 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
56 spin_unlock_irqrestore(&media5200_irq.lock, flags);
57}
58
59static void media5200_irq_mask(struct irq_data *d)
60{
61 unsigned long flags;
62 u32 val;
63
64 spin_lock_irqsave(&media5200_irq.lock, flags);
65 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
66 val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
67 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
68 spin_unlock_irqrestore(&media5200_irq.lock, flags);
69}
70
71static struct irq_chip media5200_irq_chip = {
72 .name = "Media5200 FPGA",
73 .irq_unmask = media5200_irq_unmask,
74 .irq_mask = media5200_irq_mask,
75 .irq_mask_ack = media5200_irq_mask,
76};
77
78static void media5200_irq_cascade(struct irq_desc *desc)
79{
80 struct irq_chip *chip = irq_desc_get_chip(desc);
81 int val;
82 u32 status, enable;
83
84
85 raw_spin_lock(&desc->lock);
86 chip->irq_mask(&desc->irq_data);
87 raw_spin_unlock(&desc->lock);
88
89
90
91 status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
92 enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
93 val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
94 if (val) {
95 generic_handle_domain_irq(media5200_irq.irqhost, val - 1);
96
97
98
99 }
100
101
102 raw_spin_lock(&desc->lock);
103 chip->irq_ack(&desc->irq_data);
104 if (!irqd_irq_disabled(&desc->irq_data))
105 chip->irq_unmask(&desc->irq_data);
106 raw_spin_unlock(&desc->lock);
107}
108
109static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
110 irq_hw_number_t hw)
111{
112 pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
113 irq_set_chip_data(virq, &media5200_irq);
114 irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
115 irq_set_status_flags(virq, IRQ_LEVEL);
116 return 0;
117}
118
119static int media5200_irq_xlate(struct irq_domain *h, struct device_node *ct,
120 const u32 *intspec, unsigned int intsize,
121 irq_hw_number_t *out_hwirq,
122 unsigned int *out_flags)
123{
124 if (intsize != 2)
125 return -1;
126
127 pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
128 *out_hwirq = intspec[1];
129 *out_flags = IRQ_TYPE_NONE;
130 return 0;
131}
132
133static const struct irq_domain_ops media5200_irq_ops = {
134 .map = media5200_irq_map,
135 .xlate = media5200_irq_xlate,
136};
137
138
139
140
141static void __init media5200_init_irq(void)
142{
143 struct device_node *fpga_np;
144 int cascade_virq;
145
146
147 mpc52xx_init_irq();
148
149
150 fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
151 if (!fpga_np)
152 goto out;
153 pr_debug("%s: found fpga node: %pOF\n", __func__, fpga_np);
154
155 media5200_irq.regs = of_iomap(fpga_np, 0);
156 if (!media5200_irq.regs)
157 goto out;
158 pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
159
160 cascade_virq = irq_of_parse_and_map(fpga_np, 0);
161 if (!cascade_virq)
162 goto out;
163 pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
164
165
166 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
167
168 spin_lock_init(&media5200_irq.lock);
169
170 media5200_irq.irqhost = irq_domain_add_linear(fpga_np,
171 MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
172 if (!media5200_irq.irqhost)
173 goto out;
174 pr_debug("%s: allocated irqhost\n", __func__);
175
176 irq_set_handler_data(cascade_virq, &media5200_irq);
177 irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
178
179 return;
180
181 out:
182 pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
183}
184
185
186
187
188static void __init media5200_setup_arch(void)
189{
190
191 struct device_node *np;
192 struct mpc52xx_gpio __iomem *gpio;
193 u32 port_config;
194
195 if (ppc_md.progress)
196 ppc_md.progress("media5200_setup_arch()", 0);
197
198
199 mpc52xx_map_common_devices();
200
201
202 mpc5200_setup_xlb_arbiter();
203
204 np = of_find_matching_node(NULL, mpc5200_gpio_ids);
205 gpio = of_iomap(np, 0);
206 of_node_put(np);
207 if (!gpio) {
208 printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
209 __func__);
210 return;
211 }
212
213
214 port_config = in_be32(&gpio->port_config);
215
216 port_config &= ~0x03000000;
217 port_config |= 0x01000000;
218
219 out_be32(&gpio->port_config, port_config);
220
221
222 iounmap(gpio);
223
224}
225
226
227static const char * const board[] __initconst = {
228 "fsl,media5200",
229 NULL
230};
231
232
233
234
235static int __init media5200_probe(void)
236{
237 return of_device_compatible_match(of_root, board);
238}
239
240define_machine(media5200_platform) {
241 .name = "media5200-platform",
242 .probe = media5200_probe,
243 .setup_arch = media5200_setup_arch,
244 .discover_phbs = mpc52xx_setup_pci,
245 .init = mpc52xx_declare_of_platform_devices,
246 .init_IRQ = media5200_init_irq,
247 .get_irq = mpc52xx_get_irq,
248 .restart = mpc52xx_restart,
249 .calibrate_decr = generic_calibrate_decr,
250};
251