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51#include <linux/device.h>
52#include <linux/irq.h>
53#include <linux/interrupt.h>
54#include <linux/io.h>
55#include <linux/list.h>
56#include <linux/mutex.h>
57#include <linux/of.h>
58#include <linux/of_platform.h>
59#include <linux/of_gpio.h>
60#include <linux/kernel.h>
61#include <linux/slab.h>
62#include <linux/fs.h>
63#include <linux/watchdog.h>
64#include <linux/miscdevice.h>
65#include <linux/uaccess.h>
66#include <linux/module.h>
67#include <asm/div64.h>
68#include <asm/mpc52xx.h>
69
70MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
71MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
72MODULE_LICENSE("GPL");
73
74
75
76
77
78
79
80
81
82
83
84
85struct mpc52xx_gpt_priv {
86 struct list_head list;
87 struct device *dev;
88 struct mpc52xx_gpt __iomem *regs;
89 raw_spinlock_t lock;
90 struct irq_domain *irqhost;
91 u32 ipb_freq;
92 u8 wdt_mode;
93
94#if defined(CONFIG_GPIOLIB)
95 struct gpio_chip gc;
96#endif
97};
98
99LIST_HEAD(mpc52xx_gpt_list);
100DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
101
102#define MPC52xx_GPT_MODE_MS_MASK (0x07)
103#define MPC52xx_GPT_MODE_MS_IC (0x01)
104#define MPC52xx_GPT_MODE_MS_OC (0x02)
105#define MPC52xx_GPT_MODE_MS_PWM (0x03)
106#define MPC52xx_GPT_MODE_MS_GPIO (0x04)
107
108#define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
109#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
110#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
111
112#define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
113#define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
114#define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
115#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
116#define MPC52xx_GPT_MODE_WDT_EN (0x8000)
117
118#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
119#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
120#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
121#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
122
123#define MPC52xx_GPT_MODE_WDT_PING (0xa5)
124
125#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
126
127#define MPC52xx_GPT_CAN_WDT (1 << 0)
128#define MPC52xx_GPT_IS_WDT (1 << 1)
129
130
131
132
133
134
135static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
136{
137 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
138 unsigned long flags;
139
140 raw_spin_lock_irqsave(&gpt->lock, flags);
141 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
142 raw_spin_unlock_irqrestore(&gpt->lock, flags);
143}
144
145static void mpc52xx_gpt_irq_mask(struct irq_data *d)
146{
147 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
148 unsigned long flags;
149
150 raw_spin_lock_irqsave(&gpt->lock, flags);
151 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
152 raw_spin_unlock_irqrestore(&gpt->lock, flags);
153}
154
155static void mpc52xx_gpt_irq_ack(struct irq_data *d)
156{
157 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
158
159 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
160}
161
162static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
163{
164 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
165 unsigned long flags;
166 u32 reg;
167
168 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
169
170 raw_spin_lock_irqsave(&gpt->lock, flags);
171 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
172 if (flow_type & IRQF_TRIGGER_RISING)
173 reg |= MPC52xx_GPT_MODE_ICT_RISING;
174 if (flow_type & IRQF_TRIGGER_FALLING)
175 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
176 out_be32(&gpt->regs->mode, reg);
177 raw_spin_unlock_irqrestore(&gpt->lock, flags);
178
179 return 0;
180}
181
182static struct irq_chip mpc52xx_gpt_irq_chip = {
183 .name = "MPC52xx GPT",
184 .irq_unmask = mpc52xx_gpt_irq_unmask,
185 .irq_mask = mpc52xx_gpt_irq_mask,
186 .irq_ack = mpc52xx_gpt_irq_ack,
187 .irq_set_type = mpc52xx_gpt_irq_set_type,
188};
189
190static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
191{
192 struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
193 u32 status;
194
195 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
196 if (status)
197 generic_handle_domain_irq(gpt->irqhost, 0);
198}
199
200static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
201 irq_hw_number_t hw)
202{
203 struct mpc52xx_gpt_priv *gpt = h->host_data;
204
205 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
206 irq_set_chip_data(virq, gpt);
207 irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
208
209 return 0;
210}
211
212static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
213 const u32 *intspec, unsigned int intsize,
214 irq_hw_number_t *out_hwirq,
215 unsigned int *out_flags)
216{
217 struct mpc52xx_gpt_priv *gpt = h->host_data;
218
219 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
220
221 if ((intsize < 1) || (intspec[0] > 3)) {
222 dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);
223 return -EINVAL;
224 }
225
226 *out_hwirq = 0;
227 *out_flags = intspec[0];
228
229 return 0;
230}
231
232static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
233 .map = mpc52xx_gpt_irq_map,
234 .xlate = mpc52xx_gpt_irq_xlate,
235};
236
237static void
238mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
239{
240 int cascade_virq;
241 unsigned long flags;
242 u32 mode;
243
244 cascade_virq = irq_of_parse_and_map(node, 0);
245 if (!cascade_virq)
246 return;
247
248 gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
249 if (!gpt->irqhost) {
250 dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
251 return;
252 }
253
254 irq_set_handler_data(cascade_virq, gpt);
255 irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
256
257
258
259
260 raw_spin_lock_irqsave(&gpt->lock, flags);
261 mode = in_be32(&gpt->regs->mode);
262 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
263 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
264 raw_spin_unlock_irqrestore(&gpt->lock, flags);
265
266 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
267}
268
269
270
271
272
273#if defined(CONFIG_GPIOLIB)
274static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
275{
276 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
277
278 return (in_be32(&gpt->regs->status) >> 8) & 1;
279}
280
281static void
282mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
283{
284 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
285 unsigned long flags;
286 u32 r;
287
288 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
289 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
290
291 raw_spin_lock_irqsave(&gpt->lock, flags);
292 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
293 raw_spin_unlock_irqrestore(&gpt->lock, flags);
294}
295
296static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
297{
298 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
299 unsigned long flags;
300
301 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
302
303 raw_spin_lock_irqsave(&gpt->lock, flags);
304 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
305 raw_spin_unlock_irqrestore(&gpt->lock, flags);
306
307 return 0;
308}
309
310static int
311mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
312{
313 mpc52xx_gpt_gpio_set(gc, gpio, val);
314 return 0;
315}
316
317static void
318mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
319{
320 int rc;
321
322
323
324 if (!of_find_property(node, "gpio-controller", NULL))
325 return;
326
327 gpt->gc.label = kasprintf(GFP_KERNEL, "%pOF", node);
328 if (!gpt->gc.label) {
329 dev_err(gpt->dev, "out of memory\n");
330 return;
331 }
332
333 gpt->gc.ngpio = 1;
334 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
335 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
336 gpt->gc.get = mpc52xx_gpt_gpio_get;
337 gpt->gc.set = mpc52xx_gpt_gpio_set;
338 gpt->gc.base = -1;
339 gpt->gc.of_node = node;
340
341
342 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
343 MPC52xx_GPT_MODE_MS_GPIO);
344
345 rc = gpiochip_add_data(&gpt->gc, gpt);
346 if (rc)
347 dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);
348
349 dev_dbg(gpt->dev, "%s() complete.\n", __func__);
350}
351#else
352static void
353mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
354#endif
355
356
357
358
359
360
361
362
363
364struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
365{
366 struct mpc52xx_gpt_priv *gpt;
367 struct list_head *pos;
368
369
370 mutex_lock(&mpc52xx_gpt_list_mutex);
371 list_for_each(pos, &mpc52xx_gpt_list) {
372 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
373 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
374 mutex_unlock(&mpc52xx_gpt_list_mutex);
375 return gpt;
376 }
377 }
378 mutex_unlock(&mpc52xx_gpt_list_mutex);
379
380 return NULL;
381}
382EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
383
384static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
385 int continuous, int as_wdt)
386{
387 u32 clear, set;
388 u64 clocks;
389 u32 prescale;
390 unsigned long flags;
391
392 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
393 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
394 if (as_wdt) {
395 clear |= MPC52xx_GPT_MODE_IRQ_EN;
396 set |= MPC52xx_GPT_MODE_WDT_EN;
397 } else if (continuous)
398 set |= MPC52xx_GPT_MODE_CONTINUOUS;
399
400
401
402
403
404 clocks = period * (u64)gpt->ipb_freq;
405 do_div(clocks, 1000000000);
406
407
408 if (clocks > 0xffffffff)
409 return -EINVAL;
410
411
412
413
414
415
416
417
418
419
420
421
422
423 prescale = (clocks >> 16) + 1;
424 do_div(clocks, prescale);
425 if (clocks > 0xffff) {
426 pr_err("calculation error; prescale:%x clocks:%llx\n",
427 prescale, clocks);
428 return -EINVAL;
429 }
430
431
432 raw_spin_lock_irqsave(&gpt->lock, flags);
433 if (as_wdt)
434 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
435 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
436 raw_spin_unlock_irqrestore(&gpt->lock, flags);
437 return -EBUSY;
438 }
439 out_be32(&gpt->regs->count, prescale << 16 | clocks);
440 clrsetbits_be32(&gpt->regs->mode, clear, set);
441 raw_spin_unlock_irqrestore(&gpt->lock, flags);
442
443 return 0;
444}
445
446
447
448
449
450
451
452
453
454int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
455 int continuous)
456{
457 return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
458}
459EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
460
461
462
463
464
465
466
467int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
468{
469 unsigned long flags;
470
471
472 raw_spin_lock_irqsave(&gpt->lock, flags);
473 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
474 raw_spin_unlock_irqrestore(&gpt->lock, flags);
475 return -EBUSY;
476 }
477
478 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
479 raw_spin_unlock_irqrestore(&gpt->lock, flags);
480 return 0;
481}
482EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
483
484
485
486
487
488
489
490u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
491{
492 u64 period;
493 u64 prescale;
494 unsigned long flags;
495
496 raw_spin_lock_irqsave(&gpt->lock, flags);
497 period = in_be32(&gpt->regs->count);
498 raw_spin_unlock_irqrestore(&gpt->lock, flags);
499
500 prescale = period >> 16;
501 period &= 0xffff;
502 if (prescale == 0)
503 prescale = 0x10000;
504 period = period * prescale * 1000000000ULL;
505 do_div(period, (u64)gpt->ipb_freq);
506 return period;
507}
508EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
509
510#if defined(CONFIG_MPC5200_WDT)
511
512
513
514
515#define WDT_IDENTITY "mpc52xx watchdog on GPT0"
516
517
518static unsigned long wdt_is_active;
519
520
521static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
522
523
524static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
525{
526 unsigned long flags;
527
528 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
529 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
530 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
531}
532
533
534static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
535 size_t len, loff_t *ppos)
536{
537 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
538 mpc52xx_gpt_wdt_ping(gpt_wdt);
539 return 0;
540}
541
542static const struct watchdog_info mpc5200_wdt_info = {
543 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
544 .identity = WDT_IDENTITY,
545};
546
547static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
548 unsigned long arg)
549{
550 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
551 int __user *data = (int __user *)arg;
552 int timeout;
553 u64 real_timeout;
554 int ret = 0;
555
556 switch (cmd) {
557 case WDIOC_GETSUPPORT:
558 ret = copy_to_user(data, &mpc5200_wdt_info,
559 sizeof(mpc5200_wdt_info));
560 if (ret)
561 ret = -EFAULT;
562 break;
563
564 case WDIOC_GETSTATUS:
565 case WDIOC_GETBOOTSTATUS:
566 ret = put_user(0, data);
567 break;
568
569 case WDIOC_KEEPALIVE:
570 mpc52xx_gpt_wdt_ping(gpt_wdt);
571 break;
572
573 case WDIOC_SETTIMEOUT:
574 ret = get_user(timeout, data);
575 if (ret)
576 break;
577 real_timeout = (u64) timeout * 1000000000ULL;
578 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
579 if (ret)
580 break;
581
582 fallthrough;
583
584 case WDIOC_GETTIMEOUT:
585
586
587
588
589
590
591 real_timeout =
592 mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
593 do_div(real_timeout, 1000000000ULL);
594 timeout = (int) real_timeout;
595 ret = put_user(timeout, data);
596 break;
597
598 default:
599 ret = -ENOTTY;
600 }
601 return ret;
602}
603
604static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
605{
606 int ret;
607
608
609 if (!mpc52xx_gpt_wdt)
610 return -ENODEV;
611
612
613 if (test_and_set_bit(0, &wdt_is_active))
614 return -EBUSY;
615
616
617 ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
618 0, 1);
619 if (ret) {
620 clear_bit(0, &wdt_is_active);
621 return ret;
622 }
623
624 file->private_data = mpc52xx_gpt_wdt;
625 return stream_open(inode, file);
626}
627
628static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
629{
630
631#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
632 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
633 unsigned long flags;
634
635 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
636 clrbits32(&gpt_wdt->regs->mode,
637 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
638 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
639 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
640#endif
641 clear_bit(0, &wdt_is_active);
642 return 0;
643}
644
645
646static const struct file_operations mpc52xx_wdt_fops = {
647 .owner = THIS_MODULE,
648 .llseek = no_llseek,
649 .write = mpc52xx_wdt_write,
650 .unlocked_ioctl = mpc52xx_wdt_ioctl,
651 .compat_ioctl = compat_ptr_ioctl,
652 .open = mpc52xx_wdt_open,
653 .release = mpc52xx_wdt_release,
654};
655
656static struct miscdevice mpc52xx_wdt_miscdev = {
657 .minor = WATCHDOG_MINOR,
658 .name = "watchdog",
659 .fops = &mpc52xx_wdt_fops,
660};
661
662static int mpc52xx_gpt_wdt_init(void)
663{
664 int err;
665
666
667 err = misc_register(&mpc52xx_wdt_miscdev);
668 if (err)
669 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
670 else
671 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
672 return err;
673}
674
675static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
676 const u32 *period)
677{
678 u64 real_timeout;
679
680
681 mpc52xx_gpt_wdt = gpt;
682
683
684 if (!period || *period == 0)
685 return 0;
686
687 real_timeout = (u64) *period * 1000000000ULL;
688 if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
689 dev_warn(gpt->dev, "starting as wdt failed\n");
690 else
691 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
692 return 0;
693}
694
695#else
696
697static int mpc52xx_gpt_wdt_init(void)
698{
699 return 0;
700}
701
702static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
703 const u32 *period)
704{
705 return 0;
706}
707
708#endif
709
710
711
712
713static int mpc52xx_gpt_probe(struct platform_device *ofdev)
714{
715 struct mpc52xx_gpt_priv *gpt;
716
717 gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL);
718 if (!gpt)
719 return -ENOMEM;
720
721 raw_spin_lock_init(&gpt->lock);
722 gpt->dev = &ofdev->dev;
723 gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
724 gpt->regs = of_iomap(ofdev->dev.of_node, 0);
725 if (!gpt->regs)
726 return -ENOMEM;
727
728 dev_set_drvdata(&ofdev->dev, gpt);
729
730 mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node);
731 mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
732
733 mutex_lock(&mpc52xx_gpt_list_mutex);
734 list_add(&gpt->list, &mpc52xx_gpt_list);
735 mutex_unlock(&mpc52xx_gpt_list_mutex);
736
737
738 if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
739 of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
740 const u32 *on_boot_wdt;
741
742 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
743 on_boot_wdt = of_get_property(ofdev->dev.of_node,
744 "fsl,wdt-on-boot", NULL);
745 if (on_boot_wdt) {
746 dev_info(gpt->dev, "used as watchdog\n");
747 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
748 } else
749 dev_info(gpt->dev, "can function as watchdog\n");
750 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
751 }
752
753 return 0;
754}
755
756static int mpc52xx_gpt_remove(struct platform_device *ofdev)
757{
758 return -EBUSY;
759}
760
761static const struct of_device_id mpc52xx_gpt_match[] = {
762 { .compatible = "fsl,mpc5200-gpt", },
763
764
765 { .compatible = "fsl,mpc5200-gpt-gpio", },
766 { .compatible = "mpc5200-gpt", },
767 {}
768};
769
770static struct platform_driver mpc52xx_gpt_driver = {
771 .driver = {
772 .name = "mpc52xx-gpt",
773 .of_match_table = mpc52xx_gpt_match,
774 },
775 .probe = mpc52xx_gpt_probe,
776 .remove = mpc52xx_gpt_remove,
777};
778
779static int __init mpc52xx_gpt_init(void)
780{
781 return platform_driver_register(&mpc52xx_gpt_driver);
782}
783
784
785subsys_initcall(mpc52xx_gpt_init);
786device_initcall(mpc52xx_gpt_wdt_init);
787