// SPDX-License-Identifier: GPL-2.0-or-later
/* ppc-opc.c -- PowerPC opcode list
   Copyright (C) 1994-2016 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

   This file is part of GDB, GAS, and the GNU binutils.

 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include "nonstdio.h"
#include "ppc.h"

#define ATTRIBUTE_UNUSED
#define _(x)    x

/* This file holds the PowerPC opcode table.  The opcode table
   includes almost all of the extended instruction mnemonics.  This
   permits the disassembler to use them, and simplifies the assembler
   logic, at the cost of increasing the table size.  The table is
   strictly constant data, so the compiler should be able to put it in
   the .text section.

   This file also holds the operand table.  All knowledge about
   inserting operands into instructions and vice-versa is kept in this
   file.  */

/* Local insertion and extraction functions.  */

static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
static long extract_arx (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
static long extract_ary (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
static long extract_bat (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
static long extract_bba (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
static long extract_bdm (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
static long extract_bdp (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
static long extract_bo (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
static long extract_boe (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
static long extract_dxd (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
static long extract_fxm (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_li20 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
static long extract_mbe (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
static long extract_nb (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
static long extract_nsi (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
static long extract_oimm (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
static long extract_rbs (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
static long extract_rx (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
static long extract_ry (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
static long extract_spr (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
static long extract_sprg (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
static long extract_tbr (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
static long extract_dm (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
static long extract_vleui (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
static long extract_vleil (unsigned long, ppc_cpu_t, int *);

/* The operands table.

   The fields are bitm, shift, insert, extract, flags.

   We used to put parens around the various additions, like the one
   for BA just below.  However, that caused trouble with feeble
   compilers with a limit on depth of a parenthesized expression, like
   (reportedly) the compiler in Microsoft Developer Studio 5.  So we
   omit the parens, since the macros are never used in a context where
   the addition will be ambiguous.  */

const struct powerpc_operand powerpc_operands[] =
{
  /* The zero index is used to indicate the end of the list of
     operands.  */
#define UNUSED 0
  { 0, 0, NULL, NULL, 0 },

  /* The BA field in an XL form instruction.  */
#define BA UNUSED + 1
  /* The BI field in a B form or XL form instruction.  */
#define BI BA
#define BI_MASK (0x1f << 16)
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },

  /* The BA field in an XL form instruction when it must be the same
     as the BT field in the same instruction.  */
#define BAT BA + 1
  { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },

  /* The BB field in an XL form instruction.  */
#define BB BAT + 1
#define BB_MASK (0x1f << 11)
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },

  /* The BB field in an XL form instruction when it must be the same
     as the BA field in the same instruction.  */
#define BBA BB + 1
  /* The VB field in a VX form instruction when it must be the same
     as the VA field in the same instruction.  */
#define VBA BBA
  { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },

  /* The BD field in a B form instruction.  The lower two bits are
     forced to zero.  */
#define BD BBA + 1
  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when absolute addressing is
     used.  */
#define BDA BD + 1
  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used.
     This sets the y bit of the BO field appropriately.  */
#define BDM BDA + 1
  { 0xfffc, 0, insert_bdm, extract_bdm,
    PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used
     and absolute address is used.  */
#define BDMA BDM + 1
  { 0xfffc, 0, insert_bdm, extract_bdm,
    PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used.
     This sets the y bit of the BO field appropriately.  */
#define BDP BDMA + 1
  { 0xfffc, 0, insert_bdp, extract_bdp,
    PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used
     and absolute addressing is used.  */
#define BDPA BDP + 1
  { 0xfffc, 0, insert_bdp, extract_bdp,
    PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BF field in an X or XL form instruction.  */
#define BF BDPA + 1
  /* The CRFD field in an X form instruction.  */
#define CRFD BF
  /* The CRD field in an XL form instruction.  */
#define CRD BF
  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },

  /* The BF field in an X or XL form instruction.  */
#define BFF BF + 1
  { 0x7, 23, NULL, NULL, 0 },

  /* An optional BF field.  This is used for comparison instructions,
     in which an omitted BF field is taken as zero.  */
#define OBF BFF + 1
  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },

  /* The BFA field in an X or XL form instruction.  */
#define BFA OBF + 1
  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },

  /* The BO field in a B form instruction.  Certain values are
     illegal.  */
#define BO BFA + 1
#define BO_MASK (0x1f << 21)
  { 0x1f, 21, insert_bo, extract_bo, 0 },

  /* The BO field in a B form instruction when the + or - modifier is
     used.  This is like the BO field, but it must be even.  */
#define BOE BO + 1
  { 0x1e, 21, insert_boe, extract_boe, 0 },

  /* The RM field in an X form instruction.  */
#define RM BOE + 1
  { 0x3, 11, NULL, NULL, 0 },

#define BH RM + 1
  { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The BT field in an X or XL form instruction.  */
#define BT BH + 1
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },

  /* The BI16 field in a BD8 form instruction.  */
#define BI16 BT + 1
  { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },

  /* The BI32 field in a BD15 form instruction.  */
#define BI32 BI16 + 1
  { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },

  /* The BO32 field in a BD15 form instruction.  */
#define BO32 BI32 + 1
  { 0x3, 20, NULL, NULL, 0 },

  /* The B8 field in a BD8 form instruction.  */
#define B8 BO32 + 1
  { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The B15 field in a BD15 form instruction.  The lowest bit is
     forced to zero.  */
#define B15 B8 + 1
  { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The B24 field in a BD24 form instruction.  The lowest bit is
     forced to zero.  */
#define B24 B15 + 1
  { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The condition register number portion of the BI field in a B form
     or XL form instruction.  This is used for the extended
     conditional branch mnemonics, which set the lower two bits of the
     BI field.  This field is optional.  */
#define CR B24 + 1
  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },

  /* The CRB field in an X form instruction.  */
#define CRB CR + 1
  /* The MB field in an M form instruction.  */
#define MB CRB
#define MB_MASK (0x1f << 6)
  { 0x1f, 6, NULL, NULL, 0 },

  /* The CRD32 field in an XL form instruction.  */
#define CRD32 CRB + 1
  { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },

  /* The CRFS field in an X form instruction.  */
#define CRFS CRD32 + 1
  { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },

#define CRS CRFS + 1
  { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },

  /* The CT field in an X form instruction.  */
#define CT CRS + 1
  /* The MO field in an mbar instruction.  */
#define MO CT
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The D field in a D form instruction.  This is a displacement off
     a register, and implies that the next operand is a register in
     parentheses.  */
#define D CT + 1
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The D8 field in a D form instruction.  This is a displacement off
     a register, and implies that the next operand is a register in
     parentheses.  */
#define D8 D + 1
  { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DCMX field in an X form instruction.  */
#define DCMX D8 + 1
  { 0x7f, 16, NULL, NULL, 0 },

  /* The split DCMX field in an X form instruction.  */
#define DCMXS DCMX + 1
  { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },

  /* The DQ field in a DQ form instruction.  This is like D, but the
     lower four bits are forced to zero. */
#define DQ DCMXS + 1
  { 0xfff0, 0, NULL, NULL,
    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },

  /* The DS field in a DS form instruction.  This is like D, but the
     lower two bits are forced to zero.  */
#define DS DQ + 1
  { 0xfffc, 0, NULL, NULL,
    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },

  /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
     unsigned imediate */
#define DUIS DS + 1
#define BHRBE DUIS
  { 0x3ff, 11, NULL, NULL, 0 },

  /* The split D field in a DX form instruction.  */
#define DXD DUIS + 1
  { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
    PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},

  /* The split ND field in a DX form instruction.
     This is the same as the DX field, only negated.  */
#define NDXD DXD + 1
  { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
    PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},

  /* The E field in a wrteei instruction.  */
  /* And the W bit in the pair singles instructions.  */
  /* And the ST field in a VX form instruction.  */
#define E NDXD + 1
#define PSW E
#define ST E
  { 0x1, 15, NULL, NULL, 0 },

  /* The FL1 field in a POWER SC form instruction.  */
#define FL1 E + 1
  /* The U field in an X form instruction.  */
#define U FL1
  { 0xf, 12, NULL, NULL, 0 },

  /* The FL2 field in a POWER SC form instruction.  */
#define FL2 FL1 + 1
  { 0x7, 2, NULL, NULL, 0 },

  /* The FLM field in an XFL form instruction.  */
#define FLM FL2 + 1
  { 0xff, 17, NULL, NULL, 0 },

  /* The FRA field in an X or A form instruction.  */
#define FRA FLM + 1
#define FRA_MASK (0x1f << 16)
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRAp field of DFP instructions.  */
#define FRAp FRA + 1
  { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRB field in an X or A form instruction.  */
#define FRB FRAp + 1
#define FRB_MASK (0x1f << 11)
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRBp field of DFP instructions.  */
#define FRBp FRB + 1
  { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRC field in an A form instruction.  */
#define FRC FRBp + 1
#define FRC_MASK (0x1f << 6)
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRS field in an X form instruction or the FRT field in a D, X
     or A form instruction.  */
#define FRS FRC + 1
#define FRT FRS
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
     instructions.  */
#define FRSp FRS + 1
#define FRTp FRSp
  { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },

  /* The FXM field in an XFX instruction.  */
#define FXM FRSp + 1
  { 0xff, 12, insert_fxm, extract_fxm, 0 },

  /* Power4 version for mfcr.  */
#define FXM4 FXM + 1
  { 0xff, 12, insert_fxm, extract_fxm,
    PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
  /* If the FXM4 operand is ommitted, use the sentinel value -1.  */
  { -1, -1, NULL, NULL, 0},

  /* The IMM20 field in an LI instruction.  */
#define IMM20 FXM4 + 2
  { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},

  /* The L field in a D or X form instruction.  */
#define L IMM20 + 1
  { 0x1, 21, NULL, NULL, 0 },

  /* The optional L field in tlbie and tlbiel instructions.  */
#define LOPT L + 1
  /* The R field in a HTM X form instruction.  */
#define HTM_R LOPT
  { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The optional (for 32-bit) L field in cmp[l][i] instructions.  */
#define L32OPT LOPT + 1
  { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },

  /* The L field in dcbf instruction.  */
#define L2OPT L32OPT + 1
  { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The LEV field in a POWER SVC form instruction.  */
#define SVC_LEV L2OPT + 1
  { 0x7f, 5, NULL, NULL, 0 },

  /* The LEV field in an SC form instruction.  */
#define LEV SVC_LEV + 1
  { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The LI field in an I form instruction.  The lower two bits are
     forced to zero.  */
#define LI LEV + 1
  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The LI field in an I form instruction when used as an absolute
     address.  */
#define LIA LI + 1
  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The LS or WC field in an X (sync or wait) form instruction.  */
#define LS LIA + 1
#define WC LS
  { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },

  /* The ME field in an M form instruction.  */
#define ME LS + 1
#define ME_MASK (0x1f << 1)
  { 0x1f, 1, NULL, NULL, 0 },

  /* The MB and ME fields in an M form instruction expressed a single
     operand which is a bitmask indicating which bits to select.  This
     is a two operand form using PPC_OPERAND_NEXT.  See the
     description in opcode/ppc.h for what this means.  */
#define MBE ME + 1
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
  { -1, 0, insert_mbe, extract_mbe, 0 },

  /* The MB or ME field in an MD or MDS form instruction.  The high
     bit is wrapped to the low end.  */
#define MB6 MBE + 2
#define ME6 MB6
#define MB6_MASK (0x3f << 5)
  { 0x3f, 5, insert_mb6, extract_mb6, 0 },

  /* The NB field in an X form instruction.  The value 32 is stored as
     0.  */
#define NB MB6 + 1
  { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },

  /* The NBI field in an lswi instruction, which has special value
     restrictions.  The value 32 is stored as 0.  */
#define NBI NB + 1
  { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },

  /* The NSI field in a D form instruction.  This is the same as the
     SI field, only negated.  */
#define NSI NBI + 1
  { 0xffff, 0, insert_nsi, extract_nsi,
    PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },

  /* The NSI field in a D form instruction when we accept a wide range
     of positive values.  */
#define NSISIGNOPT NSI + 1
  { 0xffff, 0, insert_nsi, extract_nsi,
    PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
#define RA NSISIGNOPT + 1
#define RA_MASK (0x1f << 16)
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },

  /* As above, but 0 in the RA field means zero, not r0.  */
#define RA0 RA + 1
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in the DQ form lq or an lswx instruction, which have special
     value restrictions.  */
#define RAQ RA0 + 1
#define RAX RAQ
  { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in a D or X form instruction which is an updating
     load, which means that the RA field may not be zero and may not
     equal the RT field.  */
#define RAL RAQ + 1
  { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in an lmw instruction, which has special value
     restrictions.  */
#define RAM RAL + 1
  { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in a D or X form instruction which is an updating
     store or an updating floating point load, which means that the RA
     field may not be zero.  */
#define RAS RAM + 1
  { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field of the tlbwe, dccci and iccci instructions,
     which are optional.  */
#define RAOPT RAS + 1
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

  /* The RB field in an X, XO, M, or MDS form instruction.  */
#define RB RAOPT + 1
#define RB_MASK (0x1f << 11)
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },

  /* The RB field in an X form instruction when it must be the same as
     the RS field in the instruction.  This is used for extended
     mnemonics like mr.  */
#define RBS RB + 1
  { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },

  /* The RB field in an lswx instruction, which has special value
     restrictions.  */
#define RBX RBS + 1
  { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },

  /* The RB field of the dccci and iccci instructions, which are optional.  */
#define RBOPT RBX + 1
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

  /* The RC register field in an maddld, maddhd or maddhdu instruction.  */
#define RC RBOPT + 1
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },

  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
     instruction or the RT field in a D, DS, X, XFX or XO form
     instruction.  */
#define RS RC + 1
#define RT RS
#define RT_MASK (0x1f << 21)
#define RD RS
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },

  /* The RS and RT fields of the DS form stq and DQ form lq instructions,
     which have special value restrictions.  */
#define RSQ RS + 1
#define RTQ RSQ
  { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },

  /* The RS field of the tlbwe instruction, which is optional.  */
#define RSO RSQ + 1
#define RTO RSO
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

  /* The RX field of the SE_RR form instruction.  */
#define RX RSO + 1
  { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },

  /* The ARX field of the SE_RR form instruction.  */
#define ARX RX + 1
  { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },

  /* The RY field of the SE_RR form instruction.  */
#define RY ARX + 1
#define RZ RY
  { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },

  /* The ARY field of the SE_RR form instruction.  */
#define ARY RY + 1
  { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },

  /* The SCLSCI8 field in a D form instruction.  */
#define SCLSCI8 ARY + 1
  { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },

  /* The SCLSCI8N field in a D form instruction.  This is the same as the
     SCLSCI8 field, only negated.  */
#define SCLSCI8N SCLSCI8 + 1
  { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
    PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },

  /* The SD field of the SD4 form instruction.  */
#define SE_SD SCLSCI8N + 1
  { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },

  /* The SD field of the SD4 form instruction, for halfword.  */
#define SE_SDH SE_SD + 1
  { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },

  /* The SD field of the SD4 form instruction, for word.  */
#define SE_SDW SE_SDH + 1
  { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },

  /* The SH field in an X or M form instruction.  */
#define SH SE_SDW + 1
#define SH_MASK (0x1f << 11)
  /* The other UIMM field in a EVX form instruction.  */
#define EVUIMM SH
  /* The FC field in an atomic X form instruction.  */
#define FC SH
  { 0x1f, 11, NULL, NULL, 0 },

  /* The SI field in a HTM X form instruction.  */
#define HTM_SI SH + 1
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },

  /* The SH field in an MD form instruction.  This is split.  */
#define SH6 HTM_SI + 1
#define SH6_MASK ((0x1f << 11) | (1 << 1))
  { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },

  /* The SH field of the tlbwe instruction, which is optional.  */
#define SHO SH6 + 1
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The SI field in a D form instruction.  */
#define SI SHO + 1
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },

  /* The SI field in a D form instruction when we accept a wide range
     of positive values.  */
#define SISIGNOPT SI + 1
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The SI8 field in a D form instruction.  */
#define SI8 SISIGNOPT + 1
  { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },

  /* The SPR field in an XFX form instruction.  This is flipped--the
     lower 5 bits are stored in the upper 5 and vice- versa.  */
#define SPR SI8 + 1
#define PMR SPR
#define TMR SPR
#define SPR_MASK (0x3ff << 11)
  { 0x3ff, 11, insert_spr, extract_spr, 0 },

  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
#define SPRBAT SPR + 1
#define SPRBAT_MASK (0x3 << 17)
  { 0x3, 17, NULL, NULL, 0 },

  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
#define SPRG SPRBAT + 1
  { 0x1f, 16, insert_sprg, extract_sprg, 0 },

  /* The SR field in an X form instruction.  */
#define SR SPRG + 1
  /* The 4-bit UIMM field in a VX form instruction.  */
#define UIMM4 SR
  { 0xf, 16, NULL, NULL, 0 },

  /* The STRM field in an X AltiVec form instruction.  */
#define STRM SR + 1
  /* The T field in a tlbilx form instruction.  */
#define T STRM
  /* The L field in wclr instructions.  */
#define L2 STRM
  { 0x3, 21, NULL, NULL, 0 },

  /* The ESYNC field in an X (sync) form instruction.  */
#define ESYNC STRM + 1
  { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },

  /* The SV field in a POWER SC form instruction.  */
#define SV ESYNC + 1
  { 0x3fff, 2, NULL, NULL, 0 },

  /* The TBR field in an XFX form instruction.  This is like the SPR
     field, but it is optional.  */
#define TBR SV + 1
  { 0x3ff, 11, insert_tbr, extract_tbr,
    PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
  /* If the TBR operand is ommitted, use the value 268.  */
  { -1, 268, NULL, NULL, 0},

  /* The TO field in a D or X form instruction.  */
#define TO TBR + 2
#define DUI TO
#define TO_MASK (0x1f << 21)
  { 0x1f, 21, NULL, NULL, 0 },

  /* The UI field in a D form instruction.  */
#define UI TO + 1
  { 0xffff, 0, NULL, NULL, 0 },

#define UISIGNOPT UI + 1
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },

  /* The IMM field in an SE_IM5 instruction.  */
#define UI5 UISIGNOPT + 1
  { 0x1f, 4, NULL, NULL, 0 },

  /* The OIMM field in an SE_OIM5 instruction.  */
#define OIMM5 UI5 + 1
  { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },

  /* The UI7 field in an SE_LI instruction.  */
#define UI7 OIMM5 + 1
  { 0x7f, 4, NULL, NULL, 0 },

  /* The VA field in a VA, VX or VXR form instruction.  */
#define VA UI7 + 1
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },

  /* The VB field in a VA, VX or VXR form instruction.  */
#define VB VA + 1
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },

  /* The VC field in a VA form instruction.  */
#define VC VB + 1
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },

  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
#define VD VC + 1
#define VS VD
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },

  /* The SIMM field in a VX form instruction, and TE in Z form.  */
#define SIMM VD + 1
#define TE SIMM
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},

  /* The UIMM field in a VX form instruction.  */
#define UIMM SIMM + 1
#define DCTL UIMM
  { 0x1f, 16, NULL, NULL, 0 },

  /* The 3-bit UIMM field in a VX form instruction.  */
#define UIMM3 UIMM + 1
  { 0x7, 16, NULL, NULL, 0 },

  /* The 6-bit UIM field in a X form instruction.  */
#define UIM6 UIMM3 + 1
  { 0x3f, 16, NULL, NULL, 0 },

  /* The SIX field in a VX form instruction.  */
#define SIX UIM6 + 1
  { 0xf, 11, NULL, NULL, 0 },

  /* The PS field in a VX form instruction.  */
#define PS SIX + 1
  { 0x1, 9, NULL, NULL, 0 },

  /* The SHB field in a VA form instruction.  */
#define SHB PS + 1
  { 0xf, 6, NULL, NULL, 0 },

  /* The other UIMM field in a half word EVX form instruction.  */
#define EVUIMM_2 SHB + 1
  { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },

  /* The other UIMM field in a word EVX form instruction.  */
#define EVUIMM_4 EVUIMM_2 + 1
  { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },

  /* The other UIMM field in a double EVX form instruction.  */
#define EVUIMM_8 EVUIMM_4 + 1
  { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },

  /* The WS or DRM field in an X form instruction.  */
#define WS EVUIMM_8 + 1
#define DRM WS
  { 0x7, 11, NULL, NULL, 0 },

  /* PowerPC paired singles extensions.  */
  /* W bit in the pair singles instructions for x type instructions.  */
#define PSWM WS + 1
  /* The BO16 field in a BD8 form instruction.  */
#define BO16 PSWM
  {  0x1, 10, 0, 0, 0 },

  /* IDX bits for quantization in the pair singles instructions.  */
#define PSQ PSWM + 1
  {  0x7, 12, 0, 0, 0 },

  /* IDX bits for quantization in the pair singles x-type instructions.  */
#define PSQM PSQ + 1
  {  0x7, 7, 0, 0, 0 },

  /* Smaller D field for quantization in the pair singles instructions.  */
#define PSD PSQM + 1
  {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The L field in an mtmsrd or A form instruction or R or W in an X form.  */
#define A_L PSD + 1
#define W A_L
#define X_R A_L
  { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The RMC or CY field in a Z23 form instruction.  */
#define RMC A_L + 1
#define CY RMC
  { 0x3, 9, NULL, NULL, 0 },

#define R RMC + 1
  { 0x1, 16, NULL, NULL, 0 },

#define RIC R + 1
  { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },

#define PRS RIC + 1
  { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },

#define SP PRS + 1
  { 0x3, 19, NULL, NULL, 0 },

#define S SP + 1
  { 0x1, 20, NULL, NULL, 0 },

  /* The S field in a XL form instruction.  */
#define SXL S + 1
  { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
  /* If the SXL operand is ommitted, use the value 1.  */
  { -1, 1, NULL, NULL, 0},

  /* SH field starting at bit position 16.  */
#define SH16 SXL + 2
  /* The DCM and DGM fields in a Z form instruction.  */
#define DCM SH16
#define DGM DCM
  { 0x3f, 10, NULL, NULL, 0 },

  /* The EH field in larx instruction.  */
#define EH SH16 + 1
  { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The L field in an mtfsf or XFL form instruction.  */
  /* The A field in a HTM X form instruction.  */
#define XFL_L EH + 1
#define HTM_A XFL_L
  { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},

  /* Xilinx APU related masks and macros */
#define FCRT XFL_L + 1
#define FCRT_MASK (0x1f << 21)
  { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },

  /* Xilinx FSL related masks and macros */
#define FSL FCRT + 1
#define FSL_MASK (0x1f << 11)
  { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },

  /* Xilinx UDI related masks and macros */
#define URT FSL + 1
  { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },

#define URA URT + 1
  { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },

#define URB URA + 1
  { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },

#define URC URB + 1
  { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },

  /* The VLESIMM field in a D form instruction.  */
#define VLESIMM URC + 1
  { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
    PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The VLENSIMM field in a D form instruction.  */
#define VLENSIMM VLESIMM + 1
  { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
    PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The VLEUIMM field in a D form instruction.  */
#define VLEUIMM VLENSIMM + 1
  { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },

  /* The VLEUIMML field in a D form instruction.  */
#define VLEUIMML VLEUIMM + 1
  { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },

  /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
#define XS6 VLEUIMML + 1
#define XT6 XS6
  { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },

  /* The XT and XS fields in an DQ form VSX instruction.  This is split.  */
#define XSQ6 XT6 + 1
#define XTQ6 XSQ6
  { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },

  /* The XA field in an XX3 form instruction.  This is split.  */
#define XA6 XTQ6 + 1
  { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },

  /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
#define XB6 XA6 + 1
  { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },

  /* The XB field in an XX3 form instruction when it must be the same as
     the XA field in the instruction.  This is used in extended mnemonics
     like xvmovdp.  This is split.  */
#define XB6S XB6 + 1
  { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },

  /* The XC field in an XX4 form instruction.  This is split.  */
#define XC6 XB6S + 1
  { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },

  /* The DM or SHW field in an XX3 form instruction.  */
#define DM XC6 + 1
#define SHW DM
  { 0x3, 8, NULL, NULL, 0 },

  /* The DM field in an extended mnemonic XX3 form instruction.  */
#define DMEX DM + 1
  { 0x3, 8, insert_dm, extract_dm, 0 },

  /* The UIM field in an XX2 form instruction.  */
#define UIM DMEX + 1
  /* The 2-bit UIMM field in a VX form instruction.  */
#define UIMM2 UIM
  /* The 2-bit L field in a darn instruction.  */
#define LRAND UIM
  { 0x3, 16, NULL, NULL, 0 },

#define ERAT_T UIM + 1
  { 0x7, 21, NULL, NULL, 0 },

#define IH ERAT_T + 1
  { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The 8-bit IMM8 field in a XX1 form instruction.  */
#define IMM8 IH + 1
  { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
};

const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
                                           / sizeof (powerpc_operands[0]));

/* The functions used to insert and extract complicated operands.  */

/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs.  */

static unsigned long
insert_arx (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  if (value >= 8 && value < 24)
    return insn | ((value - 8) & 0xf);
  else
    {
      *errmsg = _("invalid register");
      return 0;
    }
}

static long
extract_arx (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return (insn & 0xf) + 8;
}

static unsigned long
insert_ary (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  if (value >= 8 && value < 24)
    return insn | (((value - 8) & 0xf) << 4);
  else
    {
      *errmsg = _("invalid register");
      return 0;
    }
}

static long
extract_ary (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 4) & 0xf) + 8;
}

static unsigned long
insert_rx (unsigned long insn,
           long value,
           ppc_cpu_t dialect ATTRIBUTE_UNUSED,
           const char **errmsg)
{
  if (value >= 0 && value < 8)
    return insn | value;
  else if (value >= 24 && value <= 31)
    return insn | (value - 16);
  else
    {
      *errmsg = _("invalid register");
      return 0;
    }
}

static long
extract_rx (unsigned long insn,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            int *invalid ATTRIBUTE_UNUSED)
{
  int value = insn & 0xf;
  if (value >= 0 && value < 8)
    return value;
  else
    return value + 16;
}

static unsigned long
insert_ry (unsigned long insn,
           long value,
           ppc_cpu_t dialect ATTRIBUTE_UNUSED,
           const char **errmsg)
{
  if (value >= 0 && value < 8)
    return insn | (value << 4);
  else if (value >= 24 && value <= 31)
    return insn | ((value - 16) << 4);
  else
    {
      *errmsg = _("invalid register");
      return 0;
    }
}

static long
extract_ry (unsigned long insn,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            int *invalid ATTRIBUTE_UNUSED)
{
  int value = (insn >> 4) & 0xf;
  if (value >= 0 && value < 8)
    return value;
  else
    return value + 16;
}

/* The BA field in an XL form instruction when it must be the same as
   the BT field in the same instruction.  This operand is marked FAKE.
   The insertion function just copies the BT field into the BA field,
   and the extraction function just checks that the fields are the
   same.  */

static unsigned long
insert_bat (unsigned long insn,
            long value ATTRIBUTE_UNUSED,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((insn >> 21) & 0x1f) << 16);
}

static long
extract_bat (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
    *invalid = 1;
  return 0;
}

/* The BB field in an XL form instruction when it must be the same as
   the BA field in the same instruction.  This operand is marked FAKE.
   The insertion function just copies the BA field into the BB field,
   and the extraction function just checks that the fields are the
   same.  */

static unsigned long
insert_bba (unsigned long insn,
            long value ATTRIBUTE_UNUSED,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((insn >> 16) & 0x1f) << 11);
}

static long
extract_bba (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
    *invalid = 1;
  return 0;
}

/* The BD field in a B form instruction when the - modifier is used.
   This modifier means that the branch is not expected to be taken.
   For chips built to versions of the architecture prior to version 2
   (ie. not Power4 compatible), we set the y bit of the BO field to 1
   if the offset is negative.  When extracting, we require that the y
   bit be 1 and that the offset be positive, since if the y bit is 0
   we just want to print the normal form of the instruction.
   Power4 compatible targets use two bits, "a", and "t", instead of
   the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
   "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
   in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
   for branch on CTR.  We only handle the taken/not-taken hint here.
   Note that we don't relax the conditions tested here when
   disassembling with -Many because insns using extract_bdm and
   extract_bdp always occur in pairs.  One or the other will always
   be valid.  */

#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)

static unsigned long
insert_bdm (unsigned long insn,
            long value,
            ppc_cpu_t dialect,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  if ((dialect & ISA_V2) == 0)
    {
      if ((value & 0x8000) != 0)
        insn |= 1 << 21;
    }
  else
    {
      if ((insn & (0x14 << 21)) == (0x04 << 21))
        insn |= 0x02 << 21;
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
        insn |= 0x08 << 21;
    }
  return insn | (value & 0xfffc);
}

static long
extract_bdm (unsigned long insn,
             ppc_cpu_t dialect,
             int *invalid)
{
  if ((dialect & ISA_V2) == 0)
    {
      if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
        *invalid = 1;
    }
  else
    {
      if ((insn & (0x17 << 21)) != (0x06 << 21)
          && (insn & (0x1d << 21)) != (0x18 << 21))
        *invalid = 1;
    }

  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}

/* The BD field in a B form instruction when the + modifier is used.
   This is like BDM, above, except that the branch is expected to be
   taken.  */

static unsigned long
insert_bdp (unsigned long insn,
            long value,
            ppc_cpu_t dialect,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  if ((dialect & ISA_V2) == 0)
    {
      if ((value & 0x8000) == 0)
        insn |= 1 << 21;
    }
  else
    {
      if ((insn & (0x14 << 21)) == (0x04 << 21))
        insn |= 0x03 << 21;
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
        insn |= 0x09 << 21;
    }
  return insn | (value & 0xfffc);
}

static long
extract_bdp (unsigned long insn,
             ppc_cpu_t dialect,
             int *invalid)
{
  if ((dialect & ISA_V2) == 0)
    {
      if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
        *invalid = 1;
    }
  else
    {
      if ((insn & (0x17 << 21)) != (0x07 << 21)
          && (insn & (0x1d << 21)) != (0x19 << 21))
        *invalid = 1;
    }

  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}

static inline int
valid_bo_pre_v2 (long value)
{
  /* Certain encodings have bits that are required to be zero.
     These are (z must be zero, y may be anything):
         0000y
         0001y
         001zy
         0100y
         0101y
         011zy
         1z00y
         1z01y
         1z1zz
  */
  if ((value & 0x14) == 0)
    return 1;
  else if ((value & 0x14) == 0x4)
    return (value & 0x2) == 0;
  else if ((value & 0x14) == 0x10)
    return (value & 0x8) == 0;
  else
    return value == 0x14;
}

static inline int
valid_bo_post_v2 (long value)
{
  /* Certain encodings have bits that are required to be zero.
     These are (z must be zero, a & t may be anything):
         0000z
         0001z
         001at
         0100z
         0101z
         011at
         1a00t
         1a01t
         1z1zz
  */
  if ((value & 0x14) == 0)
    return (value & 0x1) == 0;
  else if ((value & 0x14) == 0x14)
    return value == 0x14;
  else
    return 1;
}

/* Check for legal values of a BO field.  */

static int
valid_bo (long value, ppc_cpu_t dialect, int extract)
{
  int valid_y = valid_bo_pre_v2 (value);
  int valid_at = valid_bo_post_v2 (value);

  /* When disassembling with -Many, accept either encoding on the
     second pass through opcodes.  */
  if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
    return valid_y || valid_at;
  if ((dialect & ISA_V2) == 0)
    return valid_y;
  else
    return valid_at;
}

/* The BO field in a B form instruction.  Warn about attempts to set
   the field to an illegal value.  */

static unsigned long
insert_bo (unsigned long insn,
           long value,
           ppc_cpu_t dialect,
           const char **errmsg)
{
  if (!valid_bo (value, dialect, 0))
    *errmsg = _("invalid conditional option");
  else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
    *errmsg = _("invalid counter access");
  return insn | ((value & 0x1f) << 21);
}

static long
extract_bo (unsigned long insn,
            ppc_cpu_t dialect,
            int *invalid)
{
  long value;

  value = (insn >> 21) & 0x1f;
  if (!valid_bo (value, dialect, 1))
    *invalid = 1;
  return value;
}

/* The BO field in a B form instruction when the + or - modifier is
   used.  This is like the BO field, but it must be even.  When
   extracting it, we force it to be even.  */

static unsigned long
insert_boe (unsigned long insn,
            long value,
            ppc_cpu_t dialect,
            const char **errmsg)
{
  if (!valid_bo (value, dialect, 0))
    *errmsg = _("invalid conditional option");
  else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
    *errmsg = _("invalid counter access");
  else if ((value & 1) != 0)
    *errmsg = _("attempt to set y bit when using + or - modifier");

  return insn | ((value & 0x1f) << 21);
}

static long
extract_boe (unsigned long insn,
             ppc_cpu_t dialect,
             int *invalid)
{
  long value;

  value = (insn >> 21) & 0x1f;
  if (!valid_bo (value, dialect, 1))
    *invalid = 1;
  return value & 0x1e;
}

/* The DCMX field in a X form instruction when the field is split
   into separate DC, DM and DX fields.  */

static unsigned long
insert_dcmxs (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
}

static long
extract_dcmxs (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
}

/* The D field in a DX form instruction when the field is split
   into separate D0, D1 and D2 fields.  */

static unsigned long
insert_dxd (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
}

static long
extract_dxd (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
  return (dxd ^ 0x8000) - 0x8000;
}

static unsigned long
insert_dxdn (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insert_dxd (insn, -value, dialect, errmsg);
}

static long
extract_dxdn (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return -extract_dxd (insn, dialect, invalid);
}

/* FXM mask in mfcr and mtcrf instructions.  */

static unsigned long
insert_fxm (unsigned long insn,
            long value,
            ppc_cpu_t dialect,
            const char **errmsg)
{
  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
     one bit of the mask field is set.  */
  if ((insn & (1 << 20)) != 0)
    {
      if (value == 0 || (value & -value) != value)
        {
          *errmsg = _("invalid mask field");
          value = 0;
        }
    }

  /* If only one bit of the FXM field is set, we can use the new form
     of the instruction, which is faster.  Unlike the Power4 branch hint
     encoding, this is not backward compatible.  Do not generate the
     new form unless -mpower4 has been given, or -many and the two
     operand form of mfcr was used.  */
  else if (value > 0
           && (value & -value) == value
           && ((dialect & PPC_OPCODE_POWER4) != 0
               || ((dialect & PPC_OPCODE_ANY) != 0
                   && (insn & (0x3ff << 1)) == 19 << 1)))
    insn |= 1 << 20;

  /* Any other value on mfcr is an error.  */
  else if ((insn & (0x3ff << 1)) == 19 << 1)
    {
      /* A value of -1 means we used the one operand form of
         mfcr which is valid.  */
      if (value != -1)
        *errmsg = _("invalid mfcr mask");
      value = 0;
    }

  return insn | ((value & 0xff) << 12);
}

static long
extract_fxm (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  long mask = (insn >> 12) & 0xff;

  /* Is this a Power4 insn?  */
  if ((insn & (1 << 20)) != 0)
    {
      /* Exactly one bit of MASK should be set.  */
      if (mask == 0 || (mask & -mask) != mask)
        *invalid = 1;
    }

  /* Check that non-power4 form of mfcr has a zero MASK.  */
  else if ((insn & (0x3ff << 1)) == 19 << 1)
    {
      if (mask != 0)
        *invalid = 1;
      else
        mask = -1;
    }

  return mask;
}

static unsigned long
insert_li20 (unsigned long insn,
             long value,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
}

static long
extract_li20 (unsigned long insn,
              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
              int *invalid ATTRIBUTE_UNUSED)
{
  long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;

  return ext
         | (((insn >> 11) & 0xf) << 16)
         | (((insn >> 17) & 0xf) << 12)
         | (((insn >> 16) & 0x1) << 11)
         | (insn & 0x7ff);
}

/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
   For SYNC, some L values are reserved:
     * Value 3 is reserved on newer server cpus.
     * Values 2 and 3 are reserved on all other cpus.  */

static unsigned long
insert_ls (unsigned long insn,
           long value,
           ppc_cpu_t dialect,
           const char **errmsg)
{
  /* For SYNC, some L values are illegal.  */
  if (((insn >> 1) & 0x3ff) == 598)
    {
      long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
      if (value > max_lvalue)
        {
          *errmsg = _("illegal L operand value");
          return insn;
        }
    }

  return insn | ((value & 0x3) << 21);
}

/* The 4-bit E field in a sync instruction that accepts 2 operands.
   If ESYNC is non-zero, then the L field must be either 0 or 1 and
   the complement of ESYNC-bit2.  */

static unsigned long
insert_esync (unsigned long insn,
              long value,
              ppc_cpu_t dialect,
              const char **errmsg)
{
  unsigned long ls = (insn >> 21) & 0x03;

  if (value == 0)
    {
      if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
          || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
        *errmsg = _("illegal L operand value");
      return insn;
    }

  if ((ls & ~0x1)
      || (((value >> 1) & 0x1) ^ ls) == 0)
        *errmsg = _("incompatible L operand value");

  return insn | ((value & 0xf) << 16);
}

/* The MB and ME fields in an M form instruction expressed as a single
   operand which is itself a bitmask.  The extraction function always
   marks it as invalid, since we never want to recognize an
   instruction which uses a field of this type.  */

static unsigned long
insert_mbe (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  unsigned long uval, mask;
  int mb, me, mx, count, last;

  uval = value;

  if (uval == 0)
    {
      *errmsg = _("illegal bitmask");
      return insn;
    }

  mb = 0;
  me = 32;
  if ((uval & 1) != 0)
    last = 1;
  else
    last = 0;
  count = 0;

  /* mb: location of last 0->1 transition */
  /* me: location of last 1->0 transition */
  /* count: # transitions */

  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
    {
      if ((uval & mask) && !last)
        {
          ++count;
          mb = mx;
          last = 1;
        }
      else if (!(uval & mask) && last)
        {
          ++count;
          me = mx;
          last = 0;
        }
    }
  if (me == 0)
    me = 32;

  if (count != 2 && (count != 0 || ! last))
    *errmsg = _("illegal bitmask");

  return insn | (mb << 6) | ((me - 1) << 1);
}

static long
extract_mbe (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  long ret;
  int mb, me;
  int i;

  *invalid = 1;

  mb = (insn >> 6) & 0x1f;
  me = (insn >> 1) & 0x1f;
  if (mb < me + 1)
    {
      ret = 0;
      for (i = mb; i <= me; i++)
        ret |= 1L << (31 - i);
    }
  else if (mb == me + 1)
    ret = ~0;
  else /* (mb > me + 1) */
    {
      ret = ~0;
      for (i = me + 1; i < mb; i++)
        ret &= ~(1L << (31 - i));
    }
  return ret;
}

/* The MB or ME field in an MD or MDS form instruction.  The high bit
   is wrapped to the low end.  */

static unsigned long
insert_mb6 (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 6) | (value & 0x20);
}

static long
extract_mb6 (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 6) & 0x1f) | (insn & 0x20);
}

/* The NB field in an X form instruction.  The value 32 is stored as
   0.  */

static long
extract_nb (unsigned long insn,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            int *invalid ATTRIBUTE_UNUSED)
{
  long ret;

  ret = (insn >> 11) & 0x1f;
  if (ret == 0)
    ret = 32;
  return ret;
}

/* The NB field in an lswi instruction, which has special value
   restrictions.  The value 32 is stored as 0.  */

static unsigned long
insert_nbi (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  long rtvalue = (insn & RT_MASK) >> 21;
  long ravalue = (insn & RA_MASK) >> 16;

  if (value == 0)
    value = 32;
  if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
                                                     : ravalue))
    *errmsg = _("address register in load range");
  return insn | ((value & 0x1f) << 11);
}

/* The NSI field in a D form instruction.  This is the same as the SI
   field, only negated.  The extraction function always marks it as
   invalid, since we never want to recognize an instruction which uses
   a field of this type.  */

static unsigned long
insert_nsi (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (-value & 0xffff);
}

static long
extract_nsi (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  *invalid = 1;
  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
}

/* The RA field in a D or X form instruction which is an updating
   load, which means that the RA field may not be zero and may not
   equal the RT field.  */

static unsigned long
insert_ral (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  if (value == 0
      || (unsigned long) value == ((insn >> 21) & 0x1f))
    *errmsg = "invalid register operand when updating";
  return insn | ((value & 0x1f) << 16);
}

/* The RA field in an lmw instruction, which has special value
   restrictions.  */

static unsigned long
insert_ram (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  if ((unsigned long) value >= ((insn >> 21) & 0x1f))
    *errmsg = _("index register in load range");
  return insn | ((value & 0x1f) << 16);
}

/* The RA field in the DQ form lq or an lswx instruction, which have special
   value restrictions.  */

static unsigned long
insert_raq (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  long rtvalue = (insn & RT_MASK) >> 21;

  if (value == rtvalue)
    *errmsg = _("source and target register operands must be different");
  return insn | ((value & 0x1f) << 16);
}

/* The RA field in a D or X form instruction which is an updating
   store or an updating floating point load, which means that the RA
   field may not be zero.  */

static unsigned long
insert_ras (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  if (value == 0)
    *errmsg = _("invalid register operand when updating");
  return insn | ((value & 0x1f) << 16);
}

/* The RB field in an X form instruction when it must be the same as
   the RS field in the instruction.  This is used for extended
   mnemonics like mr.  This operand is marked FAKE.  The insertion
   function just copies the BT field into the BA field, and the
   extraction function just checks that the fields are the same.  */

static unsigned long
insert_rbs (unsigned long insn,
            long value ATTRIBUTE_UNUSED,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((insn >> 21) & 0x1f) << 11);
}

static long
extract_rbs (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
    *invalid = 1;
  return 0;
}

/* The RB field in an lswx instruction, which has special value
   restrictions.  */

static unsigned long
insert_rbx (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  long rtvalue = (insn & RT_MASK) >> 21;

  if (value == rtvalue)
    *errmsg = _("source and target register operands must be different");
  return insn | ((value & 0x1f) << 11);
}

/* The SCI8 field is made up of SCL and {U,N}I8 fields.  */
static unsigned long
insert_sci8 (unsigned long insn,
             long value,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             const char **errmsg)
{
  unsigned int fill_scale = 0;
  unsigned long ui8 = value;

  if ((ui8 & 0xffffff00) == 0)
    ;
  else if ((ui8 & 0xffffff00) == 0xffffff00)
    fill_scale = 0x400;
  else if ((ui8 & 0xffff00ff) == 0)
    {
      fill_scale = 1 << 8;
      ui8 >>= 8;
    }
  else if ((ui8 & 0xffff00ff) == 0xffff00ff)
    {
      fill_scale = 0x400 | (1 << 8);
      ui8 >>= 8;
    }
  else if ((ui8 & 0xff00ffff) == 0)
    {
      fill_scale = 2 << 8;
      ui8 >>= 16;
    }
  else if ((ui8 & 0xff00ffff) == 0xff00ffff)
    {
      fill_scale = 0x400 | (2 << 8);
      ui8 >>= 16;
    }
  else if ((ui8 & 0x00ffffff) == 0)
    {
      fill_scale = 3 << 8;
      ui8 >>= 24;
    }
  else if ((ui8 & 0x00ffffff) == 0x00ffffff)
    {
      fill_scale = 0x400 | (3 << 8);
      ui8 >>= 24;
    }
  else
    {
      *errmsg = _("illegal immediate value");
      ui8 = 0;
    }

  return insn | fill_scale | (ui8 & 0xff);
}

static long
extract_sci8 (unsigned long insn,
              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
              int *invalid ATTRIBUTE_UNUSED)
{
  int fill = insn & 0x400;
  int scale_factor = (insn & 0x300) >> 5;
  long value = (insn & 0xff) << scale_factor;

  if (fill != 0)
    value |= ~((long) 0xff << scale_factor);
  return value;
}

static unsigned long
insert_sci8n (unsigned long insn,
              long value,
              ppc_cpu_t dialect,
              const char **errmsg)
{
  return insert_sci8 (insn, -value, dialect, errmsg);
}

static long
extract_sci8n (unsigned long insn,
               ppc_cpu_t dialect,
               int *invalid)
{
  return -extract_sci8 (insn, dialect, invalid);
}

static unsigned long
insert_sd4h (unsigned long insn,
             long value,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1e) << 7);
}

static long
extract_sd4h (unsigned long insn,
              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
              int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 8) & 0xf) << 1;
}

static unsigned long
insert_sd4w (unsigned long insn,
             long value,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x3c) << 6);
}

static long
extract_sd4w (unsigned long insn,
              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
              int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 8) & 0xf) << 2;
}

static unsigned long
insert_oimm (unsigned long insn,
             long value,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((value - 1) & 0x1f) << 4);
}

static long
extract_oimm (unsigned long insn,
              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
              int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 4) & 0x1f) + 1;
}

/* The SH field in an MD form instruction.  This is split.  */

static unsigned long
insert_sh6 (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  /* SH6 operand in the rldixor instructions.  */
  if (PPC_OP (insn) == 4)
    return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
  else
    return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
}

static long
extract_sh6 (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  /* SH6 operand in the rldixor instructions.  */
  if (PPC_OP (insn) == 4)
    return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
  else
    return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
}

/* The SPR field in an XFX form instruction.  This is flipped--the
   lower 5 bits are stored in the upper 5 and vice- versa.  */

static unsigned long
insert_spr (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
}

static long
extract_spr (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,

             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
}

/* Some dialects have 8 SPRG registers instead of the standard 4.  */
#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)

static unsigned long
insert_sprg (unsigned long insn,
             long value,
             ppc_cpu_t dialect,
             const char **errmsg)
{
  if (value > 7
      || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
    *errmsg = _("invalid sprg number");

  /* If this is mfsprg4..7 then use spr 260..263 which can be read in
     user mode.  Anything else must use spr 272..279.  */
  if (value <= 3 || (insn & 0x100) != 0)
    value |= 0x10;

  return insn | ((value & 0x17) << 16);
}

static long
extract_sprg (unsigned long insn,
              ppc_cpu_t dialect,
              int *invalid)
{
  unsigned long val = (insn >> 16) & 0x1f;

  /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
     If not BOOKE, 405 or VLE, then both use only 272..275.  */
  if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
      || (val - 0x10 > 7 && (insn & 0x100) != 0)
      || val <= 3
      || (val & 8) != 0)
    *invalid = 1;
  return val & 7;
}

/* The TBR field in an XFX instruction.  This is just like SPR, but it
   is optional.  */

static unsigned long
insert_tbr (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  if (value != 268 && value != 269)
    *errmsg = _("invalid tbr number");
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
}

static long
extract_tbr (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  long ret;

  ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
  if (ret != 268 && ret != 269)
    *invalid = 1;
  return ret;
}

/* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */

static unsigned long
insert_xt6 (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
}

static long
extract_xt6 (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
}

/* The XT and XS fields in an DQ form VSX instruction.  This is split.  */
static unsigned long
insert_xtq6 (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
}

static long
extract_xtq6 (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
}

/* The XA field in an XX3 form instruction.  This is split.  */

static unsigned long
insert_xa6 (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
}

static long
extract_xa6 (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
}

/* The XB field in an XX3 form instruction.  This is split.  */

static unsigned long
insert_xb6 (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
}

static long
extract_xb6 (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
}

/* The XB field in an XX3 form instruction when it must be the same as
   the XA field in the instruction.  This is used for extended
   mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
   function just copies the XA field into the XB field, and the
   extraction function just checks that the fields are the same.  */

static unsigned long
insert_xb6s (unsigned long insn,
            long value ATTRIBUTE_UNUSED,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
}

static long
extract_xb6s (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
      || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
    *invalid = 1;
  return 0;
}

/* The XC field in an XX4 form instruction.  This is split.  */

static unsigned long
insert_xc6 (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
}

static long
extract_xc6 (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
}

static unsigned long
insert_dm (unsigned long insn,
           long value,
           ppc_cpu_t dialect ATTRIBUTE_UNUSED,
           const char **errmsg)
{
  if (value != 0 && value != 1)
    *errmsg = _("invalid constant");
  return insn | (((value) ? 3 : 0) << 8);
}

static long
extract_dm (unsigned long insn,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            int *invalid)
{
  long value;

  value = (insn >> 8) & 3;
  if (value != 0 && value != 3)
    *invalid = 1;
  return (value) ? 1 : 0;
}

/* The VLESIMM field in an I16A form instruction.  This is split.  */

static unsigned long
insert_vlesi (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
}

static long
extract_vlesi (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
  value = (value ^ 0x8000) - 0x8000;
  return value;
}

static unsigned long
insert_vlensi (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  value = -value;
  return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
}
static long
extract_vlensi (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
  value = (value ^ 0x8000) - 0x8000;
  /* Don't use for disassembly.  */
  *invalid = 1;
  return -value;
}

/* The VLEUIMM field in an I16A form instruction.  This is split.  */

static unsigned long
insert_vleui (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
}

static long
extract_vleui (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
}

/* The VLEUIMML field in an I16L form instruction.  This is split.  */

static unsigned long
insert_vleil (unsigned long insn,
            long value,
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
}

static long
extract_vleil (unsigned long insn,
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
}


/* Macros used to form opcodes.  */

/* The main opcode.  */
#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
#define OP_MASK OP (0x3f)

/* The main opcode combined with a trap code in the TO field of a D
   form instruction.  Used for extended mnemonics for the trap
   instructions.  */
#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
#define OPTO_MASK (OP_MASK | TO_MASK)

/* The main opcode combined with a comparison size bit in the L field
   of a D form or X form instruction.  Used for extended mnemonics for
   the comparison instructions.  */
#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
#define OPL_MASK OPL (0x3f,1)

/* The main opcode combined with an update code in D form instruction.
   Used for extended mnemonics for VLE memory instructions.  */
#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
#define OPVUP_MASK OPVUP (0x3f,  0xff)

/* The main opcode combined with an update code and the RT fields specified in
   D form instruction.  Used for VLE volatile context save/restore
   instructions.  */
#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)

/* An A form instruction.  */
#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
#define A_MASK A (0x3f, 0x1f, 1)

/* An A_MASK with the FRB field fixed.  */
#define AFRB_MASK (A_MASK | FRB_MASK)

/* An A_MASK with the FRC field fixed.  */
#define AFRC_MASK (A_MASK | FRC_MASK)

/* An A_MASK with the FRA and FRC fields fixed.  */
#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)

/* An AFRAFRC_MASK, but with L bit clear.  */
#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))

/* A B form instruction.  */
#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
#define B_MASK B (0x3f, 1, 1)

/* A BD8 form instruction.  This is a 16-bit instruction.  */
#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
#define BD8_MASK BD8 (0x3f, 1, 1)

/* Another BD8 form instruction.  This is a 16-bit instruction.  */
#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
#define BD8IO_MASK BD8IO (0x1f)

/* A BD8 form instruction for simplified mnemonics.  */
#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
/* A mask that excludes BO32 and BI32.  */
#define EBD8IO1_MASK 0xf800
/* A mask that includes BO32 and excludes BI32.  */
#define EBD8IO2_MASK 0xfc00
/* A mask that include BO32 AND BI32.  */
#define EBD8IO3_MASK 0xff00

/* A BD15 form instruction.  */
#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
#define BD15_MASK BD15 (0x3f, 0xf, 1)

/* A BD15 form instruction for extended conditional branch mnemonics.  */
#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
#define EBD15_MASK 0xfff00001

/* A BD15 form instruction for extended conditional branch mnemonics with BI.  */
#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
                                    | (((aa) & 0xf) << 22) \
                                    | (((bo) & 0x3) << 20) \
                                    | (((bi) & 0x3) << 16) \
                                    | ((lk) & 1)
#define EBD15BI_MASK  0xfff30001

/* A BD24 form instruction.  */
#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
#define BD24_MASK BD24 (0x3f, 1, 1)

/* A B form instruction setting the BO field.  */
#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)

/* A BBO_MASK with the y bit of the BO field removed.  This permits
   matching a conditional branch regardless of the setting of the y
   bit.  Similarly for the 'at' bits used for power4 branch hints.  */
#define Y_MASK   (((unsigned long) 1) << 21)
#define AT1_MASK (((unsigned long) 3) << 21)
#define AT2_MASK (((unsigned long) 9) << 21)
#define BBOY_MASK  (BBO_MASK &~ Y_MASK)
#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)

/* A B form instruction setting the BO field and the condition bits of
   the BI field.  */
#define BBOCB(op, bo, cb, aa, lk) \
  (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)

/* A BBOCB_MASK with the y bit of the BO field removed.  */
#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)

/* A BBOYCB_MASK in which the BI field is fixed.  */
#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)

/* A VLE C form instruction.  */
#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
#define C_LK_MASK C_LK(0x7fff, 1)
#define C(x) ((((unsigned long)(x)) & 0xffff))
#define C_MASK C(0xffff)

/* An Context form instruction.  */
#define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
#define CTX_MASK CTX(0x3f, 0x7)

/* A User Context form instruction.  */
#define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define UCTX_MASK UCTX(0x3f, 0x1f)

/* The main opcode mask with the RA field clear.  */
#define DRA_MASK (OP_MASK | RA_MASK)

/* A DQ form VSX instruction.  */
#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
#define DQX_MASK DQX (0x3f, 7)

/* A DS form instruction.  */
#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
#define DS_MASK DSO (0x3f, 3)

/* An DX form instruction.  */
#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
#define DX_MASK DX (0x3f, 0x1f)

/* An EVSEL form instruction.  */
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
#define EVSEL_MASK EVSEL(0x3f, 0xff)

/* An IA16 form instruction.  */
#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
#define IA16_MASK IA16(0x3f, 0x1f)

/* An I16A form instruction.  */
#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
#define I16A_MASK I16A(0x3f, 0x1f)

/* An I16L form instruction.  */
#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
#define I16L_MASK I16L(0x3f, 0x1f)

/* An IM7 form instruction.  */
#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
#define IM7_MASK IM7(0x1f)

/* An M form instruction.  */
#define M(op, rc) (OP (op) | ((rc) & 1))
#define M_MASK M (0x3f, 1)

/* An LI20 form instruction.  */
#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
#define LI20_MASK LI20(0x3f, 0x1)

/* An M form instruction with the ME field specified.  */
#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))

/* An M_MASK with the MB and ME fields fixed.  */
#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)

/* An M_MASK with the SH and ME fields fixed.  */
#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)

/* An MD form instruction.  */
#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
#define MD_MASK MD (0x3f, 0x7, 1)

/* An MD_MASK with the MB field fixed.  */
#define MDMB_MASK (MD_MASK | MB6_MASK)

/* An MD_MASK with the SH field fixed.  */
#define MDSH_MASK (MD_MASK | SH6_MASK)

/* An MDS form instruction.  */
#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
#define MDS_MASK MDS (0x3f, 0xf, 1)

/* An MDS_MASK with the MB field fixed.  */
#define MDSMB_MASK (MDS_MASK | MB6_MASK)

/* An SC form instruction.  */
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)

/* An SCI8 form instruction.  */
#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
#define SCI8_MASK SCI8(0x3f, 0x1f)

/* An SCI8 form instruction.  */
#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)

/* An SD4 form instruction.  This is a 16-bit instruction.  */
#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
#define SD4_MASK SD4(0xf)

/* An SE_IM5 form instruction.  This is a 16-bit instruction.  */
#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
#define SE_IM5_MASK SE_IM5(0x3f, 1)

/* An SE_R form instruction.  This is a 16-bit instruction.  */
#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
#define SE_R_MASK SE_R(0x3f, 0x3f)

/* An SE_RR form instruction.  This is a 16-bit instruction.  */
#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
#define SE_RR_MASK SE_RR(0x3f, 3)

/* A VX form instruction.  */
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))

/* The mask for an VX form instruction.  */
#define VX_MASK VX(0x3f, 0x7ff)

/* A VX_MASK with the VA field fixed.  */
#define VXVA_MASK (VX_MASK | (0x1f << 16))

/* A VX_MASK with the VB field fixed.  */
#define VXVB_MASK (VX_MASK | (0x1f << 11))

/* A VX_MASK with the VA and VB fields fixed.  */
#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))

/* A VX_MASK with the VD and VA fields fixed.  */
#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))

/* A VX_MASK with a UIMM4 field.  */
#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))

/* A VX_MASK with a UIMM3 field.  */
#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))

/* A VX_MASK with a UIMM2 field.  */
#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))

/* A VX_MASK with a PS field.  */
#define VXPS_MASK (VX_MASK & ~(0x1 << 9))

/* A VX_MASK with the VA field fixed with a PS field.  */
#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))

/* A VA form instruction.  */
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))

/* The mask for an VA form instruction.  */
#define VXA_MASK VXA(0x3f, 0x3f)

/* A VXA_MASK with a SHB field.  */
#define VXASHB_MASK (VXA_MASK | (1 << 10))

/* A VXR form instruction.  */
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))

/* The mask for a VXR form instruction.  */
#define VXR_MASK VXR(0x3f, 0x3ff, 1)

/* A VX form instruction with a VA tertiary opcode.  */
#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))

#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
#define VXASH_MASK VXASH (0x3f, 0x1f)

/* An X form instruction.  */
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))

/* A X form instruction for Quad-Precision FP Instructions.  */
#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))

/* An EX form instruction.  */
#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))

/* The mask for an EX form instruction.  */
#define EX_MASK EX (0x3f, 0x7ff)

/* An XX2 form instruction.  */
#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))

/* A XX2 form instruction with the VA bits specified.  */
#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))

/* An XX3 form instruction.  */
#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))

/* An XX3 form instruction with the RC bit specified.  */
#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))

/* An XX4 form instruction.  */
#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))

/* A Z form instruction.  */
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))

/* An X form instruction with the RC bit specified.  */
#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))

/* A X form instruction for Quad-Precision FP Instructions with RC bit.  */
#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))

/* An X form instruction with the RA bits specified as two ops.  */
#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)

/* A Z form instruction with the RC bit specified.  */
#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))

/* The mask for an X form instruction.  */
#define X_MASK XRC (0x3f, 0x3ff, 1)

/* The mask for an X form instruction with the BF bits specified.  */
#define XBF_MASK (X_MASK | (3 << 21))

/* An X form wait instruction with everything filled in except the WC field.  */
#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)

/* The mask for an XX1 form instruction.  */
#define XX1_MASK X (0x3f, 0x3ff)

/* An XX1_MASK with the RB field fixed.  */
#define XX1RB_MASK (XX1_MASK | RB_MASK)

/* The mask for an XX2 form instruction.  */
#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))

/* The mask for an XX2 form instruction with the UIM bits specified.  */
#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))

/* The mask for an XX2 form instruction with the 4 UIM bits specified.  */
#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))

/* The mask for an XX2 form instruction with the BF bits specified.  */
#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))

/* The mask for an XX2 form instruction with the BF and DCMX bits specified.  */
#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)

/* The mask for an XX2 form instruction with a split DCMX bits specified.  */
#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)

/* The mask for an XX3 form instruction.  */
#define XX3_MASK XX3 (0x3f, 0xff)

/* The mask for an XX3 form instruction with the BF bits specified.  */
#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))

/* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
#define XX3SHW_MASK XX3DM_MASK

/* The mask for an XX4 form instruction.  */
#define XX4_MASK XX4 (0x3f, 0x3)

/* An X form wait instruction with everything filled in except the WC field.  */
#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)

/* The mask for an XMMF form instruction.  */
#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))

/* The mask for a Z form instruction.  */
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
#define Z2_MASK ZRC (0x3f, 0xff, 1)

/* An X_MASK with the RA/VA field fixed.  */
#define XRA_MASK (X_MASK | RA_MASK)
#define XVA_MASK XRA_MASK

/* An XRA_MASK with the A_L/W field clear.  */
#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
#define XRLA_MASK XWRA_MASK

/* An X_MASK with the RB field fixed.  */
#define XRB_MASK (X_MASK | RB_MASK)

/* An X_MASK with the RT field fixed.  */
#define XRT_MASK (X_MASK | RT_MASK)

/* An XRT_MASK mask with the L bits clear.  */
#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))

/* An X_MASK with the RA and RB fields fixed.  */
#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)

/* An XBF_MASK with the RA and RB fields fixed.  */
#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)

/* An XRARB_MASK, but with the L bit clear.  */
#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))

/* An XRARB_MASK, but with the L bits in a darn instruction clear.  */
#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))

/* An X_MASK with the RT and RA fields fixed.  */
#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)

/* An X_MASK with the RT and RB fields fixed.  */
#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)

/* An XRTRA_MASK, but with L bit clear.  */
#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))

/* An X_MASK with the RT, RA and RB fields fixed.  */
#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)

/* An XRTRARB_MASK, but with L bit clear.  */
#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))

/* An XRTRARB_MASK, but with A bit clear.  */
#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))

/* An XRTRARB_MASK, but with BF bits clear.  */
#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))

/* An X form instruction with the L bit specified.  */
#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))

/* An X form instruction with the L bits specified.  */
#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))

/* An X form instruction with the L bit and RC bit specified.  */
#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))

/* An X form instruction with RT fields specified */
#define XRT(op, xop, rt) (X ((op), (xop)) \
        | ((((unsigned long)(rt)) & 0x1f) << 21))

/* An X form instruction with RT and RA fields specified */
#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
        | ((((unsigned long)(rt)) & 0x1f) << 21) \
        | ((((unsigned long)(ra)) & 0x1f) << 16))

/* The mask for an X form comparison instruction.  */
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))

/* The mask for an X form comparison instruction with the L field
   fixed.  */
#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))

/* An X form trap instruction with the TO field specified.  */
#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
#define XTO_MASK (X_MASK | TO_MASK)

/* An X form tlb instruction with the SH field specified.  */
#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
#define XTLB_MASK (X_MASK | SH_MASK)

/* An X form sync instruction.  */
#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))

/* An X form sync instruction with everything filled in except the LS field.  */
#define XSYNC_MASK (0xff9fffff)

/* An X form sync instruction with everything filled in except the L and E fields.  */
#define XSYNCLE_MASK (0xff90ffff)

/* An X_MASK, but with the EH bit clear.  */
#define XEH_MASK (X_MASK & ~((unsigned long )1))

/* An X form AltiVec dss instruction.  */
#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)

/* An XFL form instruction.  */
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
#define XFL_MASK XFL (0x3f, 0x3ff, 1)

/* An X form isel instruction.  */
#define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
#define XISEL_MASK      XISEL(0x3f, 0x1f)

/* An XL form instruction with the LK field set to 0.  */
#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))

/* An XL form instruction which uses the LK field.  */
#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))

/* The mask for an XL form instruction.  */
#define XL_MASK XLLK (0x3f, 0x3ff, 1)

/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear.  */
#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))

/* An XL form instruction which explicitly sets the BO field.  */
#define XLO(op, bo, xop, lk) \
  (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
#define XLO_MASK (XL_MASK | BO_MASK)

/* An XL form instruction which explicitly sets the y bit of the BO
   field.  */
#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
#define XLYLK_MASK (XL_MASK | Y_MASK)

/* An XL form instruction which sets the BO field and the condition
   bits of the BI field.  */
#define XLOCB(op, bo, cb, xop, lk) \
  (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)

/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
#define XLBB_MASK (XL_MASK | BB_MASK)
#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)

/* A mask for branch instructions using the BH field.  */
#define XLBH_MASK (XL_MASK | (0x1c << 11))

/* An XL_MASK with the BO and BB fields fixed.  */
#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)

/* An XL_MASK with the BO, BI and BB fields fixed.  */
#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)

/* An X form mbar instruction with MO field.  */
#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))

/* An XO form instruction.  */
#define XO(op, xop, oe, rc) \
  (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
#define XO_MASK XO (0x3f, 0x1ff, 1, 1)

/* An XO_MASK with the RB field fixed.  */
#define XORB_MASK (XO_MASK | RB_MASK)

/* An XOPS form instruction for paired singles.  */
#define XOPS(op, xop, rc) \
  (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)


/* An XS form instruction.  */
#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
#define XS_MASK XS (0x3f, 0x1ff, 1)

/* A mask for the FXM version of an XFX form instruction.  */
#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))

/* An XFX form instruction with the FXM field filled in.  */
#define XFXM(op, xop, fxm, p4) \
  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
   | ((unsigned long)(p4) << 20))

/* An XFX form instruction with the SPR field filled in.  */
#define XSPR(op, xop, spr) \
  (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
#define XSPR_MASK (X_MASK | SPR_MASK)

/* An XFX form instruction with the SPR field filled in except for the
   SPRBAT field.  */
#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)

/* An XFX form instruction with the SPR field filled in except for the
   SPRG field.  */
#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))

/* An X form instruction with everything filled in except the E field.  */
#define XE_MASK (0xffff7fff)

/* An X form user context instruction.  */
#define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define XUC_MASK      XUC(0x3f, 0x1f)

/* An XW form instruction.  */
#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
/* The mask for a G form instruction. rc not supported at present.  */
#define XW_MASK XW (0x3f, 0x3f, 0)

/* An APU form instruction.  */
#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))

/* The mask for an APU form instruction.  */
#define APU_MASK APU (0x3f, 0x3ff, 1)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)

/* The BO encodings used in extended conditional branch mnemonics.  */
#define BODNZF  (0x0)
#define BODNZFP (0x1)
#define BODZF   (0x2)
#define BODZFP  (0x3)
#define BODNZT  (0x8)
#define BODNZTP (0x9)
#define BODZT   (0xa)
#define BODZTP  (0xb)

#define BOF     (0x4)
#define BOFP    (0x5)
#define BOFM4   (0x6)
#define BOFP4   (0x7)
#define BOT     (0xc)
#define BOTP    (0xd)
#define BOTM4   (0xe)
#define BOTP4   (0xf)

#define BODNZ   (0x10)
#define BODNZP  (0x11)
#define BODZ    (0x12)
#define BODZP   (0x13)
#define BODNZM4 (0x18)
#define BODNZP4 (0x19)
#define BODZM4  (0x1a)
#define BODZP4  (0x1b)

#define BOU     (0x14)

/* The BO16 encodings used in extended VLE conditional branch mnemonics.  */
#define BO16F   (0x0)
#define BO16T   (0x1)

/* The BO32 encodings used in extended VLE conditional branch mnemonics.  */
#define BO32F   (0x0)
#define BO32T   (0x1)
#define BO32DNZ (0x2)
#define BO32DZ  (0x3)

/* The BI condition bit encodings used in extended conditional branch
   mnemonics.  */
#define CBLT    (0)
#define CBGT    (1)
#define CBEQ    (2)
#define CBSO    (3)

/* The TO encodings used in extended trap mnemonics.  */
#define TOLGT   (0x1)
#define TOLLT   (0x2)
#define TOEQ    (0x4)
#define TOLGE   (0x5)
#define TOLNL   (0x5)
#define TOLLE   (0x6)
#define TOLNG   (0x6)
#define TOGT    (0x8)
#define TOGE    (0xc)
#define TONL    (0xc)
#define TOLT    (0x10)
#define TOLE    (0x14)
#define TONG    (0x14)
#define TONE    (0x18)
#define TOU     (0x1f)

/* Smaller names for the flags so each entry in the opcodes table will
   fit on a single line.  */
#undef  PPC
#define PPC     PPC_OPCODE_PPC
#define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define POWER4  PPC_OPCODE_POWER4
#define POWER5  PPC_OPCODE_POWER5
#define POWER6  PPC_OPCODE_POWER6
#define POWER7  PPC_OPCODE_POWER7
#define POWER8  PPC_OPCODE_POWER8
#define POWER9  PPC_OPCODE_POWER9
#define CELL    PPC_OPCODE_CELL
#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
#define NON32   (PPC_OPCODE_64 | PPC_OPCODE_POWER4      \
                 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
#define PPC403  PPC_OPCODE_403
#define PPC405  PPC_OPCODE_405
#define PPC440  PPC_OPCODE_440
#define PPC464  PPC440
#define PPC476  PPC_OPCODE_476
#define PPC750  PPC_OPCODE_750
#define PPC7450 PPC_OPCODE_7450
#define PPC860  PPC_OPCODE_860
#define PPCPS   PPC_OPCODE_PPCPS
#define PPCVEC  PPC_OPCODE_ALTIVEC
#define PPCVEC2 PPC_OPCODE_ALTIVEC2
#define PPCVEC3 PPC_OPCODE_ALTIVEC2
#define PPCVSX  PPC_OPCODE_VSX
#define PPCVSX2 PPC_OPCODE_VSX
#define PPCVSX3 PPC_OPCODE_VSX3
#define POWER   PPC_OPCODE_POWER
#define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
#define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
#define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
#define MFDEC1  PPC_OPCODE_POWER
#define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
#define BOOKE   PPC_OPCODE_BOOKE
#define NO371   PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
#define PPCE300 PPC_OPCODE_E300
#define PPCSPE  PPC_OPCODE_SPE
#define PPCISEL PPC_OPCODE_ISEL
#define PPCEFS  PPC_OPCODE_EFS
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR  PPC_OPCODE_PMR
#define PPCTMR  PPC_OPCODE_TMR
#define PPCCHLK PPC_OPCODE_CACHELCK
#define PPCRFMCI        PPC_OPCODE_RFMCI
#define E500MC  PPC_OPCODE_E500MC
#define PPCA2   PPC_OPCODE_A2
#define TITAN   PPC_OPCODE_TITAN

#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
#define E500    PPC_OPCODE_E500
#define E6500   PPC_OPCODE_E6500
#define PPCVLE  PPC_OPCODE_VLE
#define PPCHTM  PPC_OPCODE_HTM
#define E200Z4  PPC_OPCODE_E200Z4
/* The list of embedded processors that use the embedded operand ordering
   for the 3 operand dcbt and dcbtst instructions.  */
#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
                 | PPC_OPCODE_A2)



/* The opcode table.

   The format of the opcode table is:

   NAME         OPCODE          MASK         FLAGS      ANTI            {OPERANDS}

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   FLAGS are flags indicating which processors support the instruction.
   ANTI indicates which processors don't support the instruction.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.

   This table must be sorted by major opcode.  Please try to keep it
   vaguely sorted within major opcode too, except of course where
   constrained otherwise by disassembler operation.  */

const struct powerpc_opcode powerpc_opcodes[] = {
{"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476|PPCVLE,  {0}},
{"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdui",        OPTO(2,TOU),    OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
{"tdi",         OP(2),          OP_MASK,     PPC64,     PPCVLE,         {TO, RA, SI}},

{"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twui",        OPTO(3,TOU),    OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
{"tui",         OPTO(3,TOU),    OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
{"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCVLE,         {TO, RA, SI}},
{"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCVLE,         {TO, RA, SI}},

{"ps_cmpu0",    X  (4,   0),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
{"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmul10cuq",   VX (4,   1),    VXVB_MASK,   PPCVEC3,   0,              {VD, VA}},
{"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vcmpneb",     VXR(4,   7,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     0,              {FRT,RA,RB,PSWM,PSQM}},
{"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     0,              {FRS,RA,RB,PSWM,PSQM}},
{"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
{"machhwu",     XO (4,  12,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
{"machhwu.",    XO (4,  12,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
{"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
{"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"vmsumudm",    VXA(4,  35),    VXA_MASK,    PPCVEC3,   0,              {VD, VA, VB, VC}},
{"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
{"vsldoi",      VXA(4,  44),    VXASHB_MASK, PPCVEC,    0,              {VD, VA, VB, SHB}},
{"vpermxor",    VXA(4,  45),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
{"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VC, VB}},
{"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VC, VB}},
{"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
{"maddhd",      VXA(4,  48),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
{"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
{"maddhdu",     VXA(4,  49),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
{"ps_mul",      A  (4,  25,0),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
{"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
{"maddld",      VXA(4,  51),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
{"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
{"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
{"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vpermr",      VXA(4,  59),    VXA_MASK,    PPCVEC3,   0,              {VD, VA, VB, VC}},
{"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vaddeuqm",    VXA(4,  60),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
{"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vaddecuq",    VXA(4,  61),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
{"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vsubeuqm",    VXA(4,  62),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
{"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
{"vsubecuq",    VXA(4,  63),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
{"ps_cmpo0",    X  (4,  32),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
{"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmul10ecuq",  VX (4,  65),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vcmpneh",     VXR(4,  71,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     0,              {FRT,RA,RB,PSWM,PSQM}},
{"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     0,              {FRS,RA,RB,PSWM,PSQM}},
{"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"machhw",      XO (4,  44,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"machhw.",     XO (4,  44,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmachhw",     XO (4,  46,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmachhw.",    XO (4,  46,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_cmpu1",    X  (4,  64),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
{"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrlwmi",      VX (4,  133),   VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vcmpnew",     VXR(4,  135,0), VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vmulouw",     VX (4,  136),   VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vmuluwm",     VX (4,  137),   VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"machhwsu",    XO (4,  76,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"machhwsu.",   XO (4,  76,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_cmpo1",    X  (4,  96),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
{"vaddudm",     VX (4, 192),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vmaxud",      VX (4, 194),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vrld",        VX (4, 196),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vrldmi",      VX (4, 197),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vcmpequd",    VXR(4, 199,0),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
{"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"machhws",     XO (4, 108,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"machhws.",    XO (4, 108,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmachhws",    XO (4, 110,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmachhws.",   XO (4, 110,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vadduqm",     VX (4, 256),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vslb",        VX (4, 260),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpnezb",    VXR(4, 263,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrefp",       VX (4, 266),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"macchwu",     XO (4, 140,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"macchwu.",    XO (4, 140,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vaddcuq",     VX (4, 320),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vslh",        VX (4, 324),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpnezh",    VXR(4, 327,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrsqrtefp",   VX (4, 330),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"macchw",      XO (4, 172,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"macchw.",     XO (4, 172,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmacchw",     XO (4, 174,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmacchw.",    XO (4, 174,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vslw",        VX (4, 388),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrlwnm",      VX (4, 389),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vcmpnezw",    VXR(4, 391,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vmulosw",     VX (4, 392),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vexptefp",    VX (4, 394),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"macchwsu",    XO (4, 204,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"macchwsu.",   XO (4, 204,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vmaxsd",      VX (4, 450),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vsl",         VX (4, 452),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrldnm",      VX (4, 453),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vlogefp",     VX (4, 458),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"macchws",     XO (4, 236,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"macchws.",    XO (4, 236,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmacchws",    XO (4, 238,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmacchws.",   XO (4, 238,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmul10uq",    VX (4, 513),    VXVB_MASK,   PPCVEC3,   0,              {VD, VA}},
{"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE,    0,              {RS, RB, UIMM}},
{"vminub",      VX (4, 514),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    0,              {RS, RB, RA}},
{"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE,    0,              {RS, UIMM, RB}},
{"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    0,              {RS, RB, UIMM}},
{"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"evabs",       VX (4, 520),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evneg",       VX (4, 521),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vrfin",       VX (4, 522),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vspltb",      VX (4, 524),   VXUIMM4_MASK, PPCVEC,    0,              {VD, VB, UIMM4}},
{"vextractub",  VX (4, 525),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vupkhsb",     VX (4, 526),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"brinc",       VX (4, 527),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
{"evand",       VX (4, 529),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evandc",      VX (4, 530),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evxor",       VX (4, 534),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmr",        VX (4, 535),    VX_MASK,     PPCSPE,    0,              {RS, RA, BBA}},
{"evor",        VX (4, 535),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evnor",       VX (4, 536),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evnot",       VX (4, 536),    VX_MASK,     PPCSPE,    0,              {RS, RA, BBA}},
{"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
{"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evorc",       VX (4, 539),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evnand",      VX (4, 542),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
{"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
{"evslw",       VX (4, 548),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
{"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE,    0,              {RS, SIMM}},
{"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
{"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE,    0,              {RS, SIMM}},
{"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
{"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmul10euq",   VX (4, 577),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vrfiz",       VX (4, 586),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"vsplth",      VX (4, 588),   VXUIMM3_MASK, PPCVEC,    0,              {VD, VB, UIMM3}},
{"vextractuh",  VX (4, 589),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"vupkhsh",     VX (4, 590),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
{"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE,    0,              {RS, RA, RB, CRFS}},
{"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
{"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vmuleuw",     VX (4, 648),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vrfip",       VX (4, 650),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"vspltw",      VX (4, 652),   VXUIMM2_MASK, PPCVEC,    0,              {VD, VB, UIMM2}},
{"vextractuw",  VX (4, 653),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"vupklsb",     VX (4, 654),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
{"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
{"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
{"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
{"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"efssub",      VX (4, 705),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"vminud",      VX (4, 706),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
{"vsr",         VX (4, 708),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
{"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
{"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vcmpgtud",    VXR(4, 711,0),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
{"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"vrfim",       VX (4, 714),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"vextractd",   VX (4, 717),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"vupklsh",     VX (4, 718),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
{"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
{"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
{"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
{"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
{"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
{"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
{"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
{"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evldd",       VX (4, 769),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
{"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evldw",       VX (4, 771),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
{"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evldh",       VX (4, 773),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
{"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_2, RA}},
{"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"vcuxwfp",     VX (4, 778),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vspltisb",    VX (4, 780),    VXVB_MASK,   PPCVEC,    0,              {VD, SIMM}},
{"vinsertb",    VX (4, 781),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_2, RA}},
{"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_2, RA}},
{"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
{"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
{"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
{"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
{"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
{"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
{"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"bcdcpsgn.",   VX (4, 833),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"vcsxwfp",     VX (4, 842),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"vspltish",    VX (4, 844),    VXVB_MASK,   PPCVEC,    0,              {VD, SIMM}},
{"vinserth",    VX (4, 845),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"vupkhpx",     VX (4, 846),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
{"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
{"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
{"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
{"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
{"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vmulesw",     VX (4, 904),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"vcfpuxws",    VX (4, 906),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"vspltisw",    VX (4, 908),    VXVB_MASK,   PPCVEC,    0,              {VD, SIMM}},
{"vinsertw",    VX (4, 909),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"maclhwsu",    XO (4, 460,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"maclhwsu.",   XO (4, 460,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vminsd",      VX (4, 962),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vsrad",       VX (4, 964),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vcmpgtsd",    VXR(4, 967,0),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
{"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"vcfpsxws",    VX (4, 970),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
{"vinsertd",    VX (4, 973),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
{"vupklpx",     VX (4, 974),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
{"maclhws",     XO (4, 492,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"maclhws.",    XO (4, 492,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmaclhws",    XO (4, 494,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmaclhws.",   XO (4, 494,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"bcdadd.",     VX (4,1025),    VXPS_MASK,   PPCVEC2,   0,              {VD, VA, VB, PS}},
{"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vabsdub",     VX (4,1027),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vand",        VX (4,1028),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vcmpneb.",    VXR(4,   7,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"udi0fcm.",    APU(4, 515,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"udi0fcm",     APU(4, 515,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vpmsumb",     VX (4,1032),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vslo",        VX (4,1036),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"machhwuo",    XO (4,  12,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"machhwuo.",   XO (4,  12,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"bcdsub.",     VX (4,1089),    VXPS_MASK,   PPCVEC2,   0,              {VD, VA, VB, PS}},
{"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vabsduh",     VX (4,1091),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vandc",       VX (4,1092),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi1fcm.",    APU(4, 547,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"udi1fcm",     APU(4, 547,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"vcmpneh.",    VXR(4,  71,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vpmsumh",     VX (4,1096),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vsro",        VX (4,1100),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vpkudum",     VX (4,1102),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"machhwo",     XO (4,  44,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"machhwo.",    XO (4,  44,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"nmachhwo",    XO (4,  46,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmachhwo.",   XO (4,  46,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"bcdus.",      VX (4,1153),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vabsduw",     VX (4,1155),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vmr",         VX (4,1156),    VX_MASK,     PPCVEC,    0,              {VD, VA, VBA}},
{"vor",         VX (4,1156),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vcmpnew.",    VXR(4, 135,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vpmsumw",     VX (4,1160),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi2fcm.",    APU(4, 579,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"udi2fcm",     APU(4, 579,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"machhwsuo",   XO (4,  76,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"machhwsuo.",  XO (4,  76,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vsubudm",     VX (4,1216),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"bcds.",       VX (4,1217),    VXPS_MASK,   PPCVEC3,   0,              {VD, VA, VB, PS}},
{"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evmra",       VX (4,1220),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vxor",        VX (4,1220),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi3fcm.",    APU(4, 611,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"vcmpequd.",   VXR(4, 199,1),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
{"udi3fcm",     APU(4, 611,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vpmsumd",     VX (4,1224),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
{"vpkudus",     VX (4,1230),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"machhwso",    XO (4, 108,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"machhwso.",   XO (4, 108,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmachhwso",   XO (4, 110,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmachhwso.",  XO (4, 110,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
{"vsubuqm",     VX (4,1280),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"bcdtrunc.",   VX (4,1281),    VXPS_MASK,   PPCVEC3,   0,              {VD, VA, VB, PS}},
{"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vnot",        VX (4,1284),    VX_MASK,     PPCVEC,    0,              {VD, VA, VBA}},
{"vnor",        VX (4,1284),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"udi4fcm.",    APU(4, 643,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"udi4fcm",     APU(4, 643,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"vcmpnezb.",   VXR(4, 263,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vcipher",     VX (4,1288),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vcipherlast", VX (4,1289),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vgbbd",       VX (4,1292),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"macchwuo",    XO (4, 140,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"macchwuo.",   XO (4, 140,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vsubcuq",     VX (4,1344),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"bcdutrunc.",  VX (4,1345),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vorc",        VX (4,1348),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"udi5fcm.",    APU(4, 675,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"udi5fcm",     APU(4, 675,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"vcmpnezh.",   VXR(4, 327,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"vncipher",    VX (4,1352),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vncipherlast",VX (4,1353),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vbpermq",     VX (4,1356),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vpksdus",     VX (4,1358),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"macchwo",     XO (4, 172,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"macchwo.",    XO (4, 172,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"nmacchwo",    XO (4, 174,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmacchwo.",   XO (4, 174,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"bcdctsq.",    VXVA(4,1409,0), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
{"bcdcfsq.",    VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
{"bcdctz.",     VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
{"bcdctn.",     VXVA(4,1409,5), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
{"bcdcfz.",     VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
{"bcdcfn.",     VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
{"bcdsetsgn.",  VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3,  0,              {VD, VB, PS}},
{"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vnand",       VX (4,1412),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"udi6fcm.",    APU(4, 707,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"udi6fcm",     APU(4, 707,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"vcmpnezw.",   VXR(4, 391,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
{"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"macchwsuo",   XO (4, 204,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"macchwsuo.",  XO (4, 204,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"bcdsr.",      VX (4,1473),    VXPS_MASK,   PPCVEC3,   0,              {VD, VA, VB, PS}},
{"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vsld",        VX (4,1476),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi7fcm.",    APU(4, 739,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"udi7fcm",     APU(4, 739,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
{"vsbox",       VX (4,1480),    VXVB_MASK,   PPCVEC2,   0,              {VD, VA}},
{"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"vbpermd",     VX (4,1484),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vpksdss",     VX (4,1486),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"macchwso",    XO (4, 236,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"macchwso.",   XO (4, 236,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
{"nmacchwso",   XO (4, 238,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmacchwso.",  XO (4, 238,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vclzlsbb",    VXVA(4,1538,0), VXVA_MASK,   PPCVEC3,   0,              {RT, VB}},
{"vctzlsbb",    VXVA(4,1538,1), VXVA_MASK,   PPCVEC3,   0,              {RT, VB}},
{"vnegw",       VXVA(4,1538,6), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
{"vnegd",       VXVA(4,1538,7), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
{"vprtybw",     VXVA(4,1538,8), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
{"vprtybd",     VXVA(4,1538,9), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
{"vprtybq",     VXVA(4,1538,10), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vextsb2w",    VXVA(4,1538,16), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vextsh2w",    VXVA(4,1538,17), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vextsb2d",    VXVA(4,1538,24), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vextsh2d",    VXVA(4,1538,25), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vextsw2d",    VXVA(4,1538,26), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vctzb",       VXVA(4,1538,28), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vctzh",       VXVA(4,1538,29), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vctzw",       VXVA(4,1538,30), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"vctzd",       VXVA(4,1538,31), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
{"mfvscr",      VX (4,1540),    VXVAVB_MASK, PPCVEC,    0,              {VD}},
{"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vextublx",    VX (4,1549),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
{"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"mtvscr",      VX (4,1604),    VXVDVA_MASK, PPCVEC,    0,              {VB}},
{"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vextuhlx",    VX (4,1613),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
{"vupkhsw",     VX (4,1614),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vshasigmaw",  VX (4,1666),    VX_MASK,     PPCVEC2,   0,              {VD, VA, ST, SIX}},
{"veqv",        VX (4,1668),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmrgow",      VX (4,1676),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vextuwlx",    VX (4,1677),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
{"vshasigmad",  VX (4,1730),    VX_MASK,     PPCVEC2,   0,              {VD, VA, ST, SIX}},
{"vsrd",        VX (4,1732),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vcmpgtud.",   VXR(4, 711,1),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
{"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vupklsw",     VX (4,1742),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vclzb",       VX (4,1794),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vpopcntb",    VX (4,1795),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vsrv",        VX (4,1796),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vextubrx",    VX (4,1805),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
{"maclhwuo",    XO (4, 396,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"maclhwuo.",   XO (4, 396,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vclzh",       VX (4,1858),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vpopcnth",    VX (4,1859),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vslv",        VX (4,1860),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
{"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"vextuhrx",    VX (4,1869),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
{"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"maclhwo",     XO (4, 428,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"maclhwo.",    XO (4, 428,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmaclhwo",    XO (4, 430,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmaclhwo.",   XO (4, 430,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vclzw",       VX (4,1922),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vpopcntw",    VX (4,1923),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
{"vmrgew",      VX (4,1932),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
{"vextuwrx",    VX (4,1933),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
{"maclhwsuo",   XO (4, 460,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"maclhwsuo.",  XO (4, 460,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"vclzd",       VX (4,1986),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vpopcntd",    VX (4,1987),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
{"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
{"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"vcmpgtsd.",   VXR(4, 967,1),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
{"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
{"maclhwso",    XO (4, 492,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"maclhwso.",   XO (4, 492,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmaclhwso",   XO (4, 494,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"nmaclhwso.",  XO (4, 494,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
{"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     0,              {RA, RB}},

{"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
{"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},

{"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
{"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},

{"dozi",        OP(9),          OP_MASK,     M601,      PPCVLE,         {RT, RA, SI}},

{"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCVLE,         {OBF, RA, UISIGNOPT}},
{"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCVLE,         {OBF, RA, UISIGNOPT}},
{"cmpli",       OP(10),         OP_MASK,     PPC,       PPCVLE,         {BF, L32OPT, RA, UISIGNOPT}},
{"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPC|PPCVLE,     {BF, RA, UISIGNOPT}},

{"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCVLE,         {OBF, RA, SI}},
{"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCVLE,         {OBF, RA, SI}},
{"cmpi",        OP(11),         OP_MASK,     PPC,       PPCVLE,         {BF, L32OPT, RA, SI}},
{"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPC|PPCVLE,     {BF, RA, SI}},

{"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
{"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},
{"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, NSI}},

{"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
{"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},
{"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, NSI}},

{"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCVLE,         {RT, SI}},
{"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCVLE,         {RT, SI}},
{"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, SI}},
{"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, D, RA0}},
{"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, NSI}},
{"la",          OP(14),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, D, RA0}},

{"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCVLE,         {RT, SISIGNOPT}},
{"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCVLE,         {RT, SISIGNOPT}},
{"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, SISIGNOPT}},
{"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA0, SISIGNOPT}},
{"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, NSISIGNOPT}},

{"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
{"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
{"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BD}},
{"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BD}},
{"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
{"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
{"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BD}},
{"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BD}},
{"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
{"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
{"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDA}},
{"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BDA}},
{"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
{"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
{"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDA}},
{"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BDA}},
{"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
{"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
{"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCVLE,        {BD}},
{"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
{"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
{"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCVLE,        {BD}},
{"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
{"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
{"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCVLE,        {BDA}},
{"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
{"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
{"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCVLE,        {BDA}},

{"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BD}},
{"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BD}},
{"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDA}},
{"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDA}},

{"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
{"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
{"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
{"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
{"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
{"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
{"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},