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6
7#include <linux/slab.h>
8#include <linux/perf_event.h>
9#include <asm/cpu_mf.h>
10
11
12
13
14CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
24CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
25CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
26CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
27CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
28CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
29CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
30CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
31CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
32CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
33CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
34CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040);
35CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041);
36CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042);
37CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043);
38CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044);
39CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045);
40CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046);
41CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047);
42CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048);
43CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049);
44CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a);
45CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b);
46CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c);
47CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d);
48CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e);
49CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f);
50CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050);
51CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051);
52CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052);
53CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053);
54CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
55CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
56CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
57CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
58CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
59CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
60CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
61CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
62CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
63CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
64CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
65CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
66CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
67CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
68CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
69CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
70CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
71CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
72CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
73CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
74CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
75CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
76CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
77CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
78CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
79CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
80CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
81CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
82CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
83CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
84CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
85CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
86CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
87CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
88CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
89CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
90CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
91CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
92CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
93CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
94CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
95CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
96CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
97CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
98CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
99CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
100CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
101CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
102CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
103CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
104CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
105CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
106CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
107CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
108CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
109CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
110CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
111CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
112CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
113CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
114CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
115CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
116CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
117CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
118CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
119CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
120CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
121CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
122CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
123CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
124CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
125CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
126CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
127CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
128CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
129CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
130CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
131CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
132CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
133CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
134CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
135CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
136CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
137CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
138CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
139CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
140CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
141CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
142CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
143CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
144CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
145CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
146CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
147CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
148CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
149CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
150CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
151CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
152CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
153CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
154CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
155CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
156CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
157CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
158CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
159CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
160CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
161CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
162CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
163CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
164CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
165CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
166CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
167CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
168CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
169CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
170CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
171CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
172CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
173CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
174CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
175CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
176CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
177CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
178CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
179CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
180CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
181CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
182CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
183CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
184CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
185CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
186CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
187CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
188CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
189CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
190CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
191CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
192CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
193CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
194CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
195CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
196CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
197CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
198CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
199CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
200CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
201CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
202CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
203CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
204CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
205CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
206CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
207CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
208CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
209CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
210CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
211CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
212CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
213CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
214CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
215CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
216CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
217CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
218CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
219CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
220CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
221CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
222CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
223CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
224CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
225CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
226CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
227CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
228CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
229CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
230CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
231CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
232CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
233CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
234CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
235CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
236CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
237CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240
241CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
242CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
243CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
244CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
245CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
246CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
247CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
248CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
249CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
250CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
251CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
252CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
253CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
254CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
255CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
256CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
257CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
258CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
259CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
260CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
261CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
262CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
263CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
264CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
265CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
266CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
267CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
268CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
269CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
270CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
271CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
272CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
273CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
274CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
275CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
276CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
277CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
278CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
279CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
280CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
281CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
282CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
283CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
284CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
285CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
286CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
287CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
288CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
289CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
290CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
291CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
292CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
293CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
294CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
295CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
296CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
297CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
298
299static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
300 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
301 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
302 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
303 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
304 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
305 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
306 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
307 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
308 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
309 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
310 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
311 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
312 NULL,
313};
314
315static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
316 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
317 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
318 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
319 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
320 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
321 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
322 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
323 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
324 NULL,
325};
326
327static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
328 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
329 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
330 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
331 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
332 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
333 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
334 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
335 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
336 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
337 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
338 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
339 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
340 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
341 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
342 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
343 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
344 NULL,
345};
346
347static struct attribute *cpumcf_svn_6_pmu_event_attr[] __initdata = {
348 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
349 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
350 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
351 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
352 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
353 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
354 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
355 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
356 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
357 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
358 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
359 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
360 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
361 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
362 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
363 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
364 CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT),
365 CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT),
366 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT),
367 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT),
368 NULL,
369};
370
371static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
372 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
373 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
374 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
375 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
376 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
377 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
378 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
379 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
380 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
381 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
382 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
383 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
384 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
385 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
386 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
387 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
388 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
389 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
390 NULL,
391};
392
393static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
394 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
395 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
396 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
397 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
398 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
399 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
400 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
401 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
402 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
403 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
404 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
405 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
406 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
407 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
408 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
409 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
410 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
411 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
412 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
413 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
414 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
415 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
416 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
417 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
418 NULL,
419};
420
421static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
422 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
423 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
424 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
425 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
426 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
427 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
428 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
429 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
430 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
431 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
432 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
433 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
434 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
435 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
436 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
437 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
438 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
439 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
440 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
441 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
442 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
443 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
444 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
445 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
446 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
447 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
448 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
449 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
450 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
451 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
452 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
453 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
454 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
455 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
456 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
457 NULL,
458};
459
460static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
461 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
462 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
463 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
464 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
465 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
466 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
467 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
468 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
469 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
470 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
471 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
472 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
473 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
474 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
475 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
476 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
477 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
478 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
479 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
480 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
481 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
482 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
483 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
484 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
485 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
486 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
487 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
488 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
489 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
490 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
491 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
492 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
493 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
494 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
495 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
496 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
497 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
498 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
499 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
500 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
501 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
502 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
503 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
504 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
505 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
506 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
507 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
508 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
509 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
510 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
511 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
512 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
513 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
514 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
515 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
516 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
517 NULL,
518};
519
520static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
521 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
522 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
523 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
524 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
525 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
526 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
527 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
528 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
529 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
530 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
531 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
532 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
533 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
534 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
535 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
536 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
537 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
538 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
539 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
540 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
541 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
542 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
543 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
544 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
545 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
546 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
547 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
548 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
549 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
550 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
551 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
552 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
553 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
554 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
555 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
556 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
557 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
558 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
559 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
560 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
561 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
562 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
563 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
564 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
565 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
566 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
567 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
568 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
569 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
570 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
571 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
572 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
573 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
574 NULL,
575};
576
577static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
578 CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
579 CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
580 CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
581 CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
582 CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
583 CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
584 CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
585 CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
586 CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
587 CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
588 CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
589 CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
590 CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
591 CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
592 CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
593 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
594 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
595 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
596 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
597 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
598 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
599 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
600 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
601 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
602 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
603 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
604 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
605 CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
606 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
607 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
608 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
609 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
610 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
611 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
612 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
613 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
614 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
615 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
616 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
617 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
618 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
619 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
620 CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
621 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
622 CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
623 CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
624 CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
625 CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
626 CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
627 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
628 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
629 CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
630 CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
631 CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
632 CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
633 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
634 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
635 NULL,
636};
637
638
639
640static struct attribute_group cpumcf_pmu_events_group = {
641 .name = "events",
642};
643
644PMU_FORMAT_ATTR(event, "config:0-63");
645
646static struct attribute *cpumcf_pmu_format_attr[] = {
647 &format_attr_event.attr,
648 NULL,
649};
650
651static struct attribute_group cpumcf_pmu_format_group = {
652 .name = "format",
653 .attrs = cpumcf_pmu_format_attr,
654};
655
656static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
657 &cpumcf_pmu_events_group,
658 &cpumcf_pmu_format_group,
659 NULL,
660};
661
662
663static __init struct attribute **merge_attr(struct attribute **a,
664 struct attribute **b,
665 struct attribute **c)
666{
667 struct attribute **new;
668 int j, i;
669
670 for (j = 0; a[j]; j++)
671 ;
672 for (i = 0; b[i]; i++)
673 j++;
674 for (i = 0; c[i]; i++)
675 j++;
676 j++;
677
678 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL);
679 if (!new)
680 return NULL;
681 j = 0;
682 for (i = 0; a[i]; i++)
683 new[j++] = a[i];
684 for (i = 0; b[i]; i++)
685 new[j++] = b[i];
686 for (i = 0; c[i]; i++)
687 new[j++] = c[i];
688 new[j] = NULL;
689
690 return new;
691}
692
693__init const struct attribute_group **cpumf_cf_event_group(void)
694{
695 struct attribute **combined, **model, **cfvn, **csvn;
696 struct attribute *none[] = { NULL };
697 struct cpumf_ctr_info ci;
698 struct cpuid cpu_id;
699
700
701 qctri(&ci);
702 switch (ci.cfvn) {
703 case 1:
704 cfvn = cpumcf_fvn1_pmu_event_attr;
705 break;
706 case 3:
707 cfvn = cpumcf_fvn3_pmu_event_attr;
708 break;
709 default:
710 cfvn = none;
711 }
712
713
714 switch (ci.csvn) {
715 case 1 ... 5:
716 csvn = cpumcf_svn_12345_pmu_event_attr;
717 break;
718 case 6:
719 csvn = cpumcf_svn_6_pmu_event_attr;
720 break;
721 default:
722 csvn = none;
723 }
724
725
726 get_cpu_id(&cpu_id);
727 switch (cpu_id.machine) {
728 case 0x2097:
729 case 0x2098:
730 model = cpumcf_z10_pmu_event_attr;
731 break;
732 case 0x2817:
733 case 0x2818:
734 model = cpumcf_z196_pmu_event_attr;
735 break;
736 case 0x2827:
737 case 0x2828:
738 model = cpumcf_zec12_pmu_event_attr;
739 break;
740 case 0x2964:
741 case 0x2965:
742 model = cpumcf_z13_pmu_event_attr;
743 break;
744 case 0x3906:
745 case 0x3907:
746 model = cpumcf_z14_pmu_event_attr;
747 break;
748 case 0x8561:
749 case 0x8562:
750 model = cpumcf_z15_pmu_event_attr;
751 break;
752 default:
753 model = none;
754 break;
755 }
756
757 combined = merge_attr(cfvn, csvn, model);
758 if (combined)
759 cpumcf_pmu_events_group.attrs = combined;
760 return cpumcf_pmu_attr_groups;
761}
762
