LXR linux/arch/sh/include/asm/mmu

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 1999 Niibe Yutaka
   4 * Copyright (C) 2003 - 2007 Paul Mundt
   5 *
   6 * ASID handling idea taken from MIPS implementation.
   7 */
   8#ifndef __ASM_SH_MMU_CONTEXT_H
   9#define __ASM_SH_MMU_CONTEXT_H
  10
  11#include <cpu/mmu_context.h>
  12#include <asm/tlbflush.h>
  13#include <linux/uaccess.h>
  14#include <linux/mm_types.h>
  15
  16#include <asm/io.h>
  17#include <asm-generic/mm_hooks.h>
  18
  19/*
  20 * The MMU "context" consists of two things:
  21 *    (a) TLB cache version (or round, cycle whatever expression you like)
  22 *    (b) ASID (Address Space IDentifier)
  23 */
  24#ifdef CONFIG_CPU_HAS_PTEAEX
  25#define MMU_CONTEXT_ASID_MASK           0x0000ffff
  26#else
  27#define MMU_CONTEXT_ASID_MASK           0x000000ff
  28#endif
  29
  30#define MMU_CONTEXT_VERSION_MASK        (~0UL & ~MMU_CONTEXT_ASID_MASK)
  31#define MMU_CONTEXT_FIRST_VERSION       (MMU_CONTEXT_ASID_MASK + 1)
  32
  33/* Impossible ASID value, to differentiate from NO_CONTEXT. */
  34#define MMU_NO_ASID                     MMU_CONTEXT_FIRST_VERSION
  35#define NO_CONTEXT                      0UL
  36
  37#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
  38
  39#ifdef CONFIG_MMU
  40#define cpu_context(cpu, mm)    ((mm)->context.id[cpu])
  41
  42#define cpu_asid(cpu, mm)       \
  43        (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)
  44
  45/*
  46 * Virtual Page Number mask
  47 */
  48#define MMU_VPN_MASK    0xfffff000
  49
  50#include <asm/mmu_context_32.h>
  51
  52/*
  53 * Get MMU context if needed.
  54 */
  55static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
  56{
  57        unsigned long asid = asid_cache(cpu);
  58
  59        /* Check if we have old version of context. */
  60        if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
  61                /* It's up to date, do nothing */
  62                return;
  63
  64        /* It's old, we need to get new context with new version. */
  65        if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
  66                /*
  67                 * We exhaust ASID of this version.
  68                 * Flush all TLB and start new cycle.
  69                 */
  70                local_flush_tlb_all();
  71
  72                /*
  73                 * Fix version; Note that we avoid version #0
  74                 * to distinguish NO_CONTEXT.
  75                 */
  76                if (!asid)
  77                        asid = MMU_CONTEXT_FIRST_VERSION;
  78        }
  79
  80        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
  81}
  82
  83/*
  84 * Initialize the context related info for a new mm_struct
  85 * instance.
  86 */
  87#define init_new_context init_new_context
  88static inline int init_new_context(struct task_struct *tsk,
  89                                   struct mm_struct *mm)
  90{
  91        int i;
  92
  93        for_each_online_cpu(i)
  94                cpu_context(i, mm) = NO_CONTEXT;
  95
  96        return 0;
  97}
  98
  99/*
 100 * After we have set current->mm to a new value, this activates
 101 * the context for the new mm so we see the new mappings.
 102 */
 103static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
 104{
 105        get_mmu_context(mm, cpu);
 106        set_asid(cpu_asid(cpu, mm));
 107}
 108
 109static inline void switch_mm(struct mm_struct *prev,
 110                             struct mm_struct *next,
 111                             struct task_struct *tsk)
 112{
 113        unsigned int cpu = smp_processor_id();
 114
 115        if (likely(prev != next)) {
 116                cpumask_set_cpu(cpu, mm_cpumask(next));
 117                set_TTB(next->pgd);
 118                activate_context(next, cpu);
 119        } else
 120                if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)))
 121                        activate_context(next, cpu);
 122}
 123
 124#include <asm-generic/mmu_context.h>
 125
 126#else
 127
 128#define set_asid(asid)                  do { } while (0)
 129#define get_asid()                      (0)
 130#define cpu_asid(cpu, mm)               ({ (void)cpu; NO_CONTEXT; })
 131#define switch_and_save_asid(asid)      (0)
 132#define set_TTB(pgd)                    do { } while (0)
 133#define get_TTB()                       (0)
 134
 135#include <asm-generic/nommu_context.h>
 136
 137#endif /* CONFIG_MMU */
 138
 139#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
 140/*
 141 * If this processor has an MMU, we need methods to turn it off/on ..
 142 * paging_init() will also have to be updated for the processor in
 143 * question.
 144 */
 145static inline void enable_mmu(void)
 146{
 147        unsigned int cpu = smp_processor_id();
 148
 149        /* Enable MMU */
 150        __raw_writel(MMU_CONTROL_INIT, MMUCR);
 151        ctrl_barrier();
 152
 153        if (asid_cache(cpu) == NO_CONTEXT)
 154                asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
 155
 156        set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
 157}
 158
 159static inline void disable_mmu(void)
 160{
 161        unsigned long cr;
 162
 163        cr = __raw_readl(MMUCR);
 164        cr &= ~MMU_CONTROL_INIT;
 165        __raw_writel(cr, MMUCR);
 166
 167        ctrl_barrier();
 168}
 169#else
 170/*
 171 * MMU control handlers for processors lacking memory
 172 * management hardware.
 173 */
 174#define enable_mmu()    do { } while (0)
 175#define disable_mmu()   do { } while (0)
 176#endif
 177
 178#endif /* __ASM_SH_MMU_CONTEXT_H */
 179