LXR linux/arch/sh/include/asm/watchdog.h

   1/* SPDX-License-Identifier: GPL-2.0+
   2 *
   3 * include/asm-sh/watchdog.h
   4 *
   5 * Copyright (C) 2002, 2003 Paul Mundt
   6 * Copyright (C) 2009 Siemens AG
   7 * Copyright (C) 2009 Valentin Sitdikov
   8 */
   9#ifndef __ASM_SH_WATCHDOG_H
  10#define __ASM_SH_WATCHDOG_H
  11
  12#include <linux/types.h>
  13#include <linux/io.h>
  14
  15#define WTCNT_HIGH      0x5a
  16#define WTCSR_HIGH      0xa5
  17
  18#define WTCSR_CKS2      0x04
  19#define WTCSR_CKS1      0x02
  20#define WTCSR_CKS0      0x01
  21
  22#include <cpu/watchdog.h>
  23
  24/*
  25 * See cpu-sh2/watchdog.h for explanation of this stupidity..
  26 */
  27#ifndef WTCNT_R
  28#  define WTCNT_R       WTCNT
  29#endif
  30
  31#ifndef WTCSR_R
  32#  define WTCSR_R       WTCSR
  33#endif
  34
  35/*
  36 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
  37 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
  38 * something a little more reasonable, and really can't deal with anything
  39 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
  40 *
  41 * Clock Division Ratio         Overflow Period
  42 * --------------------------------------------
  43 *     1/32 (initial value)       41 usecs
  44 *     1/64                       82 usecs
  45 *     1/128                     164 usecs
  46 *     1/256                     328 usecs
  47 *     1/512                     656 usecs
  48 *     1/1024                   1.31 msecs
  49 *     1/2048                   2.62 msecs
  50 *     1/4096                   5.25 msecs
  51 */
  52#define WTCSR_CKS_32    0x00
  53#define WTCSR_CKS_64    0x01
  54#define WTCSR_CKS_128   0x02
  55#define WTCSR_CKS_256   0x03
  56#define WTCSR_CKS_512   0x04
  57#define WTCSR_CKS_1024  0x05
  58#define WTCSR_CKS_2048  0x06
  59#define WTCSR_CKS_4096  0x07
  60
  61#if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
  62/**
  63 *      sh_wdt_read_cnt - Read from Counter
  64 *      Reads back the WTCNT value.
  65 */
  66static inline __u32 sh_wdt_read_cnt(void)
  67{
  68        return __raw_readl(WTCNT_R);
  69}
  70
  71/**
  72 *      sh_wdt_write_cnt - Write to Counter
  73 *      @val: Value to write
  74 *
  75 *      Writes the given value @val to the lower byte of the timer counter.
  76 *      The upper byte is set manually on each write.
  77 */
  78static inline void sh_wdt_write_cnt(__u32 val)
  79{
  80        __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
  81}
  82
  83/**
  84 *      sh_wdt_write_bst - Write to Counter
  85 *      @val: Value to write
  86 *
  87 *      Writes the given value @val to the lower byte of the timer counter.
  88 *      The upper byte is set manually on each write.
  89 */
  90static inline void sh_wdt_write_bst(__u32 val)
  91{
  92        __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
  93}
  94/**
  95 *      sh_wdt_read_csr - Read from Control/Status Register
  96 *
  97 *      Reads back the WTCSR value.
  98 */
  99static inline __u32 sh_wdt_read_csr(void)
 100{
 101        return __raw_readl(WTCSR_R);
 102}
 103
 104/**
 105 *      sh_wdt_write_csr - Write to Control/Status Register
 106 *      @val: Value to write
 107 *
 108 *      Writes the given value @val to the lower byte of the control/status
 109 *      register. The upper byte is set manually on each write.
 110 */
 111static inline void sh_wdt_write_csr(__u32 val)
 112{
 113        __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
 114}
 115#else
 116/**
 117 *      sh_wdt_read_cnt - Read from Counter
 118 *      Reads back the WTCNT value.
 119 */
 120static inline __u8 sh_wdt_read_cnt(void)
 121{
 122        return __raw_readb(WTCNT_R);
 123}
 124
 125/**
 126 *      sh_wdt_write_cnt - Write to Counter
 127 *      @val: Value to write
 128 *
 129 *      Writes the given value @val to the lower byte of the timer counter.
 130 *      The upper byte is set manually on each write.
 131 */
 132static inline void sh_wdt_write_cnt(__u8 val)
 133{
 134        __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
 135}
 136
 137/**
 138 *      sh_wdt_read_csr - Read from Control/Status Register
 139 *
 140 *      Reads back the WTCSR value.
 141 */
 142static inline __u8 sh_wdt_read_csr(void)
 143{
 144        return __raw_readb(WTCSR_R);
 145}
 146
 147/**
 148 *      sh_wdt_write_csr - Write to Control/Status Register
 149 *      @val: Value to write
 150 *
 151 *      Writes the given value @val to the lower byte of the control/status
 152 *      register. The upper byte is set manually on each write.
 153 */
 154static inline void sh_wdt_write_csr(__u8 val)
 155{
 156        __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
 157}
 158#endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
 159#endif /* __ASM_SH_WATCHDOG_H */
 160