LXR linux/arch/sh/kernel/cpu/sh4/clock-sh4-202.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * arch/sh/kernel/cpu/sh4/clock-sh4-202.c
   4 *
   5 * Additional SH4-202 support for the clock framework
   6 *
   7 *  Copyright (C) 2005  Paul Mundt
   8 */
   9#include <linux/init.h>
  10#include <linux/kernel.h>
  11#include <linux/err.h>
  12#include <linux/io.h>
  13#include <linux/clkdev.h>
  14#include <asm/clock.h>
  15#include <asm/freq.h>
  16
  17#define CPG2_FRQCR3     0xfe0a0018
  18
  19static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
  20static int frqcr3_values[]   = { 0, 1, 2, 3, 4, 5, 6  };
  21
  22static unsigned long emi_clk_recalc(struct clk *clk)
  23{
  24        int idx = __raw_readl(CPG2_FRQCR3) & 0x0007;
  25        return clk->parent->rate / frqcr3_divisors[idx];
  26}
  27
  28static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
  29{
  30        int divisor = clk->parent->rate / rate;
  31        int i;
  32
  33        for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++)
  34                if (frqcr3_divisors[i] == divisor)
  35                        return frqcr3_values[i];
  36
  37        /* Safe fallback */
  38        return 5;
  39}
  40
  41static struct sh_clk_ops sh4202_emi_clk_ops = {
  42        .recalc         = emi_clk_recalc,
  43};
  44
  45static struct clk sh4202_emi_clk = {
  46        .flags          = CLK_ENABLE_ON_INIT,
  47        .ops            = &sh4202_emi_clk_ops,
  48};
  49
  50static unsigned long femi_clk_recalc(struct clk *clk)
  51{
  52        int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007;
  53        return clk->parent->rate / frqcr3_divisors[idx];
  54}
  55
  56static struct sh_clk_ops sh4202_femi_clk_ops = {
  57        .recalc         = femi_clk_recalc,
  58};
  59
  60static struct clk sh4202_femi_clk = {
  61        .flags          = CLK_ENABLE_ON_INIT,
  62        .ops            = &sh4202_femi_clk_ops,
  63};
  64
  65static void shoc_clk_init(struct clk *clk)
  66{
  67        int i;
  68
  69        /*
  70         * For some reason, the shoc_clk seems to be set to some really
  71         * insane value at boot (values outside of the allowable frequency
  72         * range for instance). We deal with this by scaling it back down
  73         * to something sensible just in case.
  74         *
  75         * Start scaling from the high end down until we find something
  76         * that passes rate verification..
  77         */
  78        for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
  79                int divisor = frqcr3_divisors[i];
  80
  81                if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
  82                        break;
  83        }
  84
  85        WARN_ON(i == ARRAY_SIZE(frqcr3_divisors));      /* Undefined clock */
  86}
  87
  88static unsigned long shoc_clk_recalc(struct clk *clk)
  89{
  90        int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007;
  91        return clk->parent->rate / frqcr3_divisors[idx];
  92}
  93
  94static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
  95{
  96        struct clk *bclk = clk_get(NULL, "bus_clk");
  97        unsigned long bclk_rate = clk_get_rate(bclk);
  98
  99        clk_put(bclk);
 100
 101        if (rate > bclk_rate)
 102                return 1;
 103        if (rate > 66000000)
 104                return 1;
 105
 106        return 0;
 107}
 108
 109static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
 110{
 111        unsigned long frqcr3;
 112        unsigned int tmp;
 113
 114        /* Make sure we have something sensible to switch to */
 115        if (shoc_clk_verify_rate(clk, rate) != 0)
 116                return -EINVAL;
 117
 118        tmp = frqcr3_lookup(clk, rate);
 119
 120        frqcr3 = __raw_readl(CPG2_FRQCR3);
 121        frqcr3 &= ~(0x0007 << 6);
 122        frqcr3 |= tmp << 6;
 123        __raw_writel(frqcr3, CPG2_FRQCR3);
 124
 125        clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
 126
 127        return 0;
 128}
 129
 130static struct sh_clk_ops sh4202_shoc_clk_ops = {
 131        .init           = shoc_clk_init,
 132        .recalc         = shoc_clk_recalc,
 133        .set_rate       = shoc_clk_set_rate,
 134};
 135
 136static struct clk sh4202_shoc_clk = {
 137        .flags          = CLK_ENABLE_ON_INIT,
 138        .ops            = &sh4202_shoc_clk_ops,
 139};
 140
 141static struct clk *sh4202_onchip_clocks[] = {
 142        &sh4202_emi_clk,
 143        &sh4202_femi_clk,
 144        &sh4202_shoc_clk,
 145};
 146
 147static struct clk_lookup lookups[] = {
 148        /* main clocks */
 149        CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
 150        CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk),
 151        CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
 152};
 153
 154int __init arch_clk_init(void)
 155{
 156        struct clk *clk;
 157        int i, ret = 0;
 158
 159        cpg_clk_init();
 160
 161        clk = clk_get(NULL, "master_clk");
 162        for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
 163                struct clk *clkp = sh4202_onchip_clocks[i];
 164
 165                clkp->parent = clk;
 166                ret |= clk_register(clkp);
 167        }
 168
 169        clk_put(clk);
 170
 171        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 172
 173        return ret;
 174}
 175