1
2#ifndef _ASM_X86_APIC_H
3#define _ASM_X86_APIC_H
4
5#include <linux/cpumask.h>
6
7#include <asm/alternative.h>
8#include <asm/cpufeature.h>
9#include <asm/apicdef.h>
10#include <linux/atomic.h>
11#include <asm/fixmap.h>
12#include <asm/mpspec.h>
13#include <asm/msr.h>
14#include <asm/hardirq.h>
15
16#define ARCH_APICTIMER_STOPS_ON_C3 1
17
18
19
20
21#define APIC_QUIET 0
22#define APIC_VERBOSE 1
23#define APIC_DEBUG 2
24
25
26#define APIC_EXTNMI_BSP 0
27#define APIC_EXTNMI_ALL 1
28#define APIC_EXTNMI_NONE 2
29
30
31
32
33
34
35
36#define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43extern void generic_apic_probe(void);
44#else
45static inline void generic_apic_probe(void)
46{
47}
48#endif
49
50#ifdef CONFIG_X86_LOCAL_APIC
51
52extern int apic_verbosity;
53extern int local_apic_timer_c2_ok;
54
55extern int disable_apic;
56extern unsigned int lapic_timer_period;
57
58extern enum apic_intr_mode_id apic_intr_mode;
59enum apic_intr_mode_id {
60 APIC_PIC,
61 APIC_VIRTUAL_WIRE,
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
63 APIC_SYMMETRIC_IO,
64 APIC_SYMMETRIC_IO_NO_ROUTING
65};
66
67#ifdef CONFIG_SMP
68extern void __inquire_remote_apic(int apicid);
69#else
70static inline void __inquire_remote_apic(int apicid)
71{
72}
73#endif
74
75static inline void default_inquire_remote_apic(int apicid)
76{
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
79}
80
81
82
83
84
85
86
87
88
89static inline bool apic_from_smp_config(void)
90{
91 return smp_found_config && !disable_apic;
92}
93
94
95
96
97#ifdef CONFIG_PARAVIRT
98#include <asm/paravirt.h>
99#endif
100
101extern int setup_profiling_timer(unsigned int);
102
103static inline void native_apic_mem_write(u32 reg, u32 v)
104{
105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
106
107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
108 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
109 ASM_OUTPUT2("0" (v), "m" (*addr)));
110}
111
112static inline u32 native_apic_mem_read(u32 reg)
113{
114 return *((volatile u32 *)(APIC_BASE + reg));
115}
116
117extern void native_apic_wait_icr_idle(void);
118extern u32 native_safe_apic_wait_icr_idle(void);
119extern void native_apic_icr_write(u32 low, u32 id);
120extern u64 native_apic_icr_read(void);
121
122static inline bool apic_is_x2apic_enabled(void)
123{
124 u64 msr;
125
126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
127 return false;
128 return msr & X2APIC_ENABLE;
129}
130
131extern void enable_IR_x2apic(void);
132
133extern int get_physical_broadcast(void);
134
135extern int lapic_get_maxlvt(void);
136extern void clear_local_APIC(void);
137extern void disconnect_bsp_APIC(int virt_wire_setup);
138extern void disable_local_APIC(void);
139extern void apic_soft_disable(void);
140extern void lapic_shutdown(void);
141extern void sync_Arb_IDs(void);
142extern void init_bsp_APIC(void);
143extern void apic_intr_mode_select(void);
144extern void apic_intr_mode_init(void);
145extern void init_apic_mappings(void);
146void register_lapic_address(unsigned long address);
147extern void setup_boot_APIC_clock(void);
148extern void setup_secondary_APIC_clock(void);
149extern void lapic_update_tsc_freq(void);
150
151#ifdef CONFIG_X86_64
152static inline int apic_force_enable(unsigned long addr)
153{
154 return -1;
155}
156#else
157extern int apic_force_enable(unsigned long addr);
158#endif
159
160extern void apic_ap_setup(void);
161
162
163
164
165#ifdef CONFIG_X86_64
166extern int apic_is_clustered_box(void);
167#else
168static inline int apic_is_clustered_box(void)
169{
170 return 0;
171}
172#endif
173
174extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
175extern void lapic_assign_system_vectors(void);
176extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
177extern void lapic_update_legacy_vectors(void);
178extern void lapic_online(void);
179extern void lapic_offline(void);
180extern bool apic_needs_pit(void);
181
182extern void apic_send_IPI_allbutself(unsigned int vector);
183
184#else
185static inline void lapic_shutdown(void) { }
186#define local_apic_timer_c2_ok 1
187static inline void init_apic_mappings(void) { }
188static inline void disable_local_APIC(void) { }
189# define setup_boot_APIC_clock x86_init_noop
190# define setup_secondary_APIC_clock x86_init_noop
191static inline void lapic_update_tsc_freq(void) { }
192static inline void init_bsp_APIC(void) { }
193static inline void apic_intr_mode_select(void) { }
194static inline void apic_intr_mode_init(void) { }
195static inline void lapic_assign_system_vectors(void) { }
196static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
197static inline bool apic_needs_pit(void) { return true; }
198#endif
199
200#ifdef CONFIG_X86_X2APIC
201static inline void native_apic_msr_write(u32 reg, u32 v)
202{
203 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
204 reg == APIC_LVR)
205 return;
206
207 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
208}
209
210static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
211{
212 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
213}
214
215static inline u32 native_apic_msr_read(u32 reg)
216{
217 u64 msr;
218
219 if (reg == APIC_DFR)
220 return -1;
221
222 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
223 return (u32)msr;
224}
225
226static inline void native_x2apic_wait_icr_idle(void)
227{
228
229 return;
230}
231
232static inline u32 native_safe_x2apic_wait_icr_idle(void)
233{
234
235 return 0;
236}
237
238static inline void native_x2apic_icr_write(u32 low, u32 id)
239{
240 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
241}
242
243static inline u64 native_x2apic_icr_read(void)
244{
245 unsigned long val;
246
247 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
248 return val;
249}
250
251extern int x2apic_mode;
252extern int x2apic_phys;
253extern void __init x2apic_set_max_apicid(u32 apicid);
254extern void __init check_x2apic(void);
255extern void x2apic_setup(void);
256static inline int x2apic_enabled(void)
257{
258 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
259}
260
261#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
262#else
263static inline void check_x2apic(void) { }
264static inline void x2apic_setup(void) { }
265static inline int x2apic_enabled(void) { return 0; }
266
267#define x2apic_mode (0)
268#define x2apic_supported() (0)
269#endif
270
271struct irq_data;
272
273
274
275
276
277
278
279
280
281
282struct apic {
283
284 void (*eoi_write)(u32 reg, u32 v);
285 void (*native_eoi_write)(u32 reg, u32 v);
286 void (*write)(u32 reg, u32 v);
287 u32 (*read)(u32 reg);
288
289
290 void (*wait_icr_idle)(void);
291 u32 (*safe_wait_icr_idle)(void);
292
293 void (*send_IPI)(int cpu, int vector);
294 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
295 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
296 void (*send_IPI_allbutself)(int vector);
297 void (*send_IPI_all)(int vector);
298 void (*send_IPI_self)(int vector);
299
300 u32 disable_esr;
301
302 enum apic_delivery_modes delivery_mode;
303 bool dest_mode_logical;
304
305 u32 (*calc_dest_apicid)(unsigned int cpu);
306
307
308 u64 (*icr_read)(void);
309 void (*icr_write)(u32 low, u32 high);
310
311
312 int (*probe)(void);
313 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
314 int (*apic_id_valid)(u32 apicid);
315 int (*apic_id_registered)(void);
316
317 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
318 void (*init_apic_ldr)(void);
319 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
320 void (*setup_apic_routing)(void);
321 int (*cpu_present_to_apicid)(int mps_cpu);
322 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
323 int (*check_phys_apicid_present)(int phys_apicid);
324 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
325
326 u32 (*get_apic_id)(unsigned long x);
327 u32 (*set_apic_id)(unsigned int id);
328
329
330 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
331
332 void (*inquire_remote_apic)(int apicid);
333
334#ifdef CONFIG_X86_32
335
336
337
338
339
340
341
342
343
344
345 int (*x86_32_early_logical_apicid)(int cpu);
346#endif
347 char *name;
348};
349
350
351
352
353
354
355extern struct apic *apic;
356
357
358
359
360
361
362
363
364
365#define apic_driver(sym) \
366 static const struct apic *__apicdrivers_##sym __used \
367 __aligned(sizeof(struct apic *)) \
368 __section(".apicdrivers") = { &sym }
369
370#define apic_drivers(sym1, sym2) \
371 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
372 __aligned(sizeof(struct apic *)) \
373 __section(".apicdrivers") = { &sym1, &sym2 }
374
375extern struct apic *__apicdrivers[], *__apicdrivers_end[];
376
377
378
379
380#ifdef CONFIG_SMP
381extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
382extern int lapic_can_unplug_cpu(void);
383#endif
384
385#ifdef CONFIG_X86_LOCAL_APIC
386
387static inline u32 apic_read(u32 reg)
388{
389 return apic->read(reg);
390}
391
392static inline void apic_write(u32 reg, u32 val)
393{
394 apic->write(reg, val);
395}
396
397static inline void apic_eoi(void)
398{
399 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
400}
401
402static inline u64 apic_icr_read(void)
403{
404 return apic->icr_read();
405}
406
407static inline void apic_icr_write(u32 low, u32 high)
408{
409 apic->icr_write(low, high);
410}
411
412static inline void apic_wait_icr_idle(void)
413{
414 apic->wait_icr_idle();
415}
416
417static inline u32 safe_apic_wait_icr_idle(void)
418{
419 return apic->safe_wait_icr_idle();
420}
421
422extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
423
424#else
425
426static inline u32 apic_read(u32 reg) { return 0; }
427static inline void apic_write(u32 reg, u32 val) { }
428static inline void apic_eoi(void) { }
429static inline u64 apic_icr_read(void) { return 0; }
430static inline void apic_icr_write(u32 low, u32 high) { }
431static inline void apic_wait_icr_idle(void) { }
432static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
433static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
434
435#endif
436
437extern void apic_ack_irq(struct irq_data *data);
438
439static inline void ack_APIC_irq(void)
440{
441
442
443
444
445 apic_eoi();
446}
447
448
449static inline bool lapic_vector_set_in_irr(unsigned int vector)
450{
451 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
452
453 return !!(irr & (1U << (vector % 32)));
454}
455
456static inline unsigned default_get_apic_id(unsigned long x)
457{
458 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
459
460 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
461 return (x >> 24) & 0xFF;
462 else
463 return (x >> 24) & 0x0F;
464}
465
466
467
468
469#define TRAMPOLINE_PHYS_LOW 0x467
470#define TRAMPOLINE_PHYS_HIGH 0x469
471
472extern void generic_bigsmp_probe(void);
473
474#ifdef CONFIG_X86_LOCAL_APIC
475
476#include <asm/smp.h>
477
478#define APIC_DFR_VALUE (APIC_DFR_FLAT)
479
480DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
481
482extern struct apic apic_noop;
483
484static inline unsigned int read_apic_id(void)
485{
486 unsigned int reg = apic_read(APIC_ID);
487
488 return apic->get_apic_id(reg);
489}
490
491extern int default_apic_id_valid(u32 apicid);
492extern int default_acpi_madt_oem_check(char *, char *);
493extern void default_setup_apic_routing(void);
494
495extern u32 apic_default_calc_apicid(unsigned int cpu);
496extern u32 apic_flat_calc_apicid(unsigned int cpu);
497
498extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
499extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
500extern int default_cpu_present_to_apicid(int mps_cpu);
501extern int default_check_phys_apicid_present(int phys_apicid);
502
503#endif
504
505#ifdef CONFIG_SMP
506bool apic_id_is_primary_thread(unsigned int id);
507void apic_smt_update(void);
508#else
509static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
510static inline void apic_smt_update(void) { }
511#endif
512
513struct msi_msg;
514struct irq_cfg;
515
516extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
517 bool dmar);
518
519extern void ioapic_zap_locks(void);
520
521#endif
522