1
2#ifndef _ASM_X86_TLBFLUSH_H
3#define _ASM_X86_TLBFLUSH_H
4
5#include <linux/mm.h>
6#include <linux/sched.h>
7
8#include <asm/processor.h>
9#include <asm/cpufeature.h>
10#include <asm/special_insns.h>
11#include <asm/smp.h>
12#include <asm/invpcid.h>
13#include <asm/pti.h>
14#include <asm/processor-flags.h>
15
16void __flush_tlb_all(void);
17
18#define TLB_FLUSH_ALL -1UL
19
20void cr4_update_irqsoff(unsigned long set, unsigned long clear);
21unsigned long cr4_read_shadow(void);
22
23
24static inline void cr4_set_bits_irqsoff(unsigned long mask)
25{
26 cr4_update_irqsoff(mask, 0);
27}
28
29
30static inline void cr4_clear_bits_irqsoff(unsigned long mask)
31{
32 cr4_update_irqsoff(0, mask);
33}
34
35
36static inline void cr4_set_bits(unsigned long mask)
37{
38 unsigned long flags;
39
40 local_irq_save(flags);
41 cr4_set_bits_irqsoff(mask);
42 local_irq_restore(flags);
43}
44
45
46static inline void cr4_clear_bits(unsigned long mask)
47{
48 unsigned long flags;
49
50 local_irq_save(flags);
51 cr4_clear_bits_irqsoff(mask);
52 local_irq_restore(flags);
53}
54
55#ifndef MODULE
56
57
58
59
60#define TLB_NR_DYN_ASIDS 6
61
62struct tlb_context {
63 u64 ctx_id;
64 u64 tlb_gen;
65};
66
67struct tlb_state {
68
69
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77
78
79 struct mm_struct *loaded_mm;
80
81#define LOADED_MM_SWITCHING ((struct mm_struct *)1UL)
82
83
84 union {
85 struct mm_struct *last_user_mm;
86 unsigned long last_user_mm_spec;
87 };
88
89 u16 loaded_mm_asid;
90 u16 next_asid;
91
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99
100
101 bool invalidate_other;
102
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106
107
108 unsigned short user_pcid_flush_mask;
109
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112
113
114 unsigned long cr4;
115
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134
135 struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
136};
137DECLARE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate);
138
139struct tlb_state_shared {
140
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153
154
155 bool is_lazy;
156};
157DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
158
159bool nmi_uaccess_okay(void);
160#define nmi_uaccess_okay nmi_uaccess_okay
161
162
163static inline void cr4_init_shadow(void)
164{
165 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
166}
167
168extern unsigned long mmu_cr4_features;
169extern u32 *trampoline_cr4_features;
170
171extern void initialize_tlbstate_and_flush(void);
172
173
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184
185
186struct flush_tlb_info {
187
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201
202
203 struct mm_struct *mm;
204 unsigned long start;
205 unsigned long end;
206 u64 new_tlb_gen;
207 unsigned int initiating_cpu;
208 u8 stride_shift;
209 u8 freed_tables;
210};
211
212void flush_tlb_local(void);
213void flush_tlb_one_user(unsigned long addr);
214void flush_tlb_one_kernel(unsigned long addr);
215void flush_tlb_multi(const struct cpumask *cpumask,
216 const struct flush_tlb_info *info);
217
218#ifdef CONFIG_PARAVIRT
219#include <asm/paravirt.h>
220#endif
221
222#define flush_tlb_mm(mm) \
223 flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL, true)
224
225#define flush_tlb_range(vma, start, end) \
226 flush_tlb_mm_range((vma)->vm_mm, start, end, \
227 ((vma)->vm_flags & VM_HUGETLB) \
228 ? huge_page_shift(hstate_vma(vma)) \
229 : PAGE_SHIFT, false)
230
231extern void flush_tlb_all(void);
232extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
233 unsigned long end, unsigned int stride_shift,
234 bool freed_tables);
235extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
236
237static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
238{
239 flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, PAGE_SHIFT, false);
240}
241
242static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
243{
244
245
246
247
248
249
250 return atomic64_inc_return(&mm->context.tlb_gen);
251}
252
253static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
254 struct mm_struct *mm)
255{
256 inc_mm_tlb_gen(mm);
257 cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
258}
259
260extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
261
262#endif
263
264#endif
265