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11#ifndef VMX_H
12#define VMX_H
13
14
15#include <linux/bitops.h>
16#include <linux/types.h>
17#include <uapi/asm/vmx.h>
18#include <asm/vmxfeatures.h>
19
20#define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
21
22
23
24
25#define CPU_BASED_INTR_WINDOW_EXITING VMCS_CONTROL_BIT(INTR_WINDOW_EXITING)
26#define CPU_BASED_USE_TSC_OFFSETTING VMCS_CONTROL_BIT(USE_TSC_OFFSETTING)
27#define CPU_BASED_HLT_EXITING VMCS_CONTROL_BIT(HLT_EXITING)
28#define CPU_BASED_INVLPG_EXITING VMCS_CONTROL_BIT(INVLPG_EXITING)
29#define CPU_BASED_MWAIT_EXITING VMCS_CONTROL_BIT(MWAIT_EXITING)
30#define CPU_BASED_RDPMC_EXITING VMCS_CONTROL_BIT(RDPMC_EXITING)
31#define CPU_BASED_RDTSC_EXITING VMCS_CONTROL_BIT(RDTSC_EXITING)
32#define CPU_BASED_CR3_LOAD_EXITING VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
33#define CPU_BASED_CR3_STORE_EXITING VMCS_CONTROL_BIT(CR3_STORE_EXITING)
34#define CPU_BASED_CR8_LOAD_EXITING VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
35#define CPU_BASED_CR8_STORE_EXITING VMCS_CONTROL_BIT(CR8_STORE_EXITING)
36#define CPU_BASED_TPR_SHADOW VMCS_CONTROL_BIT(VIRTUAL_TPR)
37#define CPU_BASED_NMI_WINDOW_EXITING VMCS_CONTROL_BIT(NMI_WINDOW_EXITING)
38#define CPU_BASED_MOV_DR_EXITING VMCS_CONTROL_BIT(MOV_DR_EXITING)
39#define CPU_BASED_UNCOND_IO_EXITING VMCS_CONTROL_BIT(UNCOND_IO_EXITING)
40#define CPU_BASED_USE_IO_BITMAPS VMCS_CONTROL_BIT(USE_IO_BITMAPS)
41#define CPU_BASED_MONITOR_TRAP_FLAG VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG)
42#define CPU_BASED_USE_MSR_BITMAPS VMCS_CONTROL_BIT(USE_MSR_BITMAPS)
43#define CPU_BASED_MONITOR_EXITING VMCS_CONTROL_BIT(MONITOR_EXITING)
44#define CPU_BASED_PAUSE_EXITING VMCS_CONTROL_BIT(PAUSE_EXITING)
45#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS VMCS_CONTROL_BIT(SEC_CONTROLS)
46
47#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
48
49
50
51
52#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES VMCS_CONTROL_BIT(VIRT_APIC_ACCESSES)
53#define SECONDARY_EXEC_ENABLE_EPT VMCS_CONTROL_BIT(EPT)
54#define SECONDARY_EXEC_DESC VMCS_CONTROL_BIT(DESC_EXITING)
55#define SECONDARY_EXEC_ENABLE_RDTSCP VMCS_CONTROL_BIT(RDTSCP)
56#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE VMCS_CONTROL_BIT(VIRTUAL_X2APIC)
57#define SECONDARY_EXEC_ENABLE_VPID VMCS_CONTROL_BIT(VPID)
58#define SECONDARY_EXEC_WBINVD_EXITING VMCS_CONTROL_BIT(WBINVD_EXITING)
59#define SECONDARY_EXEC_UNRESTRICTED_GUEST VMCS_CONTROL_BIT(UNRESTRICTED_GUEST)
60#define SECONDARY_EXEC_APIC_REGISTER_VIRT VMCS_CONTROL_BIT(APIC_REGISTER_VIRT)
61#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY VMCS_CONTROL_BIT(VIRT_INTR_DELIVERY)
62#define SECONDARY_EXEC_PAUSE_LOOP_EXITING VMCS_CONTROL_BIT(PAUSE_LOOP_EXITING)
63#define SECONDARY_EXEC_RDRAND_EXITING VMCS_CONTROL_BIT(RDRAND_EXITING)
64#define SECONDARY_EXEC_ENABLE_INVPCID VMCS_CONTROL_BIT(INVPCID)
65#define SECONDARY_EXEC_ENABLE_VMFUNC VMCS_CONTROL_BIT(VMFUNC)
66#define SECONDARY_EXEC_SHADOW_VMCS VMCS_CONTROL_BIT(SHADOW_VMCS)
67#define SECONDARY_EXEC_ENCLS_EXITING VMCS_CONTROL_BIT(ENCLS_EXITING)
68#define SECONDARY_EXEC_RDSEED_EXITING VMCS_CONTROL_BIT(RDSEED_EXITING)
69#define SECONDARY_EXEC_ENABLE_PML VMCS_CONTROL_BIT(PAGE_MOD_LOGGING)
70#define SECONDARY_EXEC_PT_CONCEAL_VMX VMCS_CONTROL_BIT(PT_CONCEAL_VMX)
71#define SECONDARY_EXEC_XSAVES VMCS_CONTROL_BIT(XSAVES)
72#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
73#define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA)
74#define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING)
75#define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE VMCS_CONTROL_BIT(USR_WAIT_PAUSE)
76#define SECONDARY_EXEC_BUS_LOCK_DETECTION VMCS_CONTROL_BIT(BUS_LOCK_DETECTION)
77
78#define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING)
79#define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING)
80#define PIN_BASED_VIRTUAL_NMIS VMCS_CONTROL_BIT(VIRTUAL_NMIS)
81#define PIN_BASED_VMX_PREEMPTION_TIMER VMCS_CONTROL_BIT(PREEMPTION_TIMER)
82#define PIN_BASED_POSTED_INTR VMCS_CONTROL_BIT(POSTED_INTR)
83
84#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
85
86#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
87#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
88#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
89#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
90#define VM_EXIT_SAVE_IA32_PAT 0x00040000
91#define VM_EXIT_LOAD_IA32_PAT 0x00080000
92#define VM_EXIT_SAVE_IA32_EFER 0x00100000
93#define VM_EXIT_LOAD_IA32_EFER 0x00200000
94#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
95#define VM_EXIT_CLEAR_BNDCFGS 0x00800000
96#define VM_EXIT_PT_CONCEAL_PIP 0x01000000
97#define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
98
99#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
100
101#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
102#define VM_ENTRY_IA32E_MODE 0x00000200
103#define VM_ENTRY_SMM 0x00000400
104#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
105#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
106#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
107#define VM_ENTRY_LOAD_IA32_EFER 0x00008000
108#define VM_ENTRY_LOAD_BNDCFGS 0x00010000
109#define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
110#define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
111
112#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
113
114#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
115#define VMX_MISC_SAVE_EFER_LMA 0x00000020
116#define VMX_MISC_ACTIVITY_HLT 0x00000040
117#define VMX_MISC_ACTIVITY_WAIT_SIPI 0x00000100
118#define VMX_MISC_ZERO_LEN_INS 0x40000000
119#define VMX_MISC_MSR_LIST_MULTIPLIER 512
120
121
122#define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
123
124#define VMX_VMFUNC_EPTP_SWITCHING VMFUNC_CONTROL_BIT(EPTP_SWITCHING)
125#define VMFUNC_EPTP_ENTRIES 512
126
127static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
128{
129 return vmx_basic & GENMASK_ULL(30, 0);
130}
131
132static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
133{
134 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
135}
136
137static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
138{
139 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
140}
141
142static inline int vmx_misc_cr3_count(u64 vmx_misc)
143{
144 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
145}
146
147static inline int vmx_misc_max_msr(u64 vmx_misc)
148{
149 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
150}
151
152static inline int vmx_misc_mseg_revid(u64 vmx_misc)
153{
154 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
155}
156
157
158enum vmcs_field {
159 VIRTUAL_PROCESSOR_ID = 0x00000000,
160 POSTED_INTR_NV = 0x00000002,
161 GUEST_ES_SELECTOR = 0x00000800,
162 GUEST_CS_SELECTOR = 0x00000802,
163 GUEST_SS_SELECTOR = 0x00000804,
164 GUEST_DS_SELECTOR = 0x00000806,
165 GUEST_FS_SELECTOR = 0x00000808,
166 GUEST_GS_SELECTOR = 0x0000080a,
167 GUEST_LDTR_SELECTOR = 0x0000080c,
168 GUEST_TR_SELECTOR = 0x0000080e,
169 GUEST_INTR_STATUS = 0x00000810,
170 GUEST_PML_INDEX = 0x00000812,
171 HOST_ES_SELECTOR = 0x00000c00,
172 HOST_CS_SELECTOR = 0x00000c02,
173 HOST_SS_SELECTOR = 0x00000c04,
174 HOST_DS_SELECTOR = 0x00000c06,
175 HOST_FS_SELECTOR = 0x00000c08,
176 HOST_GS_SELECTOR = 0x00000c0a,
177 HOST_TR_SELECTOR = 0x00000c0c,
178 IO_BITMAP_A = 0x00002000,
179 IO_BITMAP_A_HIGH = 0x00002001,
180 IO_BITMAP_B = 0x00002002,
181 IO_BITMAP_B_HIGH = 0x00002003,
182 MSR_BITMAP = 0x00002004,
183 MSR_BITMAP_HIGH = 0x00002005,
184 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
185 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
186 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
187 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
188 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
189 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
190 PML_ADDRESS = 0x0000200e,
191 PML_ADDRESS_HIGH = 0x0000200f,
192 TSC_OFFSET = 0x00002010,
193 TSC_OFFSET_HIGH = 0x00002011,
194 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
195 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
196 APIC_ACCESS_ADDR = 0x00002014,
197 APIC_ACCESS_ADDR_HIGH = 0x00002015,
198 POSTED_INTR_DESC_ADDR = 0x00002016,
199 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
200 VM_FUNCTION_CONTROL = 0x00002018,
201 VM_FUNCTION_CONTROL_HIGH = 0x00002019,
202 EPT_POINTER = 0x0000201a,
203 EPT_POINTER_HIGH = 0x0000201b,
204 EOI_EXIT_BITMAP0 = 0x0000201c,
205 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
206 EOI_EXIT_BITMAP1 = 0x0000201e,
207 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
208 EOI_EXIT_BITMAP2 = 0x00002020,
209 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
210 EOI_EXIT_BITMAP3 = 0x00002022,
211 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
212 EPTP_LIST_ADDRESS = 0x00002024,
213 EPTP_LIST_ADDRESS_HIGH = 0x00002025,
214 VMREAD_BITMAP = 0x00002026,
215 VMREAD_BITMAP_HIGH = 0x00002027,
216 VMWRITE_BITMAP = 0x00002028,
217 VMWRITE_BITMAP_HIGH = 0x00002029,
218 XSS_EXIT_BITMAP = 0x0000202C,
219 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
220 ENCLS_EXITING_BITMAP = 0x0000202E,
221 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
222 TSC_MULTIPLIER = 0x00002032,
223 TSC_MULTIPLIER_HIGH = 0x00002033,
224 GUEST_PHYSICAL_ADDRESS = 0x00002400,
225 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
226 VMCS_LINK_POINTER = 0x00002800,
227 VMCS_LINK_POINTER_HIGH = 0x00002801,
228 GUEST_IA32_DEBUGCTL = 0x00002802,
229 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
230 GUEST_IA32_PAT = 0x00002804,
231 GUEST_IA32_PAT_HIGH = 0x00002805,
232 GUEST_IA32_EFER = 0x00002806,
233 GUEST_IA32_EFER_HIGH = 0x00002807,
234 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
235 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
236 GUEST_PDPTR0 = 0x0000280a,
237 GUEST_PDPTR0_HIGH = 0x0000280b,
238 GUEST_PDPTR1 = 0x0000280c,
239 GUEST_PDPTR1_HIGH = 0x0000280d,
240 GUEST_PDPTR2 = 0x0000280e,
241 GUEST_PDPTR2_HIGH = 0x0000280f,
242 GUEST_PDPTR3 = 0x00002810,
243 GUEST_PDPTR3_HIGH = 0x00002811,
244 GUEST_BNDCFGS = 0x00002812,
245 GUEST_BNDCFGS_HIGH = 0x00002813,
246 GUEST_IA32_RTIT_CTL = 0x00002814,
247 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
248 HOST_IA32_PAT = 0x00002c00,
249 HOST_IA32_PAT_HIGH = 0x00002c01,
250 HOST_IA32_EFER = 0x00002c02,
251 HOST_IA32_EFER_HIGH = 0x00002c03,
252 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
253 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
254 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
255 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
256 EXCEPTION_BITMAP = 0x00004004,
257 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
258 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
259 CR3_TARGET_COUNT = 0x0000400a,
260 VM_EXIT_CONTROLS = 0x0000400c,
261 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
262 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
263 VM_ENTRY_CONTROLS = 0x00004012,
264 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
265 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
266 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
267 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
268 TPR_THRESHOLD = 0x0000401c,
269 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
270 PLE_GAP = 0x00004020,
271 PLE_WINDOW = 0x00004022,
272 VM_INSTRUCTION_ERROR = 0x00004400,
273 VM_EXIT_REASON = 0x00004402,
274 VM_EXIT_INTR_INFO = 0x00004404,
275 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
276 IDT_VECTORING_INFO_FIELD = 0x00004408,
277 IDT_VECTORING_ERROR_CODE = 0x0000440a,
278 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
279 VMX_INSTRUCTION_INFO = 0x0000440e,
280 GUEST_ES_LIMIT = 0x00004800,
281 GUEST_CS_LIMIT = 0x00004802,
282 GUEST_SS_LIMIT = 0x00004804,
283 GUEST_DS_LIMIT = 0x00004806,
284 GUEST_FS_LIMIT = 0x00004808,
285 GUEST_GS_LIMIT = 0x0000480a,
286 GUEST_LDTR_LIMIT = 0x0000480c,
287 GUEST_TR_LIMIT = 0x0000480e,
288 GUEST_GDTR_LIMIT = 0x00004810,
289 GUEST_IDTR_LIMIT = 0x00004812,
290 GUEST_ES_AR_BYTES = 0x00004814,
291 GUEST_CS_AR_BYTES = 0x00004816,
292 GUEST_SS_AR_BYTES = 0x00004818,
293 GUEST_DS_AR_BYTES = 0x0000481a,
294 GUEST_FS_AR_BYTES = 0x0000481c,
295 GUEST_GS_AR_BYTES = 0x0000481e,
296 GUEST_LDTR_AR_BYTES = 0x00004820,
297 GUEST_TR_AR_BYTES = 0x00004822,
298 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
299 GUEST_ACTIVITY_STATE = 0X00004826,
300 GUEST_SYSENTER_CS = 0x0000482A,
301 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
302 HOST_IA32_SYSENTER_CS = 0x00004c00,
303 CR0_GUEST_HOST_MASK = 0x00006000,
304 CR4_GUEST_HOST_MASK = 0x00006002,
305 CR0_READ_SHADOW = 0x00006004,
306 CR4_READ_SHADOW = 0x00006006,
307 CR3_TARGET_VALUE0 = 0x00006008,
308 CR3_TARGET_VALUE1 = 0x0000600a,
309 CR3_TARGET_VALUE2 = 0x0000600c,
310 CR3_TARGET_VALUE3 = 0x0000600e,
311 EXIT_QUALIFICATION = 0x00006400,
312 GUEST_LINEAR_ADDRESS = 0x0000640a,
313 GUEST_CR0 = 0x00006800,
314 GUEST_CR3 = 0x00006802,
315 GUEST_CR4 = 0x00006804,
316 GUEST_ES_BASE = 0x00006806,
317 GUEST_CS_BASE = 0x00006808,
318 GUEST_SS_BASE = 0x0000680a,
319 GUEST_DS_BASE = 0x0000680c,
320 GUEST_FS_BASE = 0x0000680e,
321 GUEST_GS_BASE = 0x00006810,
322 GUEST_LDTR_BASE = 0x00006812,
323 GUEST_TR_BASE = 0x00006814,
324 GUEST_GDTR_BASE = 0x00006816,
325 GUEST_IDTR_BASE = 0x00006818,
326 GUEST_DR7 = 0x0000681a,
327 GUEST_RSP = 0x0000681c,
328 GUEST_RIP = 0x0000681e,
329 GUEST_RFLAGS = 0x00006820,
330 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
331 GUEST_SYSENTER_ESP = 0x00006824,
332 GUEST_SYSENTER_EIP = 0x00006826,
333 HOST_CR0 = 0x00006c00,
334 HOST_CR3 = 0x00006c02,
335 HOST_CR4 = 0x00006c04,
336 HOST_FS_BASE = 0x00006c06,
337 HOST_GS_BASE = 0x00006c08,
338 HOST_TR_BASE = 0x00006c0a,
339 HOST_GDTR_BASE = 0x00006c0c,
340 HOST_IDTR_BASE = 0x00006c0e,
341 HOST_IA32_SYSENTER_ESP = 0x00006c10,
342 HOST_IA32_SYSENTER_EIP = 0x00006c12,
343 HOST_RSP = 0x00006c14,
344 HOST_RIP = 0x00006c16,
345};
346
347
348
349
350#define INTR_INFO_VECTOR_MASK 0xff
351#define INTR_INFO_INTR_TYPE_MASK 0x700
352#define INTR_INFO_DELIVER_CODE_MASK 0x800
353#define INTR_INFO_UNBLOCK_NMI 0x1000
354#define INTR_INFO_VALID_MASK 0x80000000
355#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
356
357#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
358#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
359#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
360#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
361
362#define INTR_TYPE_EXT_INTR (0 << 8)
363#define INTR_TYPE_RESERVED (1 << 8)
364#define INTR_TYPE_NMI_INTR (2 << 8)
365#define INTR_TYPE_HARD_EXCEPTION (3 << 8)
366#define INTR_TYPE_SOFT_INTR (4 << 8)
367#define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8)
368#define INTR_TYPE_SOFT_EXCEPTION (6 << 8)
369#define INTR_TYPE_OTHER_EVENT (7 << 8)
370
371
372#define GUEST_INTR_STATE_STI 0x00000001
373#define GUEST_INTR_STATE_MOV_SS 0x00000002
374#define GUEST_INTR_STATE_SMI 0x00000004
375#define GUEST_INTR_STATE_NMI 0x00000008
376#define GUEST_INTR_STATE_ENCLAVE_INTR 0x00000010
377
378
379#define GUEST_ACTIVITY_ACTIVE 0
380#define GUEST_ACTIVITY_HLT 1
381#define GUEST_ACTIVITY_SHUTDOWN 2
382#define GUEST_ACTIVITY_WAIT_SIPI 3
383
384
385
386
387#define CONTROL_REG_ACCESS_NUM 0x7
388#define CONTROL_REG_ACCESS_TYPE 0x30
389#define CONTROL_REG_ACCESS_REG 0xf00
390#define LMSW_SOURCE_DATA_SHIFT 16
391#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT)
392#define REG_EAX (0 << 8)
393#define REG_ECX (1 << 8)
394#define REG_EDX (2 << 8)
395#define REG_EBX (3 << 8)
396#define REG_ESP (4 << 8)
397#define REG_EBP (5 << 8)
398#define REG_ESI (6 << 8)
399#define REG_EDI (7 << 8)
400#define REG_R8 (8 << 8)
401#define REG_R9 (9 << 8)
402#define REG_R10 (10 << 8)
403#define REG_R11 (11 << 8)
404#define REG_R12 (12 << 8)
405#define REG_R13 (13 << 8)
406#define REG_R14 (14 << 8)
407#define REG_R15 (15 << 8)
408
409
410
411
412#define DEBUG_REG_ACCESS_NUM 0x7
413#define DEBUG_REG_ACCESS_TYPE 0x10
414#define TYPE_MOV_TO_DR (0 << 4)
415#define TYPE_MOV_FROM_DR (1 << 4)
416#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf)
417
418
419
420
421
422#define APIC_ACCESS_OFFSET 0xfff
423#define APIC_ACCESS_TYPE 0xf000
424#define TYPE_LINEAR_APIC_INST_READ (0 << 12)
425#define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
426#define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
427#define TYPE_LINEAR_APIC_EVENT (3 << 12)
428#define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
429#define TYPE_PHYSICAL_APIC_INST (15 << 12)
430
431
432#define VMX_SEGMENT_AR_L_MASK (1 << 13)
433
434#define VMX_AR_TYPE_ACCESSES_MASK 1
435#define VMX_AR_TYPE_READABLE_MASK (1 << 1)
436#define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
437#define VMX_AR_TYPE_CODE_MASK (1 << 3)
438#define VMX_AR_TYPE_MASK 0x0f
439#define VMX_AR_TYPE_BUSY_64_TSS 11
440#define VMX_AR_TYPE_BUSY_32_TSS 11
441#define VMX_AR_TYPE_BUSY_16_TSS 3
442#define VMX_AR_TYPE_LDT 2
443
444#define VMX_AR_UNUSABLE_MASK (1 << 16)
445#define VMX_AR_S_MASK (1 << 4)
446#define VMX_AR_P_MASK (1 << 7)
447#define VMX_AR_L_MASK (1 << 13)
448#define VMX_AR_DB_MASK (1 << 14)
449#define VMX_AR_G_MASK (1 << 15)
450#define VMX_AR_DPL_SHIFT 5
451#define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
452
453#define VMX_AR_RESERVD_MASK 0xfffe0f00
454
455#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
456#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
457#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
458
459#define VMX_NR_VPIDS (1 << 16)
460#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
461#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
462#define VMX_VPID_EXTENT_ALL_CONTEXT 2
463#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
464
465#define VMX_EPT_EXTENT_CONTEXT 1
466#define VMX_EPT_EXTENT_GLOBAL 2
467#define VMX_EPT_EXTENT_SHIFT 24
468
469#define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
470#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
471#define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7)
472#define VMX_EPTP_UC_BIT (1ull << 8)
473#define VMX_EPTP_WB_BIT (1ull << 14)
474#define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
475#define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
476#define VMX_EPT_INVEPT_BIT (1ull << 20)
477#define VMX_EPT_AD_BIT (1ull << 21)
478#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
479#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
480
481#define VMX_VPID_INVVPID_BIT (1ull << 0)
482#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8)
483#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9)
484#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10)
485#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11)
486
487#define VMX_EPT_MT_EPTE_SHIFT 3
488#define VMX_EPTP_PWL_MASK 0x38ull
489#define VMX_EPTP_PWL_4 0x18ull
490#define VMX_EPTP_PWL_5 0x20ull
491#define VMX_EPTP_AD_ENABLE_BIT (1ull << 6)
492#define VMX_EPTP_MT_MASK 0x7ull
493#define VMX_EPTP_MT_WB 0x6ull
494#define VMX_EPTP_MT_UC 0x0ull
495#define VMX_EPT_READABLE_MASK 0x1ull
496#define VMX_EPT_WRITABLE_MASK 0x2ull
497#define VMX_EPT_EXECUTABLE_MASK 0x4ull
498#define VMX_EPT_IPAT_BIT (1ull << 6)
499#define VMX_EPT_ACCESS_BIT (1ull << 8)
500#define VMX_EPT_DIRTY_BIT (1ull << 9)
501#define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
502 VMX_EPT_WRITABLE_MASK | \
503 VMX_EPT_EXECUTABLE_MASK)
504#define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
505
506static inline u8 vmx_eptp_page_walk_level(u64 eptp)
507{
508 u64 encoded_level = eptp & VMX_EPTP_PWL_MASK;
509
510 if (encoded_level == VMX_EPTP_PWL_5)
511 return 5;
512
513
514 WARN_ON_ONCE(encoded_level != VMX_EPTP_PWL_4);
515 return 4;
516}
517
518
519#define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
520 VMX_EPT_EXECUTABLE_MASK)
521
522#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
523
524struct vmx_msr_entry {
525 u32 index;
526 u32 reserved;
527 u64 value;
528} __aligned(16);
529
530
531
532
533enum vm_entry_failure_code {
534 ENTRY_FAIL_DEFAULT = 0,
535 ENTRY_FAIL_PDPTE = 2,
536 ENTRY_FAIL_NMI = 3,
537 ENTRY_FAIL_VMCS_LINK_PTR = 4,
538};
539
540
541
542
543#define EPT_VIOLATION_ACC_READ_BIT 0
544#define EPT_VIOLATION_ACC_WRITE_BIT 1
545#define EPT_VIOLATION_ACC_INSTR_BIT 2
546#define EPT_VIOLATION_READABLE_BIT 3
547#define EPT_VIOLATION_WRITABLE_BIT 4
548#define EPT_VIOLATION_EXECUTABLE_BIT 5
549#define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
550#define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
551#define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
552#define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
553#define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT)
554#define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT)
555#define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT)
556#define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
557
558
559
560
561enum vm_instruction_error_number {
562 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
563 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
564 VMXERR_VMCLEAR_VMXON_POINTER = 3,
565 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
566 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
567 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
568 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
569 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
570 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
571 VMXERR_VMPTRLD_VMXON_POINTER = 10,
572 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
573 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
574 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
575 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
576 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
577 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
578 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
579 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
580 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
581 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
582 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
583 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
584 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
585 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
586 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
587};
588
589
590
591
592
593
594
595#define VMX_VMENTER_INSTRUCTION_ERRORS \
596 { VMXERR_VMLAUNCH_NONCLEAR_VMCS, "VMLAUNCH_NONCLEAR_VMCS" }, \
597 { VMXERR_VMRESUME_NONLAUNCHED_VMCS, "VMRESUME_NONLAUNCHED_VMCS" }, \
598 { VMXERR_VMRESUME_AFTER_VMXOFF, "VMRESUME_AFTER_VMXOFF" }, \
599 { VMXERR_ENTRY_INVALID_CONTROL_FIELD, "VMENTRY_INVALID_CONTROL_FIELD" }, \
600 { VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, "VMENTRY_INVALID_HOST_STATE_FIELD" }, \
601 { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, "VMENTRY_EVENTS_BLOCKED_BY_MOV_SS" }
602
603enum vmx_l1d_flush_state {
604 VMENTER_L1D_FLUSH_AUTO,
605 VMENTER_L1D_FLUSH_NEVER,
606 VMENTER_L1D_FLUSH_COND,
607 VMENTER_L1D_FLUSH_ALWAYS,
608 VMENTER_L1D_FLUSH_EPT_DISABLED,
609 VMENTER_L1D_FLUSH_NOT_REQUIRED,
610};
611
612extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
613
614#endif
615
