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14#define pr_fmt(fmt) "AGP: " fmt
15
16#include <linux/kernel.h>
17#include <linux/kcore.h>
18#include <linux/types.h>
19#include <linux/init.h>
20#include <linux/memblock.h>
21#include <linux/mmzone.h>
22#include <linux/pci_ids.h>
23#include <linux/pci.h>
24#include <linux/bitops.h>
25#include <linux/suspend.h>
26#include <asm/e820/api.h>
27#include <asm/io.h>
28#include <asm/iommu.h>
29#include <asm/gart.h>
30#include <asm/pci-direct.h>
31#include <asm/dma.h>
32#include <asm/amd_nb.h>
33#include <asm/x86_init.h>
34#include <linux/crash_dump.h>
35
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45
46
47
48
49#define GART_MIN_ADDR (512ULL << 20)
50#define GART_MAX_ADDR (1ULL << 32)
51
52int gart_iommu_aperture;
53int gart_iommu_aperture_disabled __initdata;
54int gart_iommu_aperture_allowed __initdata;
55
56int fallback_aper_order __initdata = 1;
57int fallback_aper_force __initdata;
58
59int fix_aperture __initdata = 1;
60
61#if defined(CONFIG_PROC_VMCORE) || defined(CONFIG_PROC_KCORE)
62
63
64
65
66
67
68static unsigned long aperture_pfn_start, aperture_page_count;
69
70static int gart_mem_pfn_is_ram(unsigned long pfn)
71{
72 return likely((pfn < aperture_pfn_start) ||
73 (pfn >= aperture_pfn_start + aperture_page_count));
74}
75
76static void __init exclude_from_core(u64 aper_base, u32 aper_order)
77{
78 aperture_pfn_start = aper_base >> PAGE_SHIFT;
79 aperture_page_count = (32 * 1024 * 1024) << aper_order >> PAGE_SHIFT;
80#ifdef CONFIG_PROC_VMCORE
81 WARN_ON(register_oldmem_pfn_is_ram(&gart_mem_pfn_is_ram));
82#endif
83#ifdef CONFIG_PROC_KCORE
84 WARN_ON(register_mem_pfn_is_ram(&gart_mem_pfn_is_ram));
85#endif
86}
87#else
88static void exclude_from_core(u64 aper_base, u32 aper_order)
89{
90}
91#endif
92
93
94
95
96static u32 __init allocate_aperture(void)
97{
98 u32 aper_size;
99 unsigned long addr;
100
101
102 if (fallback_aper_order > 5)
103 fallback_aper_order = 5;
104 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
105
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111
112 addr = memblock_phys_alloc_range(aper_size, aper_size,
113 GART_MIN_ADDR, GART_MAX_ADDR);
114 if (!addr) {
115 pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n",
116 addr, addr + aper_size - 1, aper_size >> 10);
117 return 0;
118 }
119 pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n",
120 addr, addr + aper_size - 1, aper_size >> 10);
121 register_nosave_region(addr >> PAGE_SHIFT,
122 (addr+aper_size) >> PAGE_SHIFT);
123
124 return (u32)addr;
125}
126
127
128
129static u32 __init find_cap(int bus, int slot, int func, int cap)
130{
131 int bytes;
132 u8 pos;
133
134 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
135 PCI_STATUS_CAP_LIST))
136 return 0;
137
138 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
139 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
140 u8 id;
141
142 pos &= ~3;
143 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
144 if (id == 0xff)
145 break;
146 if (id == cap)
147 return pos;
148 pos = read_pci_config_byte(bus, slot, func,
149 pos+PCI_CAP_LIST_NEXT);
150 }
151 return 0;
152}
153
154
155static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
156{
157 u32 apsize;
158 u32 apsizereg;
159 int nbits;
160 u32 aper_low, aper_hi;
161 u64 aper;
162 u32 old_order;
163
164 pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);
165 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
166 if (apsizereg == 0xffffffff) {
167 pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n",
168 bus, slot, func);
169 return 0;
170 }
171
172
173 old_order = *order;
174
175 apsize = apsizereg & 0xfff;
176
177 if (apsize & 0xff)
178 apsize |= 0xf00;
179 nbits = hweight16(apsize);
180 *order = 7 - nbits;
181 if ((int)*order < 0)
182 *order = 0;
183
184 aper_low = read_pci_config(bus, slot, func, 0x10);
185 aper_hi = read_pci_config(bus, slot, func, 0x14);
186 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
187
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190
191
192 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n",
193 bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,
194 32 << old_order);
195 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
196 pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n",
197 bus, slot, func, 32 << *order, apsizereg);
198 *order = old_order;
199 }
200
201 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n",
202 bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,
203 32 << *order, apsizereg);
204
205 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
206 return 0;
207 return (u32)aper;
208}
209
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222
223static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
224{
225 int bus, slot, func;
226
227
228 for (bus = 0; bus < 256; bus++) {
229 for (slot = 0; slot < 32; slot++) {
230 for (func = 0; func < 8; func++) {
231 u32 class, cap;
232 u8 type;
233 class = read_pci_config(bus, slot, func,
234 PCI_CLASS_REVISION);
235 if (class == 0xffffffff)
236 break;
237
238 switch (class >> 16) {
239 case PCI_CLASS_BRIDGE_HOST:
240 case PCI_CLASS_BRIDGE_OTHER:
241
242 cap = find_cap(bus, slot, func,
243 PCI_CAP_ID_AGP);
244 if (!cap)
245 break;
246 *valid_agp = 1;
247 return read_agp(bus, slot, func, cap,
248 order);
249 }
250
251
252 type = read_pci_config_byte(bus, slot, func,
253 PCI_HEADER_TYPE);
254 if (!(type & 0x80))
255 break;
256 }
257 }
258 }
259 pr_info("No AGP bridge found\n");
260
261 return 0;
262}
263
264static bool gart_fix_e820 __initdata = true;
265
266static int __init parse_gart_mem(char *p)
267{
268 return kstrtobool(p, &gart_fix_e820);
269}
270early_param("gart_fix_e820", parse_gart_mem);
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287void __init early_gart_iommu_check(void)
288{
289 u32 agp_aper_order = 0;
290 int i, fix, slot, valid_agp = 0;
291 u32 ctl;
292 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
293 u64 aper_base = 0, last_aper_base = 0;
294 int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
295
296 if (!amd_gart_present())
297 return;
298
299 if (!early_pci_allowed())
300 return;
301
302
303 search_agp_bridge(&agp_aper_order, &valid_agp);
304
305 fix = 0;
306 for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
307 int bus;
308 int dev_base, dev_limit;
309
310 bus = amd_nb_bus_dev_ranges[i].bus;
311 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
312 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
313
314 for (slot = dev_base; slot < dev_limit; slot++) {
315 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
316 continue;
317
318 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
319 aper_enabled = ctl & GARTEN;
320 aper_order = (ctl >> 1) & 7;
321 aper_size = (32 * 1024 * 1024) << aper_order;
322 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
323 aper_base <<= 25;
324
325 if (last_valid) {
326 if ((aper_order != last_aper_order) ||
327 (aper_base != last_aper_base) ||
328 (aper_enabled != last_aper_enabled)) {
329 fix = 1;
330 break;
331 }
332 }
333
334 last_aper_order = aper_order;
335 last_aper_base = aper_base;
336 last_aper_enabled = aper_enabled;
337 last_valid = 1;
338 }
339 }
340
341 if (!fix && !aper_enabled)
342 return;
343
344 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
345 fix = 1;
346
347 if (gart_fix_e820 && !fix && aper_enabled) {
348 if (e820__mapped_any(aper_base, aper_base + aper_size,
349 E820_TYPE_RAM)) {
350
351 pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n",
352 aper_base, aper_base + aper_size - 1);
353 e820__range_add(aper_base, aper_size, E820_TYPE_RESERVED);
354 e820__update_table_print();
355 }
356 }
357
358 if (valid_agp)
359 return;
360
361
362 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
363 int bus;
364 int dev_base, dev_limit;
365
366 bus = amd_nb_bus_dev_ranges[i].bus;
367 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
368 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
369
370 for (slot = dev_base; slot < dev_limit; slot++) {
371 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
372 continue;
373
374 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
375 ctl &= ~GARTEN;
376 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
377 }
378 }
379
380}
381
382static int __initdata printed_gart_size_msg;
383
384int __init gart_iommu_hole_init(void)
385{
386 u32 agp_aper_base = 0, agp_aper_order = 0;
387 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
388 u64 aper_base, last_aper_base = 0;
389 int fix, slot, valid_agp = 0;
390 int i, node;
391
392 if (!amd_gart_present())
393 return -ENODEV;
394
395 if (gart_iommu_aperture_disabled || !fix_aperture ||
396 !early_pci_allowed())
397 return -ENODEV;
398
399 pr_info("Checking aperture...\n");
400
401 if (!fallback_aper_force)
402 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
403
404 fix = 0;
405 node = 0;
406 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
407 int bus;
408 int dev_base, dev_limit;
409 u32 ctl;
410
411 bus = amd_nb_bus_dev_ranges[i].bus;
412 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
413 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
414
415 for (slot = dev_base; slot < dev_limit; slot++) {
416 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
417 continue;
418
419 iommu_detected = 1;
420 gart_iommu_aperture = 1;
421 x86_init.iommu.iommu_init = gart_iommu_init;
422
423 ctl = read_pci_config(bus, slot, 3,
424 AMD64_GARTAPERTURECTL);
425
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430
431
432 ctl &= ~GARTEN;
433 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
434
435 aper_order = (ctl >> 1) & 7;
436 aper_size = (32 * 1024 * 1024) << aper_order;
437 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
438 aper_base <<= 25;
439
440 pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n",
441 node, aper_base, aper_base + aper_size - 1,
442 aper_size >> 20);
443 node++;
444
445 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
446 if (valid_agp && agp_aper_base &&
447 agp_aper_base == aper_base &&
448 agp_aper_order == aper_order) {
449
450 if (!no_iommu &&
451 max_pfn > MAX_DMA32_PFN &&
452 !printed_gart_size_msg) {
453 pr_err("you are using iommu with agp, but GART size is less than 64MB\n");
454 pr_err("please increase GART size in your BIOS setup\n");
455 pr_err("if BIOS doesn't have that option, contact your HW vendor!\n");
456 printed_gart_size_msg = 1;
457 }
458 } else {
459 fix = 1;
460 goto out;
461 }
462 }
463
464 if ((last_aper_order && aper_order != last_aper_order) ||
465 (last_aper_base && aper_base != last_aper_base)) {
466 fix = 1;
467 goto out;
468 }
469 last_aper_order = aper_order;
470 last_aper_base = aper_base;
471 }
472 }
473
474out:
475 if (!fix && !fallback_aper_force) {
476 if (last_aper_base) {
477
478
479
480
481
482 exclude_from_core(last_aper_base, last_aper_order);
483
484 return 1;
485 }
486 return 0;
487 }
488
489 if (!fallback_aper_force) {
490 aper_alloc = agp_aper_base;
491 aper_order = agp_aper_order;
492 }
493
494 if (aper_alloc) {
495
496 } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
497 force_iommu ||
498 valid_agp ||
499 fallback_aper_force) {
500 pr_info("Your BIOS doesn't leave an aperture memory hole\n");
501 pr_info("Please enable the IOMMU option in the BIOS setup\n");
502 pr_info("This costs you %dMB of RAM\n",
503 32 << fallback_aper_order);
504
505 aper_order = fallback_aper_order;
506 aper_alloc = allocate_aperture();
507 if (!aper_alloc) {
508
509
510
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513
514
515
516 panic("Not enough memory for aperture");
517 }
518 } else {
519 return 0;
520 }
521
522
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525
526
527
528 exclude_from_core(aper_alloc, aper_order);
529
530
531 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
532 int bus, dev_base, dev_limit;
533
534
535
536
537
538 u32 ctl = aper_order << 1;
539
540 bus = amd_nb_bus_dev_ranges[i].bus;
541 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
542 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
543 for (slot = dev_base; slot < dev_limit; slot++) {
544 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
545 continue;
546
547 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
548 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
549 }
550 }
551
552 set_up_gart_resume(aper_order, aper_alloc);
553
554 return 1;
555}
556