LXR linux/arch/x86/kvm/lapic.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __KVM_X86_LAPIC_H
   3#define __KVM_X86_LAPIC_H
   4
   5#include <kvm/iodev.h>
   6
   7#include <linux/kvm_host.h>
   8
   9#include "hyperv.h"
  10
  11#define KVM_APIC_INIT           0
  12#define KVM_APIC_SIPI           1
  13#define KVM_APIC_LVT_NUM        6
  14
  15#define APIC_SHORT_MASK                 0xc0000
  16#define APIC_DEST_NOSHORT               0x0
  17#define APIC_DEST_MASK                  0x800
  18
  19#define APIC_BUS_CYCLE_NS       1
  20#define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)
  21
  22#define APIC_BROADCAST                  0xFF
  23#define X2APIC_BROADCAST                0xFFFFFFFFul
  24
  25enum lapic_mode {
  26        LAPIC_MODE_DISABLED = 0,
  27        LAPIC_MODE_INVALID = X2APIC_ENABLE,
  28        LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
  29        LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
  30};
  31
  32struct kvm_timer {
  33        struct hrtimer timer;
  34        s64 period;                             /* unit: ns */
  35        ktime_t target_expiration;
  36        u32 timer_mode;
  37        u32 timer_mode_mask;
  38        u64 tscdeadline;
  39        u64 expired_tscdeadline;
  40        u32 timer_advance_ns;
  41        s64 advance_expire_delta;
  42        atomic_t pending;                       /* accumulated triggered timers */
  43        bool hv_timer_in_use;
  44};
  45
  46struct kvm_lapic {
  47        unsigned long base_address;
  48        struct kvm_io_device dev;
  49        struct kvm_timer lapic_timer;
  50        u32 divide_count;
  51        struct kvm_vcpu *vcpu;
  52        bool sw_enabled;
  53        bool irr_pending;
  54        bool lvt0_in_nmi_mode;
  55        /* Number of bits set in ISR. */
  56        s16 isr_count;
  57        /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
  58        int highest_isr_cache;
  59        /**
  60         * APIC register page.  The layout matches the register layout seen by
  61         * the guest 1:1, because it is accessed by the vmx microcode.
  62         * Note: Only one register, the TPR, is used by the microcode.
  63         */
  64        void *regs;
  65        gpa_t vapic_addr;
  66        struct gfn_to_hva_cache vapic_cache;
  67        unsigned long pending_events;
  68        unsigned int sipi_vector;
  69};
  70
  71struct dest_map;
  72
  73int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
  74void kvm_free_lapic(struct kvm_vcpu *vcpu);
  75
  76int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
  77int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
  78int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
  79int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
  80void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
  81u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
  82void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
  83void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
  84void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
  85u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
  86void kvm_recalculate_apic_map(struct kvm *kvm);
  87void kvm_apic_set_version(struct kvm_vcpu *vcpu);
  88int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
  89int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
  90                       void *data);
  91bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
  92                           int shorthand, unsigned int dest, int dest_mode);
  93int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
  94void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
  95bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
  96bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
  97void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
  98int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
  99                     struct dest_map *dest_map);
 100int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
 101void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
 102
 103bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 104                struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
 105void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
 106
 107u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
 108int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 109int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
 110int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
 111enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
 112int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
 113
 114u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
 115void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
 116
 117void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
 118void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
 119
 120int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
 121void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
 122void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
 123
 124int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 125int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 126
 127int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 128int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 129
 130int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
 131void kvm_lapic_exit(void);
 132
 133#define VEC_POS(v) ((v) & (32 - 1))
 134#define REG_POS(v) (((v) >> 5) << 4)
 135
 136static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
 137{
 138        clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 139}
 140
 141static inline void kvm_lapic_set_vector(int vec, void *bitmap)
 142{
 143        set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 144}
 145
 146static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
 147{
 148        kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
 149        /*
 150         * irr_pending must be true if any interrupt is pending; set it after
 151         * APIC_IRR to avoid race with apic_clear_irr
 152         */
 153        apic->irr_pending = true;
 154}
 155
 156static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
 157{
 158        return *((u32 *) (apic->regs + reg_off));
 159}
 160
 161static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
 162{
 163        *((u32 *) (regs + reg_off)) = val;
 164}
 165
 166static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
 167{
 168        __kvm_lapic_set_reg(apic->regs, reg_off, val);
 169}
 170
 171DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
 172
 173static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
 174{
 175        if (static_branch_unlikely(&kvm_has_noapic_vcpu))
 176                return vcpu->arch.apic;
 177        return true;
 178}
 179
 180extern struct static_key_false_deferred apic_hw_disabled;
 181
 182static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
 183{
 184        if (static_branch_unlikely(&apic_hw_disabled.key))
 185                return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 186        return MSR_IA32_APICBASE_ENABLE;
 187}
 188
 189extern struct static_key_false_deferred apic_sw_disabled;
 190
 191static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
 192{
 193        if (static_branch_unlikely(&apic_sw_disabled.key))
 194                return apic->sw_enabled;
 195        return true;
 196}
 197
 198static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
 199{
 200        return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
 201}
 202
 203static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 204{
 205        return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
 206}
 207
 208static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 209{
 210        return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 211}
 212
 213static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
 214{
 215        return vcpu->arch.apic && vcpu->arch.apicv_active;
 216}
 217
 218static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
 219{
 220        return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
 221}
 222
 223static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
 224{
 225        return (irq->delivery_mode == APIC_DM_LOWEST ||
 226                        irq->msi_redir_hint);
 227}
 228
 229static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
 230{
 231        return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
 232}
 233
 234bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
 235
 236void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
 237
 238void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
 239                              unsigned long *vcpu_bitmap);
 240
 241bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 242                        struct kvm_vcpu **dest_vcpu);
 243int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 244                        const unsigned long *bitmap, u32 bitmap_size);
 245void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
 246void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
 247void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
 248bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
 249void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
 250bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
 251
 252static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
 253{
 254        return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 255}
 256
 257static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 258{
 259        return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 260}
 261
 262#endif
 263