LXR linux/arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h

   1/* 
   2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
   3 *
   4 *  NOTE:  This header file is not meant to be included directly.
   5 */
   6
   7/* This header file contains assembly-language definitions (assembly
   8   macros, etc.) for this specific Xtensa processor's TIE extensions
   9   and options.  It is customized to this Xtensa processor configuration.
  10
  11   Copyright (c) 1999-2014 Tensilica Inc.
  12
  13   Permission is hereby granted, free of charge, to any person obtaining
  14   a copy of this software and associated documentation files (the
  15   "Software"), to deal in the Software without restriction, including
  16   without limitation the rights to use, copy, modify, merge, publish,
  17   distribute, sublicense, and/or sell copies of the Software, and to
  18   permit persons to whom the Software is furnished to do so, subject to
  19   the following conditions:
  20
  21   The above copyright notice and this permission notice shall be included
  22   in all copies or substantial portions of the Software.
  23
  24   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  27   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  28   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  29   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  30   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
  31
  32#ifndef _XTENSA_CORE_TIE_ASM_H
  33#define _XTENSA_CORE_TIE_ASM_H
  34
  35/*  Selection parameter values for save-area save/restore macros:  */
  36/*  Option vs. TIE:  */
  37#define XTHAL_SAS_TIE   0x0001  /* custom extension or coprocessor */
  38#define XTHAL_SAS_OPT   0x0002  /* optional (and not a coprocessor) */
  39#define XTHAL_SAS_ANYOT 0x0003  /* both of the above */
  40/*  Whether used automatically by compiler:  */
  41#define XTHAL_SAS_NOCC  0x0004  /* not used by compiler w/o special opts/code */
  42#define XTHAL_SAS_CC    0x0008  /* used by compiler without special opts/code */
  43#define XTHAL_SAS_ANYCC 0x000C  /* both of the above */
  44/*  ABI handling across function calls:  */
  45#define XTHAL_SAS_CALR  0x0010  /* caller-saved */
  46#define XTHAL_SAS_CALE  0x0020  /* callee-saved */
  47#define XTHAL_SAS_GLOB  0x0040  /* global across function calls (in thread) */
  48#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
  49/*  Misc  */
  50#define XTHAL_SAS_ALL   0xFFFF  /* include all default NCP contents */
  51#define XTHAL_SAS3(optie,ccuse,abi)     ( ((optie) & XTHAL_SAS_ANYOT)  \
  52                                        | ((ccuse) & XTHAL_SAS_ANYCC)  \
  53                                        | ((abi)   & XTHAL_SAS_ANYABI) )
  54
  55
  56
  57    /*
  58     *  Macro to save all non-coprocessor (extra) custom TIE and optional state
  59     *  (not including zero-overhead loop registers).
  60     *  Required parameters:
  61     *      ptr         Save area pointer address register (clobbered)
  62     *                  (register must contain a 4 byte aligned address).
  63     *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
  64     *                  registers are clobbered, the remaining are unused).
  65     *  Optional parameters:
  66     *      continue    If macro invoked as part of a larger store sequence, set to 1
  67     *                  if this is not the first in the sequence.  Defaults to 0.
  68     *      ofs         Offset from start of larger sequence (from value of first ptr
  69     *                  in sequence) at which to store.  Defaults to next available space
  70     *                  (or 0 if <continue> is 0).
  71     *      select      Select what category(ies) of registers to store, as a bitmask
  72     *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
  73     *      alloc       Select what category(ies) of registers to allocate; if any
  74     *                  category is selected here that is not in <select>, space for
  75     *                  the corresponding registers is skipped without doing any store.
  76     */
  77    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
  78        xchal_sa_start  \continue, \ofs
  79        // Optional global register used by default by the compiler:
  80        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
  81        xchal_sa_align  \ptr, 0, 1020, 4, 4
  82        rur.THREADPTR   \at1            // threadptr option
  83        s32i    \at1, \ptr, .Lxchal_ofs_+0
  84        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
  85        .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
  86        xchal_sa_align  \ptr, 0, 1020, 4, 4
  87        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
  88        .endif
  89        // Optional caller-saved registers used by default by the compiler:
  90        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
  91        xchal_sa_align  \ptr, 0, 1016, 4, 4
  92        rsr.ACCLO       \at1            // MAC16 option
  93        s32i    \at1, \ptr, .Lxchal_ofs_+0
  94        rsr.ACCHI       \at1            // MAC16 option
  95        s32i    \at1, \ptr, .Lxchal_ofs_+4
  96        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
  97        .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  98        xchal_sa_align  \ptr, 0, 1016, 4, 4
  99        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
 100        .endif
 101        // Optional caller-saved registers not used by default by the compiler:
 102        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
 103        xchal_sa_align  \ptr, 0, 1000, 4, 4
 104        rsr.M0  \at1            // MAC16 option
 105        s32i    \at1, \ptr, .Lxchal_ofs_+0
 106        rsr.M1  \at1            // MAC16 option
 107        s32i    \at1, \ptr, .Lxchal_ofs_+4
 108        rsr.M2  \at1            // MAC16 option
 109        s32i    \at1, \ptr, .Lxchal_ofs_+8
 110        rsr.M3  \at1            // MAC16 option
 111        s32i    \at1, \ptr, .Lxchal_ofs_+12
 112        rsr.BR  \at1            // boolean option
 113        s32i    \at1, \ptr, .Lxchal_ofs_+16
 114        rsr.SCOMPARE1   \at1            // conditional store option
 115        s32i    \at1, \ptr, .Lxchal_ofs_+20
 116        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 24
 117        .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
 118        xchal_sa_align  \ptr, 0, 1000, 4, 4
 119        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 24
 120        .endif
 121    .endm       // xchal_ncp_store
 122
 123    /*
 124     *  Macro to restore all non-coprocessor (extra) custom TIE and optional state
 125     *  (not including zero-overhead loop registers).
 126     *  Required parameters:
 127     *      ptr         Save area pointer address register (clobbered)
 128     *                  (register must contain a 4 byte aligned address).
 129     *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
 130     *                  registers are clobbered, the remaining are unused).
 131     *  Optional parameters:
 132     *      continue    If macro invoked as part of a larger load sequence, set to 1
 133     *                  if this is not the first in the sequence.  Defaults to 0.
 134     *      ofs         Offset from start of larger sequence (from value of first ptr
 135     *                  in sequence) at which to load.  Defaults to next available space
 136     *                  (or 0 if <continue> is 0).
 137     *      select      Select what category(ies) of registers to load, as a bitmask
 138     *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
 139     *      alloc       Select what category(ies) of registers to allocate; if any
 140     *                  category is selected here that is not in <select>, space for
 141     *                  the corresponding registers is skipped without doing any load.
 142     */
 143    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
 144        xchal_sa_start  \continue, \ofs
 145        // Optional global register used by default by the compiler:
 146        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
 147        xchal_sa_align  \ptr, 0, 1020, 4, 4
 148        l32i    \at1, \ptr, .Lxchal_ofs_+0
 149        wur.THREADPTR   \at1            // threadptr option
 150        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
 151        .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
 152        xchal_sa_align  \ptr, 0, 1020, 4, 4
 153        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
 154        .endif
 155        // Optional caller-saved registers used by default by the compiler:
 156        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
 157        xchal_sa_align  \ptr, 0, 1016, 4, 4
 158        l32i    \at1, \ptr, .Lxchal_ofs_+0
 159        wsr.ACCLO       \at1            // MAC16 option
 160        l32i    \at1, \ptr, .Lxchal_ofs_+4
 161        wsr.ACCHI       \at1            // MAC16 option
 162        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
 163        .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
 164        xchal_sa_align  \ptr, 0, 1016, 4, 4
 165        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
 166        .endif
 167        // Optional caller-saved registers not used by default by the compiler:
 168        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
 169        xchal_sa_align  \ptr, 0, 1000, 4, 4
 170        l32i    \at1, \ptr, .Lxchal_ofs_+0
 171        wsr.M0  \at1            // MAC16 option
 172        l32i    \at1, \ptr, .Lxchal_ofs_+4
 173        wsr.M1  \at1            // MAC16 option
 174        l32i    \at1, \ptr, .Lxchal_ofs_+8
 175        wsr.M2  \at1            // MAC16 option
 176        l32i    \at1, \ptr, .Lxchal_ofs_+12
 177        wsr.M3  \at1            // MAC16 option
 178        l32i    \at1, \ptr, .Lxchal_ofs_+16
 179        wsr.BR  \at1            // boolean option
 180        l32i    \at1, \ptr, .Lxchal_ofs_+20
 181        wsr.SCOMPARE1   \at1            // conditional store option
 182        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 24
 183        .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
 184        xchal_sa_align  \ptr, 0, 1000, 4, 4
 185        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 24
 186        .endif
 187    .endm       // xchal_ncp_load
 188
 189
 190#define XCHAL_NCP_NUM_ATMPS     1
 191
 192
 193
 194
 195    /*
 196     *  Macro to save the state of TIE coprocessor AudioEngineLX.
 197     *  Required parameters:
 198     *      ptr         Save area pointer address register (clobbered)
 199     *                  (register must contain a 8 byte aligned address).
 200     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
 201     *                  registers are clobbered, the remaining are unused).
 202     *  Optional parameters are the same as for xchal_ncp_store.
 203     */
 204#define xchal_cp_AudioEngineLX_store    xchal_cp1_store
 205    .macro      xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
 206        xchal_sa_start \continue, \ofs
 207        // Custom caller-saved registers not used by default by the compiler:
 208        .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
 209        xchal_sa_align  \ptr, 0, 0, 8, 8
 210        rur.AE_OVF_SAR  \at1            // ureg 240
 211        s32i    \at1, \ptr, .Lxchal_ofs_+0
 212        rur.AE_BITHEAD  \at1            // ureg 241
 213        s32i    \at1, \ptr, .Lxchal_ofs_+4
 214        rur.AE_TS_FTS_BU_BP     \at1            // ureg 242
 215        s32i    \at1, \ptr, .Lxchal_ofs_+8
 216        rur.AE_CW_SD_NO \at1            // ureg 243
 217        s32i    \at1, \ptr, .Lxchal_ofs_+12
 218        rur.AE_CBEGIN0  \at1            // ureg 246
 219        s32i    \at1, \ptr, .Lxchal_ofs_+16
 220        rur.AE_CEND0    \at1            // ureg 247
 221        s32i    \at1, \ptr, .Lxchal_ofs_+20
 222        AE_S64.I        aed0, \ptr, .Lxchal_ofs_+24
 223        AE_S64.I        aed1, \ptr, .Lxchal_ofs_+32
 224        AE_S64.I        aed2, \ptr, .Lxchal_ofs_+40
 225        AE_S64.I        aed3, \ptr, .Lxchal_ofs_+48
 226        AE_S64.I        aed4, \ptr, .Lxchal_ofs_+56
 227        addi    \ptr, \ptr, 64
 228        AE_S64.I        aed5, \ptr, .Lxchal_ofs_+0
 229        AE_S64.I        aed6, \ptr, .Lxchal_ofs_+8
 230        AE_S64.I        aed7, \ptr, .Lxchal_ofs_+16
 231        AE_S64.I        aed8, \ptr, .Lxchal_ofs_+24
 232        AE_S64.I        aed9, \ptr, .Lxchal_ofs_+32
 233        AE_S64.I        aed10, \ptr, .Lxchal_ofs_+40
 234        AE_S64.I        aed11, \ptr, .Lxchal_ofs_+48
 235        AE_S64.I        aed12, \ptr, .Lxchal_ofs_+56
 236        addi    \ptr, \ptr, 64
 237        AE_S64.I        aed13, \ptr, .Lxchal_ofs_+0
 238        AE_S64.I        aed14, \ptr, .Lxchal_ofs_+8
 239        AE_S64.I        aed15, \ptr, .Lxchal_ofs_+16
 240        AE_SALIGN64.I   u0, \ptr, .Lxchal_ofs_+24
 241        AE_SALIGN64.I   u1, \ptr, .Lxchal_ofs_+32
 242        AE_SALIGN64.I   u2, \ptr, .Lxchal_ofs_+40
 243        AE_SALIGN64.I   u3, \ptr, .Lxchal_ofs_+48
 244        .set    .Lxchal_pofs_, .Lxchal_pofs_ + 128
 245        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 56
 246        .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
 247        xchal_sa_align  \ptr, 0, 0, 8, 8
 248        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 184
 249        .endif
 250    .endm       // xchal_cp1_store
 251
 252    /*
 253     *  Macro to restore the state of TIE coprocessor AudioEngineLX.
 254     *  Required parameters:
 255     *      ptr         Save area pointer address register (clobbered)
 256     *                  (register must contain a 8 byte aligned address).
 257     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
 258     *                  registers are clobbered, the remaining are unused).
 259     *  Optional parameters are the same as for xchal_ncp_load.
 260     */
 261#define xchal_cp_AudioEngineLX_load     xchal_cp1_load
 262    .macro      xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
 263        xchal_sa_start \continue, \ofs
 264        // Custom caller-saved registers not used by default by the compiler:
 265        .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
 266        xchal_sa_align  \ptr, 0, 0, 8, 8
 267        l32i    \at1, \ptr, .Lxchal_ofs_+0
 268        wur.AE_OVF_SAR  \at1            // ureg 240
 269        l32i    \at1, \ptr, .Lxchal_ofs_+4
 270        wur.AE_BITHEAD  \at1            // ureg 241
 271        l32i    \at1, \ptr, .Lxchal_ofs_+8
 272        wur.AE_TS_FTS_BU_BP     \at1            // ureg 242
 273        l32i    \at1, \ptr, .Lxchal_ofs_+12
 274        wur.AE_CW_SD_NO \at1            // ureg 243
 275        l32i    \at1, \ptr, .Lxchal_ofs_+16
 276        wur.AE_CBEGIN0  \at1            // ureg 246
 277        l32i    \at1, \ptr, .Lxchal_ofs_+20
 278        wur.AE_CEND0    \at1            // ureg 247
 279        AE_L64.I        aed0, \ptr, .Lxchal_ofs_+24
 280        AE_L64.I        aed1, \ptr, .Lxchal_ofs_+32
 281        AE_L64.I        aed2, \ptr, .Lxchal_ofs_+40
 282        AE_L64.I        aed3, \ptr, .Lxchal_ofs_+48
 283        AE_L64.I        aed4, \ptr, .Lxchal_ofs_+56
 284        addi    \ptr, \ptr, 64
 285        AE_L64.I        aed5, \ptr, .Lxchal_ofs_+0
 286        AE_L64.I        aed6, \ptr, .Lxchal_ofs_+8
 287        AE_L64.I        aed7, \ptr, .Lxchal_ofs_+16
 288        AE_L64.I        aed8, \ptr, .Lxchal_ofs_+24
 289        AE_L64.I        aed9, \ptr, .Lxchal_ofs_+32
 290        AE_L64.I        aed10, \ptr, .Lxchal_ofs_+40
 291        AE_L64.I        aed11, \ptr, .Lxchal_ofs_+48
 292        AE_L64.I        aed12, \ptr, .Lxchal_ofs_+56
 293        addi    \ptr, \ptr, 64
 294        AE_L64.I        aed13, \ptr, .Lxchal_ofs_+0
 295        AE_L64.I        aed14, \ptr, .Lxchal_ofs_+8
 296        AE_L64.I        aed15, \ptr, .Lxchal_ofs_+16
 297        AE_LALIGN64.I   u0, \ptr, .Lxchal_ofs_+24
 298        AE_LALIGN64.I   u1, \ptr, .Lxchal_ofs_+32
 299        AE_LALIGN64.I   u2, \ptr, .Lxchal_ofs_+40
 300        AE_LALIGN64.I   u3, \ptr, .Lxchal_ofs_+48
 301        .set    .Lxchal_pofs_, .Lxchal_pofs_ + 128
 302        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 56
 303        .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
 304        xchal_sa_align  \ptr, 0, 0, 8, 8
 305        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 184
 306        .endif
 307    .endm       // xchal_cp1_load
 308
 309#define XCHAL_CP1_NUM_ATMPS     1
 310#define XCHAL_SA_NUM_ATMPS      1
 311
 312        /*  Empty macros for unconfigured coprocessors:  */
 313        .macro xchal_cp0_store  p a b c d continue=0 ofs=-1 select=-1 ; .endm
 314        .macro xchal_cp0_load   p a b c d continue=0 ofs=-1 select=-1 ; .endm
 315        .macro xchal_cp2_store  p a b c d continue=0 ofs=-1 select=-1 ; .endm
 316        .macro xchal_cp2_load   p a b c d continue=0 ofs=-1 select=-1 ; .endm
 317        .macro xchal_cp3_store  p a b c d continue=0 ofs=-1 select=-1 ; .endm
 318        .macro xchal_cp3_load   p a b c d continue=0 ofs=-1 select=-1 ; .endm
 319        .macro xchal_cp4_store  p a b c d continue=0 ofs=-1 select=-1 ; .endm
 320        .macro xchal_cp4_load   p a b c d continue=0 ofs=-1 select=-1 ; .endm
 321        .macro xchal_cp5_store  p a b c d continue=0 ofs=-1 select=-1 ; .endm
 322        .macro xchal_cp5_load   p a b c d continue=0 ofs=-1 select=-1 ; .endm
 323        .macro xchal_cp6_store  p a b c d continue=0 ofs=-1 select=-1 ; .endm
 324        .macro xchal_cp6_load   p a b c d continue=0 ofs=-1 select=-1 ; .endm
 325        .macro xchal_cp7_store  p a b c d continue=0 ofs=-1 select=-1 ; .endm
 326        .macro xchal_cp7_load   p a b c d continue=0 ofs=-1 select=-1 ; .endm
 327
 328#endif /*_XTENSA_CORE_TIE_ASM_H*/
 329