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19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/dmi.h>
28#include <linux/gfp.h>
29#include <linux/msi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_cmnd.h>
32#include <linux/libata.h>
33#include <linux/ahci-remap.h>
34#include <linux/io-64-nonatomic-lo-hi.h>
35#include "ahci.h"
36
37#define DRV_NAME "ahci"
38#define DRV_VERSION "3.0"
39
40enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47};
48
49enum board_ids {
50
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_mobile,
54 board_ahci_nomsi,
55 board_ahci_noncq,
56 board_ahci_nosntf,
57 board_ahci_yes_fbs,
58
59
60 board_ahci_al,
61 board_ahci_avn,
62 board_ahci_mcp65,
63 board_ahci_mcp77,
64 board_ahci_mcp89,
65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700,
68 board_ahci_vt8251,
69
70
71
72
73
74 board_ahci_pcs7,
75
76
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81};
82
83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84static void ahci_remove_one(struct pci_dev *dev);
85static void ahci_shutdown_one(struct pci_dev *dev);
86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91static bool is_mcp89_apple(struct pci_dev *pdev);
92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94#ifdef CONFIG_PM
95static int ahci_pci_device_runtime_suspend(struct device *dev);
96static int ahci_pci_device_runtime_resume(struct device *dev);
97#ifdef CONFIG_PM_SLEEP
98static int ahci_pci_device_suspend(struct device *dev);
99static int ahci_pci_device_resume(struct device *dev);
100#endif
101#endif
102
103static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105};
106
107static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_vt8251_hardreset,
110};
111
112static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
114 .hardreset = ahci_p5wdh_hardreset,
115};
116
117static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120};
121
122static const struct ata_port_info ahci_port_info[] = {
123
124 [board_ahci] = {
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
129 },
130 [board_ahci_ign_iferr] = {
131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_nosntf] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_yes_fbs] = {
166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172
173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = {
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
245};
246
247static const struct pci_device_id ahci_pci_tbl[] = {
248
249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci },
250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci },
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci },
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci },
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci },
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci },
255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr },
256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci },
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci },
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci },
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci },
260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci },
261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf },
262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci },
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci },
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci },
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci },
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci },
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci },
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci },
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci },
270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile },
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile },
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile },
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile },
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile },
275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci },
276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile },
277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci },
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci },
279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci },
280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci },
281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci },
282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci },
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci },
284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci },
285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci },
286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile },
287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci },
288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile },
289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci },
290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 },
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 },
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 },
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 },
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 },
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 },
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 },
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 },
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 },
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 },
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 },
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 },
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 },
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 },
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 },
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 },
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 },
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 },
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 },
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 },
310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci },
311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile },
312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci },
313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile },
314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci },
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci },
316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci },
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci },
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci },
319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci },
320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci },
321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci },
322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile },
323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci },
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci },
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci },
326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile },
327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci },
328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci },
329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile },
330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci },
331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile },
332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci },
333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile },
334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci },
335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile },
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile },
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile },
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile },
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile },
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile },
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile },
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile },
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile },
344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile },
345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci },
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci },
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci },
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci },
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci },
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci },
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci },
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci },
353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn },
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn },
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn },
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn },
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn },
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn },
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn },
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn },
361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci },
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci },
363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci },
364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci },
365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci },
366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci },
367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci },
368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci },
369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci },
370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci },
371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci },
372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci },
373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci },
374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci },
375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci },
376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile },
377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile },
378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile },
379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile },
380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci },
381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile },
382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci },
383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile },
384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci },
385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile },
386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci },
387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile },
388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile },
389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile },
390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile },
391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci },
392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile },
393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci },
394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci },
395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile },
396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci },
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci },
398 { PCI_VDEVICE(INTEL, 0x2823), board_ahci },
399 { PCI_VDEVICE(INTEL, 0x2826), board_ahci },
400 { PCI_VDEVICE(INTEL, 0x2827), board_ahci },
401 { PCI_VDEVICE(INTEL, 0xa182), board_ahci },
402 { PCI_VDEVICE(INTEL, 0xa186), board_ahci },
403 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci },
404 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci },
405 { PCI_VDEVICE(INTEL, 0xa202), board_ahci },
406 { PCI_VDEVICE(INTEL, 0xa206), board_ahci },
407 { PCI_VDEVICE(INTEL, 0xa252), board_ahci },
408 { PCI_VDEVICE(INTEL, 0xa256), board_ahci },
409 { PCI_VDEVICE(INTEL, 0xa356), board_ahci },
410 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci },
411 { PCI_VDEVICE(INTEL, 0xa386), board_ahci },
412 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile },
413 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile },
414 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile },
415 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile },
416 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile },
417 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile },
418 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile },
419
420
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
423
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
426
427
428
429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 },
430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 },
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 },
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 },
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 },
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 },
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 },
436
437
438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
439 .class = PCI_CLASS_STORAGE_SATA_AHCI,
440 .class_mask = 0xffffff,
441 board_ahci_al },
442
443 { PCI_VDEVICE(AMD, 0x7800), board_ahci },
444 { PCI_VDEVICE(AMD, 0x7900), board_ahci },
445
446 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
447 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
448
449
450 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
451 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
452
453
454 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 },
455 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 },
456
457
458 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },
459 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },
460 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },
461 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },
462 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },
463 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },
464 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },
465 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },
466 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },
467 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },
468 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },
469 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },
470 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },
471 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },
472 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },
473 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },
474 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },
475 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },
476 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },
477 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },
478 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },
479 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },
480 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },
481 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },
482 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },
483 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },
484 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },
485 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },
486 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },
487 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },
488 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },
489 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },
490 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },
491 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },
492 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },
493 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },
494 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },
495 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },
496 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },
497 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },
498 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },
499 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },
500 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },
501 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },
502 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },
503 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },
504 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },
505 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },
506 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },
507 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },
508 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },
509 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },
510 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },
511 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },
512 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },
513 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },
514 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },
515 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },
516 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },
517 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },
518 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },
519 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },
520 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },
521 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },
522 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },
523 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },
524 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },
525 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },
526 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },
527 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },
528 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },
529 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },
530 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },
531 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },
532 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },
533 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },
534 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },
535 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },
536 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },
537 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },
538 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },
539 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },
540 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },
541 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },
542
543
544 { PCI_VDEVICE(SI, 0x1184), board_ahci },
545 { PCI_VDEVICE(SI, 0x1185), board_ahci },
546 { PCI_VDEVICE(SI, 0x0186), board_ahci },
547
548
549 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },
550
551
552 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },
553 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },
554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
555 .class = PCI_CLASS_STORAGE_SATA_AHCI,
556 .class_mask = 0xffffff,
557 .driver_data = board_ahci_yes_fbs },
558 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
559 .driver_data = board_ahci_yes_fbs },
560 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
561 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
562 .driver_data = board_ahci_yes_fbs },
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
564 .driver_data = board_ahci_yes_fbs },
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
566 .driver_data = board_ahci_yes_fbs },
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
568 .driver_data = board_ahci_yes_fbs },
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
570 .driver_data = board_ahci_yes_fbs },
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
572 .driver_data = board_ahci_yes_fbs },
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),
574 .driver_data = board_ahci_yes_fbs },
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
576 .driver_data = board_ahci_yes_fbs },
577 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
578 .driver_data = board_ahci_yes_fbs },
579 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
580 .driver_data = board_ahci_yes_fbs },
581 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645),
582 .driver_data = board_ahci_yes_fbs },
583
584
585 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },
586 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },
587
588
589 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },
590 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },
591 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },
592 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },
593 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },
594 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },
595
596
597
598
599
600 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
601 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
602
603
604 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
605
606
607 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
608
609
610 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
611 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
612
613 { }
614};
615
616static const struct dev_pm_ops ahci_pci_pm_ops = {
617 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
618 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
619 ahci_pci_device_runtime_resume, NULL)
620};
621
622static struct pci_driver ahci_pci_driver = {
623 .name = DRV_NAME,
624 .id_table = ahci_pci_tbl,
625 .probe = ahci_init_one,
626 .remove = ahci_remove_one,
627 .shutdown = ahci_shutdown_one,
628 .driver = {
629 .pm = &ahci_pci_pm_ops,
630 },
631};
632
633#if IS_ENABLED(CONFIG_PATA_MARVELL)
634static int marvell_enable;
635#else
636static int marvell_enable = 1;
637#endif
638module_param(marvell_enable, int, 0644);
639MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
640
641static int mobile_lpm_policy = -1;
642module_param(mobile_lpm_policy, int, 0644);
643MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
644
645static void ahci_pci_save_initial_config(struct pci_dev *pdev,
646 struct ahci_host_priv *hpriv)
647{
648 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
649 dev_info(&pdev->dev, "JMB361 has only one port\n");
650 hpriv->force_port_map = 1;
651 }
652
653
654
655
656
657
658 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
659 if (pdev->device == 0x6121)
660 hpriv->mask_port_map = 0x3;
661 else
662 hpriv->mask_port_map = 0xf;
663 dev_info(&pdev->dev,
664 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
665 }
666
667 ahci_save_initial_config(&pdev->dev, hpriv);
668}
669
670static void ahci_pci_init_controller(struct ata_host *host)
671{
672 struct ahci_host_priv *hpriv = host->private_data;
673 struct pci_dev *pdev = to_pci_dev(host->dev);
674 void __iomem *port_mmio;
675 u32 tmp;
676 int mv;
677
678 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
679 if (pdev->device == 0x6121)
680 mv = 2;
681 else
682 mv = 4;
683 port_mmio = __ahci_port_base(host, mv);
684
685 writel(0, port_mmio + PORT_IRQ_MASK);
686
687
688 tmp = readl(port_mmio + PORT_IRQ_STAT);
689 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
690 if (tmp)
691 writel(tmp, port_mmio + PORT_IRQ_STAT);
692 }
693
694 ahci_init_controller(host);
695}
696
697static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
698 unsigned long deadline)
699{
700 struct ata_port *ap = link->ap;
701 struct ahci_host_priv *hpriv = ap->host->private_data;
702 bool online;
703 int rc;
704
705 DPRINTK("ENTER\n");
706
707 hpriv->stop_engine(ap);
708
709 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
710 deadline, &online, NULL);
711
712 hpriv->start_engine(ap);
713
714 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
715
716
717
718
719 return online ? -EAGAIN : rc;
720}
721
722static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
723 unsigned long deadline)
724{
725 struct ata_port *ap = link->ap;
726 struct ahci_port_priv *pp = ap->private_data;
727 struct ahci_host_priv *hpriv = ap->host->private_data;
728 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
729 struct ata_taskfile tf;
730 bool online;
731 int rc;
732
733 hpriv->stop_engine(ap);
734
735
736 ata_tf_init(link->device, &tf);
737 tf.command = ATA_BUSY;
738 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
739
740 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
741 deadline, &online, NULL);
742
743 hpriv->start_engine(ap);
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758 if (online) {
759 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
760 ahci_check_ready);
761 if (rc)
762 ahci_kick_engine(ap);
763 }
764 return rc;
765}
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
783 unsigned long deadline)
784{
785 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
786 struct ata_port *ap = link->ap;
787 struct ahci_port_priv *pp = ap->private_data;
788 struct ahci_host_priv *hpriv = ap->host->private_data;
789 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
790 unsigned long tmo = deadline - jiffies;
791 struct ata_taskfile tf;
792 bool online;
793 int rc, i;
794
795 DPRINTK("ENTER\n");
796
797 hpriv->stop_engine(ap);
798
799 for (i = 0; i < 2; i++) {
800 u16 val;
801 u32 sstatus;
802 int port = ap->port_no;
803 struct ata_host *host = ap->host;
804 struct pci_dev *pdev = to_pci_dev(host->dev);
805
806
807 ata_tf_init(link->device, &tf);
808 tf.command = ATA_BUSY;
809 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
810
811 rc = sata_link_hardreset(link, timing, deadline, &online,
812 ahci_check_ready);
813
814 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
815 (sstatus & 0xf) != 1)
816 break;
817
818 ata_link_info(link, "avn bounce port%d\n", port);
819
820 pci_read_config_word(pdev, 0x92, &val);
821 val &= ~(1 << port);
822 pci_write_config_word(pdev, 0x92, val);
823 ata_msleep(ap, 1000);
824 val |= 1 << port;
825 pci_write_config_word(pdev, 0x92, val);
826 deadline += tmo;
827 }
828
829 hpriv->start_engine(ap);
830
831 if (online)
832 *class = ahci_dev_classify(ap);
833
834 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
835 return rc;
836}
837
838
839#ifdef CONFIG_PM
840static void ahci_pci_disable_interrupts(struct ata_host *host)
841{
842 struct ahci_host_priv *hpriv = host->private_data;
843 void __iomem *mmio = hpriv->mmio;
844 u32 ctl;
845
846
847
848
849
850 ctl = readl(mmio + HOST_CTL);
851 ctl &= ~HOST_IRQ_EN;
852 writel(ctl, mmio + HOST_CTL);
853 readl(mmio + HOST_CTL);
854}
855
856static int ahci_pci_device_runtime_suspend(struct device *dev)
857{
858 struct pci_dev *pdev = to_pci_dev(dev);
859 struct ata_host *host = pci_get_drvdata(pdev);
860
861 ahci_pci_disable_interrupts(host);
862 return 0;
863}
864
865static int ahci_pci_device_runtime_resume(struct device *dev)
866{
867 struct pci_dev *pdev = to_pci_dev(dev);
868 struct ata_host *host = pci_get_drvdata(pdev);
869 int rc;
870
871 rc = ahci_reset_controller(host);
872 if (rc)
873 return rc;
874 ahci_pci_init_controller(host);
875 return 0;
876}
877
878#ifdef CONFIG_PM_SLEEP
879static int ahci_pci_device_suspend(struct device *dev)
880{
881 struct pci_dev *pdev = to_pci_dev(dev);
882 struct ata_host *host = pci_get_drvdata(pdev);
883 struct ahci_host_priv *hpriv = host->private_data;
884
885 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
886 dev_err(&pdev->dev,
887 "BIOS update required for suspend/resume\n");
888 return -EIO;
889 }
890
891 ahci_pci_disable_interrupts(host);
892 return ata_host_suspend(host, PMSG_SUSPEND);
893}
894
895static int ahci_pci_device_resume(struct device *dev)
896{
897 struct pci_dev *pdev = to_pci_dev(dev);
898 struct ata_host *host = pci_get_drvdata(pdev);
899 int rc;
900
901
902 if (is_mcp89_apple(pdev))
903 ahci_mcp89_apple_enable(pdev);
904
905 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
906 rc = ahci_reset_controller(host);
907 if (rc)
908 return rc;
909
910 ahci_pci_init_controller(host);
911 }
912
913 ata_host_resume(host);
914
915 return 0;
916}
917#endif
918
919#endif
920
921static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
922{
923 const int dma_bits = using_dac ? 64 : 32;
924 int rc;
925
926
927
928
929
930
931
932
933 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
934 return 0;
935
936 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
937 if (rc)
938 dev_err(&pdev->dev, "DMA enable failed\n");
939 return rc;
940}
941
942static void ahci_pci_print_info(struct ata_host *host)
943{
944 struct pci_dev *pdev = to_pci_dev(host->dev);
945 u16 cc;
946 const char *scc_s;
947
948 pci_read_config_word(pdev, 0x0a, &cc);
949 if (cc == PCI_CLASS_STORAGE_IDE)
950 scc_s = "IDE";
951 else if (cc == PCI_CLASS_STORAGE_SATA)
952 scc_s = "SATA";
953 else if (cc == PCI_CLASS_STORAGE_RAID)
954 scc_s = "RAID";
955 else
956 scc_s = "unknown";
957
958 ahci_print_info(host, scc_s);
959}
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979static void ahci_p5wdh_workaround(struct ata_host *host)
980{
981 static const struct dmi_system_id sysids[] = {
982 {
983 .ident = "P5W DH Deluxe",
984 .matches = {
985 DMI_MATCH(DMI_SYS_VENDOR,
986 "ASUSTEK COMPUTER INC"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
988 },
989 },
990 { }
991 };
992 struct pci_dev *pdev = to_pci_dev(host->dev);
993
994 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
995 dmi_check_system(sysids)) {
996 struct ata_port *ap = host->ports[1];
997
998 dev_info(&pdev->dev,
999 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1000
1001 ap->ops = &ahci_p5wdh_ops;
1002 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1003 }
1004}
1005
1006
1007
1008
1009
1010static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1011{
1012 u32 val;
1013
1014 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1015
1016 pci_read_config_dword(pdev, 0xf8, &val);
1017 val |= 1 << 0x1b;
1018
1019
1020 pci_write_config_dword(pdev, 0xf8, val);
1021
1022 pci_read_config_dword(pdev, 0x54c, &val);
1023 val |= 1 << 0xc;
1024 pci_write_config_dword(pdev, 0x54c, val);
1025
1026 pci_read_config_dword(pdev, 0x4a4, &val);
1027 val &= 0xff;
1028 val |= 0x01060100;
1029 pci_write_config_dword(pdev, 0x4a4, val);
1030
1031 pci_read_config_dword(pdev, 0x54c, &val);
1032 val &= ~(1 << 0xc);
1033 pci_write_config_dword(pdev, 0x54c, val);
1034
1035 pci_read_config_dword(pdev, 0xf8, &val);
1036 val &= ~(1 << 0x1b);
1037 pci_write_config_dword(pdev, 0xf8, val);
1038}
1039
1040static bool is_mcp89_apple(struct pci_dev *pdev)
1041{
1042 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1043 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1044 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1045 pdev->subsystem_device == 0xcb89;
1046}
1047
1048
1049static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1050{
1051 static const struct dmi_system_id sysids[] = {
1052
1053
1054
1055
1056
1057
1058
1059 {
1060 .ident = "ASUS M2A-VM",
1061 .matches = {
1062 DMI_MATCH(DMI_BOARD_VENDOR,
1063 "ASUSTeK Computer INC."),
1064 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1065 },
1066 .driver_data = "20071026",
1067 },
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084 {
1085 .ident = "MSI K9A2 Platinum",
1086 .matches = {
1087 DMI_MATCH(DMI_BOARD_VENDOR,
1088 "MICRO-STAR INTER"),
1089 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1090 },
1091 },
1092
1093
1094
1095
1096
1097
1098
1099
1100 {
1101 .ident = "MSI K9AGM2",
1102 .matches = {
1103 DMI_MATCH(DMI_BOARD_VENDOR,
1104 "MICRO-STAR INTER"),
1105 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1106 },
1107 },
1108
1109
1110
1111
1112 {
1113 .ident = "ASUS M3A",
1114 .matches = {
1115 DMI_MATCH(DMI_BOARD_VENDOR,
1116 "ASUSTeK Computer INC."),
1117 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1118 },
1119 },
1120 { }
1121 };
1122 const struct dmi_system_id *match;
1123 int year, month, date;
1124 char buf[9];
1125
1126 match = dmi_first_match(sysids);
1127 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1128 !match)
1129 return false;
1130
1131 if (!match->driver_data)
1132 goto enable_64bit;
1133
1134 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1135 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1136
1137 if (strcmp(buf, match->driver_data) >= 0)
1138 goto enable_64bit;
1139 else {
1140 dev_warn(&pdev->dev,
1141 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1142 match->ident);
1143 return false;
1144 }
1145
1146enable_64bit:
1147 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1148 return true;
1149}
1150
1151static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1152{
1153 static const struct dmi_system_id broken_systems[] = {
1154 {
1155 .ident = "HP Compaq nx6310",
1156 .matches = {
1157 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1158 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1159 },
1160
1161 .driver_data = (void *)0x1FUL,
1162 },
1163 {
1164 .ident = "HP Compaq 6720s",
1165 .matches = {
1166 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1167 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1168 },
1169
1170 .driver_data = (void *)0x1FUL,
1171 },
1172
1173 { }
1174 };
1175 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1176
1177 if (dmi) {
1178 unsigned long slot = (unsigned long)dmi->driver_data;
1179
1180 return slot == PCI_SLOT(pdev->devfn);
1181 }
1182
1183 return false;
1184}
1185
1186static bool ahci_broken_suspend(struct pci_dev *pdev)
1187{
1188 static const struct dmi_system_id sysids[] = {
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202 {
1203 .ident = "dv4",
1204 .matches = {
1205 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1206 DMI_MATCH(DMI_PRODUCT_NAME,
1207 "HP Pavilion dv4 Notebook PC"),
1208 },
1209 .driver_data = "20090105",
1210 },
1211 {
1212 .ident = "dv5",
1213 .matches = {
1214 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1215 DMI_MATCH(DMI_PRODUCT_NAME,
1216 "HP Pavilion dv5 Notebook PC"),
1217 },
1218 .driver_data = "20090506",
1219 },
1220 {
1221 .ident = "dv6",
1222 .matches = {
1223 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1224 DMI_MATCH(DMI_PRODUCT_NAME,
1225 "HP Pavilion dv6 Notebook PC"),
1226 },
1227 .driver_data = "20090423",
1228 },
1229 {
1230 .ident = "HDX18",
1231 .matches = {
1232 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1233 DMI_MATCH(DMI_PRODUCT_NAME,
1234 "HP HDX18 Notebook PC"),
1235 },
1236 .driver_data = "20090430",
1237 },
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247 {
1248 .ident = "G725",
1249 .matches = {
1250 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1251 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1252 },
1253 .driver_data = "20091216",
1254 },
1255 { }
1256 };
1257 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1258 int year, month, date;
1259 char buf[9];
1260
1261 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1262 return false;
1263
1264 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1265 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1266
1267 return strcmp(buf, dmi->driver_data) < 0;
1268}
1269
1270static bool ahci_broken_lpm(struct pci_dev *pdev)
1271{
1272 static const struct dmi_system_id sysids[] = {
1273
1274 {
1275 .matches = {
1276 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1277 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1278 },
1279 .driver_data = "20180406",
1280 },
1281 {
1282 .matches = {
1283 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1284 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1285 },
1286 .driver_data = "20180420",
1287 },
1288 {
1289 .matches = {
1290 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1291 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1292 },
1293 .driver_data = "20180315",
1294 },
1295 {
1296 .matches = {
1297 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1298 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1299 },
1300
1301
1302
1303
1304
1305
1306 .driver_data = "20180310",
1307 },
1308 { }
1309 };
1310 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311 int year, month, date;
1312 char buf[9];
1313
1314 if (!dmi)
1315 return false;
1316
1317 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1318 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1319
1320 return strcmp(buf, dmi->driver_data) < 0;
1321}
1322
1323static bool ahci_broken_online(struct pci_dev *pdev)
1324{
1325#define ENCODE_BUSDEVFN(bus, slot, func) \
1326 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1327 static const struct dmi_system_id sysids[] = {
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341 {
1342 .ident = "EP45-DQ6",
1343 .matches = {
1344 DMI_MATCH(DMI_BOARD_VENDOR,
1345 "Gigabyte Technology Co., Ltd."),
1346 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1347 },
1348 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1349 },
1350 {
1351 .ident = "EP45-DS5",
1352 .matches = {
1353 DMI_MATCH(DMI_BOARD_VENDOR,
1354 "Gigabyte Technology Co., Ltd."),
1355 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1356 },
1357 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1358 },
1359 { }
1360 };
1361#undef ENCODE_BUSDEVFN
1362 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1363 unsigned int val;
1364
1365 if (!dmi)
1366 return false;
1367
1368 val = (unsigned long)dmi->driver_data;
1369
1370 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1371}
1372
1373static bool ahci_broken_devslp(struct pci_dev *pdev)
1374{
1375
1376 static const struct pci_device_id ids[] = {
1377 { PCI_VDEVICE(INTEL, 0x0f23)},
1378 {}
1379 };
1380
1381 return pci_match_id(ids, pdev);
1382}
1383
1384#ifdef CONFIG_ATA_ACPI
1385static void ahci_gtf_filter_workaround(struct ata_host *host)
1386{
1387 static const struct dmi_system_id sysids[] = {
1388
1389
1390
1391
1392
1393
1394
1395
1396 {
1397 .ident = "Aspire 3810T",
1398 .matches = {
1399 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1400 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1401 },
1402 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1403 },
1404 { }
1405 };
1406 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1407 unsigned int filter;
1408 int i;
1409
1410 if (!dmi)
1411 return;
1412
1413 filter = (unsigned long)dmi->driver_data;
1414 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1415 filter, dmi->ident);
1416
1417 for (i = 0; i < host->n_ports; i++) {
1418 struct ata_port *ap = host->ports[i];
1419 struct ata_link *link;
1420 struct ata_device *dev;
1421
1422 ata_for_each_link(link, ap, EDGE)
1423 ata_for_each_dev(dev, link, ALL)
1424 dev->gtf_filter |= filter;
1425 }
1426}
1427#else
1428static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1429{}
1430#endif
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1444 struct pci_dev *pdev)
1445{
1446 static const struct dmi_system_id sysids[] = {
1447 {
1448 .ident = "Acer Switch Alpha 12",
1449 .matches = {
1450 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1451 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1452 },
1453 },
1454 { }
1455 };
1456
1457 if (dmi_check_system(sysids)) {
1458 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1459 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1460 hpriv->port_map = 0x7;
1461 hpriv->cap = 0xC734FF02;
1462 }
1463 }
1464}
1465
1466#ifdef CONFIG_ARM64
1467
1468
1469
1470
1471
1472static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1473{
1474 struct ata_host *host = dev_instance;
1475 struct ahci_host_priv *hpriv;
1476 unsigned int rc = 0;
1477 void __iomem *mmio;
1478 u32 irq_stat, irq_masked;
1479 unsigned int handled = 1;
1480
1481 VPRINTK("ENTER\n");
1482 hpriv = host->private_data;
1483 mmio = hpriv->mmio;
1484 irq_stat = readl(mmio + HOST_IRQ_STAT);
1485 if (!irq_stat)
1486 return IRQ_NONE;
1487
1488 do {
1489 irq_masked = irq_stat & hpriv->port_map;
1490 spin_lock(&host->lock);
1491 rc = ahci_handle_port_intr(host, irq_masked);
1492 if (!rc)
1493 handled = 0;
1494 writel(irq_stat, mmio + HOST_IRQ_STAT);
1495 irq_stat = readl(mmio + HOST_IRQ_STAT);
1496 spin_unlock(&host->lock);
1497 } while (irq_stat);
1498 VPRINTK("EXIT\n");
1499
1500 return IRQ_RETVAL(handled);
1501}
1502#endif
1503
1504static void ahci_remap_check(struct pci_dev *pdev, int bar,
1505 struct ahci_host_priv *hpriv)
1506{
1507 int i;
1508 u32 cap;
1509
1510
1511
1512
1513 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1514 pci_resource_len(pdev, bar) < SZ_512K ||
1515 bar != AHCI_PCI_BAR_STANDARD ||
1516 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1517 return;
1518
1519 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1520 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1521 if ((cap & (1 << i)) == 0)
1522 continue;
1523 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1524 != PCI_CLASS_STORAGE_EXPRESS)
1525 continue;
1526
1527
1528 hpriv->remapped_nvme++;
1529 }
1530
1531 if (!hpriv->remapped_nvme)
1532 return;
1533
1534 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1535 hpriv->remapped_nvme);
1536 dev_warn(&pdev->dev,
1537 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1538
1539
1540
1541
1542
1543 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1544}
1545
1546static int ahci_get_irq_vector(struct ata_host *host, int port)
1547{
1548 return pci_irq_vector(to_pci_dev(host->dev), port);
1549}
1550
1551static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1552 struct ahci_host_priv *hpriv)
1553{
1554 int nvec;
1555
1556 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1557 return -ENODEV;
1558
1559
1560
1561
1562
1563
1564 if (n_ports > 1) {
1565 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1566 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1567 if (nvec > 0) {
1568 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1569 hpriv->get_irq_vector = ahci_get_irq_vector;
1570 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1571 return nvec;
1572 }
1573
1574
1575
1576
1577
1578 printk(KERN_INFO
1579 "ahci: MRSM is on, fallback to single MSI\n");
1580 pci_free_irq_vectors(pdev);
1581 }
1582 }
1583
1584
1585
1586
1587
1588 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1589 if (nvec == 1)
1590 return nvec;
1591 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1592}
1593
1594static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1595 struct ahci_host_priv *hpriv)
1596{
1597 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1598
1599
1600
1601 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1602 return;
1603
1604
1605 if (mobile_lpm_policy != -1) {
1606 policy = mobile_lpm_policy;
1607 goto update_policy;
1608 }
1609
1610#ifdef CONFIG_ACPI
1611 if (policy > ATA_LPM_MED_POWER &&
1612 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1613 if (hpriv->cap & HOST_CAP_PART)
1614 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1615 else if (hpriv->cap & HOST_CAP_SSC)
1616 policy = ATA_LPM_MIN_POWER;
1617 }
1618#endif
1619
1620update_policy:
1621 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1622 ap->target_lpm_policy = policy;
1623}
1624
1625static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1626{
1627 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1628 u16 tmp16;
1629
1630
1631
1632
1633 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1634 return;
1635
1636
1637 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1638 return;
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648 pci_read_config_word(pdev, PCS_6, &tmp16);
1649 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1650 tmp16 |= hpriv->port_map;
1651 pci_write_config_word(pdev, PCS_6, tmp16);
1652 }
1653}
1654
1655static ssize_t remapped_nvme_show(struct device *dev,
1656 struct device_attribute *attr,
1657 char *buf)
1658{
1659 struct ata_host *host = dev_get_drvdata(dev);
1660 struct ahci_host_priv *hpriv = host->private_data;
1661
1662 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1663}
1664
1665static DEVICE_ATTR_RO(remapped_nvme);
1666
1667static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1668{
1669 unsigned int board_id = ent->driver_data;
1670 struct ata_port_info pi = ahci_port_info[board_id];
1671 const struct ata_port_info *ppi[] = { &pi, NULL };
1672 struct device *dev = &pdev->dev;
1673 struct ahci_host_priv *hpriv;
1674 struct ata_host *host;
1675 int n_ports, i, rc;
1676 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1677
1678 VPRINTK("ENTER\n");
1679
1680 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1681
1682 ata_print_version_once(&pdev->dev, DRV_VERSION);
1683
1684
1685
1686
1687 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1688 return -ENODEV;
1689
1690
1691 if (is_mcp89_apple(pdev))
1692 ahci_mcp89_apple_enable(pdev);
1693
1694
1695
1696
1697
1698 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1699 dev_info(&pdev->dev,
1700 "PDC42819 can only drive SATA devices with this driver\n");
1701
1702
1703 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1704 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1705 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1706 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1707 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1708 if (pdev->device == 0xa01c)
1709 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1710 if (pdev->device == 0xa084)
1711 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1712 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1713 if (pdev->device == 0x7a08)
1714 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1715 }
1716
1717
1718 rc = pcim_enable_device(pdev);
1719 if (rc)
1720 return rc;
1721
1722 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1723 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1724 u8 map;
1725
1726
1727
1728
1729
1730 pci_read_config_byte(pdev, ICH_MAP, &map);
1731 if (map & 0x3) {
1732 dev_info(&pdev->dev,
1733 "controller is in combined mode, can't enable AHCI mode\n");
1734 return -ENODEV;
1735 }
1736 }
1737
1738
1739
1740
1741 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1742 if (rc == -EBUSY)
1743 pcim_pin_device(pdev);
1744 if (rc)
1745 return rc;
1746
1747 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1748 if (!hpriv)
1749 return -ENOMEM;
1750 hpriv->flags |= (unsigned long)pi.private_data;
1751
1752
1753 if (board_id == board_ahci_mcp65 &&
1754 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1755 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1756
1757
1758 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1759 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1760
1761
1762 if (ahci_sb600_enable_64bit(pdev))
1763 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1764
1765 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1766
1767
1768 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1769
1770 sysfs_add_file_to_group(&pdev->dev.kobj,
1771 &dev_attr_remapped_nvme.attr,
1772 NULL);
1773
1774
1775 if (ahci_broken_devslp(pdev))
1776 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1777
1778#ifdef CONFIG_ARM64
1779 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1780 pdev->device == 0xa235 &&
1781 pdev->revision < 0x30)
1782 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1783
1784 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1785 hpriv->irq_handler = ahci_thunderx_irq_handler;
1786#endif
1787
1788
1789 ahci_pci_save_initial_config(pdev, hpriv);
1790
1791
1792
1793
1794
1795 ahci_intel_pcs_quirk(pdev, hpriv);
1796
1797
1798 if (hpriv->cap & HOST_CAP_NCQ) {
1799 pi.flags |= ATA_FLAG_NCQ;
1800
1801
1802
1803
1804
1805
1806 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1807 pi.flags |= ATA_FLAG_FPDMA_AA;
1808
1809
1810
1811
1812
1813
1814
1815 pi.flags |= ATA_FLAG_FPDMA_AUX;
1816 }
1817
1818 if (hpriv->cap & HOST_CAP_PMP)
1819 pi.flags |= ATA_FLAG_PMP;
1820
1821 ahci_set_em_messages(hpriv, &pi);
1822
1823 if (ahci_broken_system_poweroff(pdev)) {
1824 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1825 dev_info(&pdev->dev,
1826 "quirky BIOS, skipping spindown on poweroff\n");
1827 }
1828
1829 if (ahci_broken_lpm(pdev)) {
1830 pi.flags |= ATA_FLAG_NO_LPM;
1831 dev_warn(&pdev->dev,
1832 "BIOS update required for Link Power Management support\n");
1833 }
1834
1835 if (ahci_broken_suspend(pdev)) {
1836 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1837 dev_warn(&pdev->dev,
1838 "BIOS update required for suspend/resume\n");
1839 }
1840
1841 if (ahci_broken_online(pdev)) {
1842 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1843 dev_info(&pdev->dev,
1844 "online status unreliable, applying workaround\n");
1845 }
1846
1847
1848
1849 acer_sa5_271_workaround(hpriv, pdev);
1850
1851
1852
1853
1854
1855
1856 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1857
1858 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1859 if (!host)
1860 return -ENOMEM;
1861 host->private_data = hpriv;
1862
1863 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1864
1865 pci_intx(pdev, 1);
1866 }
1867 hpriv->irq = pci_irq_vector(pdev, 0);
1868
1869 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1870 host->flags |= ATA_HOST_PARALLEL_SCAN;
1871 else
1872 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1873
1874 if (pi.flags & ATA_FLAG_EM)
1875 ahci_reset_em(host);
1876
1877 for (i = 0; i < host->n_ports; i++) {
1878 struct ata_port *ap = host->ports[i];
1879
1880 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1881 ata_port_pbar_desc(ap, ahci_pci_bar,
1882 0x100 + ap->port_no * 0x80, "port");
1883
1884
1885 if (ap->flags & ATA_FLAG_EM)
1886 ap->em_message_type = hpriv->em_msg_type;
1887
1888 ahci_update_initial_lpm_policy(ap, hpriv);
1889
1890
1891 if (!(hpriv->port_map & (1 << i)))
1892 ap->ops = &ata_dummy_port_ops;
1893 }
1894
1895
1896 ahci_p5wdh_workaround(host);
1897
1898
1899 ahci_gtf_filter_workaround(host);
1900
1901
1902 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1903 if (rc)
1904 return rc;
1905
1906 rc = ahci_reset_controller(host);
1907 if (rc)
1908 return rc;
1909
1910 ahci_pci_init_controller(host);
1911 ahci_pci_print_info(host);
1912
1913 pci_set_master(pdev);
1914
1915 rc = ahci_host_activate(host, &ahci_sht);
1916 if (rc)
1917 return rc;
1918
1919 pm_runtime_put_noidle(&pdev->dev);
1920 return 0;
1921}
1922
1923static void ahci_shutdown_one(struct pci_dev *pdev)
1924{
1925 ata_pci_shutdown_one(pdev);
1926}
1927
1928static void ahci_remove_one(struct pci_dev *pdev)
1929{
1930 sysfs_remove_file_from_group(&pdev->dev.kobj,
1931 &dev_attr_remapped_nvme.attr,
1932 NULL);
1933 pm_runtime_get_noresume(&pdev->dev);
1934 ata_pci_remove_one(pdev);
1935}
1936
1937module_pci_driver(ahci_pci_driver);
1938
1939MODULE_AUTHOR("Jeff Garzik");
1940MODULE_DESCRIPTION("AHCI SATA low-level driver");
1941MODULE_LICENSE("GPL");
1942MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1943MODULE_VERSION(DRV_VERSION);
1944