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19#ifndef _AHCI_H
20#define _AHCI_H
21
22#include <linux/pci.h>
23#include <linux/clk.h>
24#include <linux/libata.h>
25#include <linux/phy/phy.h>
26#include <linux/regulator/consumer.h>
27
28
29#define EM_CTRL_MSG_TYPE 0x000f0000
30
31
32#define EM_MSG_LED_HBA_PORT 0x0000000f
33#define EM_MSG_LED_PMP_SLOT 0x0000ff00
34#define EM_MSG_LED_VALUE 0xffff0000
35#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
36#define EM_MSG_LED_VALUE_OFF 0xfff80000
37#define EM_MSG_LED_VALUE_ON 0x00010000
38
39enum {
40 AHCI_MAX_PORTS = 32,
41 AHCI_MAX_CLKS = 5,
42 AHCI_MAX_SG = 168,
43 AHCI_DMA_BOUNDARY = 0xffffffff,
44 AHCI_MAX_CMDS = 32,
45 AHCI_CMD_SZ = 32,
46 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
47 AHCI_RX_FIS_SZ = 256,
48 AHCI_CMD_TBL_CDB = 0x40,
49 AHCI_CMD_TBL_HDR_SZ = 0x80,
50 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
51 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
52 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
53 AHCI_RX_FIS_SZ,
54 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
55 AHCI_CMD_TBL_AR_SZ +
56 (AHCI_RX_FIS_SZ * 16),
57 AHCI_IRQ_ON_SG = (1 << 31),
58 AHCI_CMD_ATAPI = (1 << 5),
59 AHCI_CMD_WRITE = (1 << 6),
60 AHCI_CMD_PREFETCH = (1 << 7),
61 AHCI_CMD_RESET = (1 << 8),
62 AHCI_CMD_CLR_BUSY = (1 << 10),
63
64 RX_FIS_PIO_SETUP = 0x20,
65 RX_FIS_D2H_REG = 0x40,
66 RX_FIS_SDB = 0x58,
67 RX_FIS_UNK = 0x60,
68
69
70 HOST_CAP = 0x00,
71 HOST_CTL = 0x04,
72 HOST_IRQ_STAT = 0x08,
73 HOST_PORTS_IMPL = 0x0c,
74 HOST_VERSION = 0x10,
75 HOST_EM_LOC = 0x1c,
76 HOST_EM_CTL = 0x20,
77 HOST_CAP2 = 0x24,
78
79
80 HOST_RESET = (1 << 0),
81 HOST_IRQ_EN = (1 << 1),
82 HOST_MRSM = (1 << 2),
83 HOST_AHCI_EN = (1 << 31),
84
85
86 HOST_CAP_SXS = (1 << 5),
87 HOST_CAP_EMS = (1 << 6),
88 HOST_CAP_CCC = (1 << 7),
89 HOST_CAP_PART = (1 << 13),
90 HOST_CAP_SSC = (1 << 14),
91 HOST_CAP_PIO_MULTI = (1 << 15),
92 HOST_CAP_FBS = (1 << 16),
93 HOST_CAP_PMP = (1 << 17),
94 HOST_CAP_ONLY = (1 << 18),
95 HOST_CAP_CLO = (1 << 24),
96 HOST_CAP_LED = (1 << 25),
97 HOST_CAP_ALPM = (1 << 26),
98 HOST_CAP_SSS = (1 << 27),
99 HOST_CAP_MPS = (1 << 28),
100 HOST_CAP_SNTF = (1 << 29),
101 HOST_CAP_NCQ = (1 << 30),
102 HOST_CAP_64 = (1 << 31),
103
104
105 HOST_CAP2_BOH = (1 << 0),
106 HOST_CAP2_NVMHCI = (1 << 1),
107 HOST_CAP2_APST = (1 << 2),
108 HOST_CAP2_SDS = (1 << 3),
109 HOST_CAP2_SADM = (1 << 4),
110 HOST_CAP2_DESO = (1 << 5),
111
112
113 PORT_LST_ADDR = 0x00,
114 PORT_LST_ADDR_HI = 0x04,
115 PORT_FIS_ADDR = 0x08,
116 PORT_FIS_ADDR_HI = 0x0c,
117 PORT_IRQ_STAT = 0x10,
118 PORT_IRQ_MASK = 0x14,
119 PORT_CMD = 0x18,
120 PORT_TFDATA = 0x20,
121 PORT_SIG = 0x24,
122 PORT_CMD_ISSUE = 0x38,
123 PORT_SCR_STAT = 0x28,
124 PORT_SCR_CTL = 0x2c,
125 PORT_SCR_ERR = 0x30,
126 PORT_SCR_ACT = 0x34,
127 PORT_SCR_NTF = 0x3c,
128 PORT_FBS = 0x40,
129 PORT_DEVSLP = 0x44,
130
131
132 PORT_IRQ_COLD_PRES = (1 << 31),
133 PORT_IRQ_TF_ERR = (1 << 30),
134 PORT_IRQ_HBUS_ERR = (1 << 29),
135 PORT_IRQ_HBUS_DATA_ERR = (1 << 28),
136 PORT_IRQ_IF_ERR = (1 << 27),
137 PORT_IRQ_IF_NONFATAL = (1 << 26),
138 PORT_IRQ_OVERFLOW = (1 << 24),
139 PORT_IRQ_BAD_PMP = (1 << 23),
140
141 PORT_IRQ_PHYRDY = (1 << 22),
142 PORT_IRQ_DEV_ILCK = (1 << 7),
143 PORT_IRQ_CONNECT = (1 << 6),
144 PORT_IRQ_SG_DONE = (1 << 5),
145 PORT_IRQ_UNK_FIS = (1 << 4),
146 PORT_IRQ_SDB_FIS = (1 << 3),
147 PORT_IRQ_DMAS_FIS = (1 << 2),
148 PORT_IRQ_PIOS_FIS = (1 << 1),
149 PORT_IRQ_D2H_REG_FIS = (1 << 0),
150
151 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
152 PORT_IRQ_IF_ERR |
153 PORT_IRQ_CONNECT |
154 PORT_IRQ_PHYRDY |
155 PORT_IRQ_UNK_FIS |
156 PORT_IRQ_BAD_PMP,
157 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
158 PORT_IRQ_TF_ERR |
159 PORT_IRQ_HBUS_DATA_ERR,
160 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
161 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
162 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
163
164
165 PORT_CMD_ASP = (1 << 27),
166 PORT_CMD_ALPE = (1 << 26),
167 PORT_CMD_ATAPI = (1 << 24),
168 PORT_CMD_FBSCP = (1 << 22),
169 PORT_CMD_ESP = (1 << 21),
170 PORT_CMD_HPCP = (1 << 18),
171 PORT_CMD_PMP = (1 << 17),
172 PORT_CMD_LIST_ON = (1 << 15),
173 PORT_CMD_FIS_ON = (1 << 14),
174 PORT_CMD_FIS_RX = (1 << 4),
175 PORT_CMD_CLO = (1 << 3),
176 PORT_CMD_POWER_ON = (1 << 2),
177 PORT_CMD_SPIN_UP = (1 << 1),
178 PORT_CMD_START = (1 << 0),
179
180 PORT_CMD_ICC_MASK = (0xf << 28),
181 PORT_CMD_ICC_ACTIVE = (0x1 << 28),
182 PORT_CMD_ICC_PARTIAL = (0x2 << 28),
183 PORT_CMD_ICC_SLUMBER = (0x6 << 28),
184
185
186 PORT_FBS_DWE_OFFSET = 16,
187 PORT_FBS_ADO_OFFSET = 12,
188 PORT_FBS_DEV_OFFSET = 8,
189 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET),
190 PORT_FBS_SDE = (1 << 2),
191 PORT_FBS_DEC = (1 << 1),
192 PORT_FBS_EN = (1 << 0),
193
194
195 PORT_DEVSLP_DM_OFFSET = 25,
196 PORT_DEVSLP_DM_MASK = (0xf << 25),
197 PORT_DEVSLP_DITO_OFFSET = 15,
198 PORT_DEVSLP_MDAT_OFFSET = 10,
199 PORT_DEVSLP_DETO_OFFSET = 2,
200 PORT_DEVSLP_DSP = (1 << 1),
201 PORT_DEVSLP_ADSE = (1 << 0),
202
203
204
205#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
206
207 AHCI_HFLAG_NO_NCQ = (1 << 0),
208 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1),
209 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2),
210 AHCI_HFLAG_32BIT_ONLY = (1 << 3),
211 AHCI_HFLAG_MV_PATA = (1 << 4),
212 AHCI_HFLAG_NO_MSI = (1 << 5),
213 AHCI_HFLAG_NO_PMP = (1 << 6),
214 AHCI_HFLAG_SECT255 = (1 << 8),
215 AHCI_HFLAG_YES_NCQ = (1 << 9),
216 AHCI_HFLAG_NO_SUSPEND = (1 << 10),
217 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11),
218
219 AHCI_HFLAG_NO_SNTF = (1 << 12),
220 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13),
221 AHCI_HFLAG_YES_FBS = (1 << 14),
222 AHCI_HFLAG_DELAY_ENGINE = (1 << 15),
223
224
225 AHCI_HFLAG_NO_DEVSLP = (1 << 17),
226 AHCI_HFLAG_NO_FBS = (1 << 18),
227
228#ifdef CONFIG_PCI_MSI
229 AHCI_HFLAG_MULTI_MSI = (1 << 20),
230#else
231
232 AHCI_HFLAG_MULTI_MSI = 0,
233#endif
234 AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22),
235 AHCI_HFLAG_YES_ALPM = (1 << 23),
236 AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24),
237
238 AHCI_HFLAG_IS_MOBILE = (1 << 25),
239
240
241 AHCI_HFLAG_SUSPEND_PHYS = (1 << 26),
242
243 AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27),
244
245 AHCI_HFLAG_NO_SXS = (1 << 28),
246
247
248
249 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
250 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
251
252 ICH_MAP = 0x90,
253 PCS_6 = 0x92,
254 PCS_7 = 0x94,
255
256
257 EM_MAX_SLOTS = 8,
258 EM_MAX_RETRY = 5,
259
260
261 EM_CTL_RST = (1 << 9),
262 EM_CTL_TM = (1 << 8),
263 EM_CTL_MR = (1 << 0),
264 EM_CTL_ALHD = (1 << 26),
265 EM_CTL_XMT = (1 << 25),
266 EM_CTL_SMB = (1 << 24),
267 EM_CTL_SGPIO = (1 << 19),
268 EM_CTL_SES = (1 << 18),
269 EM_CTL_SAFTE = (1 << 17),
270 EM_CTL_LED = (1 << 16),
271
272
273 EM_MSG_TYPE_LED = (1 << 0),
274 EM_MSG_TYPE_SAFTE = (1 << 1),
275 EM_MSG_TYPE_SES2 = (1 << 2),
276 EM_MSG_TYPE_SGPIO = (1 << 3),
277};
278
279struct ahci_cmd_hdr {
280 __le32 opts;
281 __le32 status;
282 __le32 tbl_addr;
283 __le32 tbl_addr_hi;
284 __le32 reserved[4];
285};
286
287struct ahci_sg {
288 __le32 addr;
289 __le32 addr_hi;
290 __le32 reserved;
291 __le32 flags_size;
292};
293
294struct ahci_em_priv {
295 enum sw_activity blink_policy;
296 struct timer_list timer;
297 unsigned long saved_activity;
298 unsigned long activity;
299 unsigned long led_state;
300 struct ata_link *link;
301};
302
303struct ahci_port_priv {
304 struct ata_link *active_link;
305 struct ahci_cmd_hdr *cmd_slot;
306 dma_addr_t cmd_slot_dma;
307 void *cmd_tbl;
308 dma_addr_t cmd_tbl_dma;
309 void *rx_fis;
310 dma_addr_t rx_fis_dma;
311
312 unsigned int ncq_saw_d2h:1;
313 unsigned int ncq_saw_dmas:1;
314 unsigned int ncq_saw_sdb:1;
315 spinlock_t lock;
316 u32 intr_mask;
317 bool fbs_supported;
318 bool fbs_enabled;
319 int fbs_last_dev;
320
321 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
322 char *irq_desc;
323};
324
325struct ahci_host_priv {
326
327 unsigned int flags;
328 u32 force_port_map;
329 u32 mask_port_map;
330
331 void __iomem * mmio;
332 u32 cap;
333 u32 cap2;
334 u32 version;
335 u32 port_map;
336 u32 saved_cap;
337 u32 saved_cap2;
338 u32 saved_port_map;
339 u32 em_loc;
340 u32 em_buf_sz;
341 u32 em_msg_type;
342 u32 remapped_nvme;
343 bool got_runtime_pm;
344 struct clk *clks[AHCI_MAX_CLKS];
345 struct reset_control *rsts;
346 struct regulator **target_pwrs;
347 struct regulator *ahci_regulator;
348 struct regulator *phy_regulator;
349
350
351
352
353 struct phy **phys;
354 unsigned nports;
355 void *plat_data;
356 unsigned int irq;
357
358
359
360
361
362 void (*start_engine)(struct ata_port *ap);
363
364
365
366
367
368 int (*stop_engine)(struct ata_port *ap);
369
370 irqreturn_t (*irq_handler)(int irq, void *dev_instance);
371
372
373 int (*get_irq_vector)(struct ata_host *host,
374 int port);
375};
376
377extern int ahci_ignore_sss;
378
379extern struct device_attribute *ahci_shost_attrs[];
380extern struct device_attribute *ahci_sdev_attrs[];
381
382
383
384
385
386#define AHCI_SHT(drv_name) \
387 __ATA_BASE_SHT(drv_name), \
388 .can_queue = AHCI_MAX_CMDS, \
389 .sg_tablesize = AHCI_MAX_SG, \
390 .dma_boundary = AHCI_DMA_BOUNDARY, \
391 .shost_attrs = ahci_shost_attrs, \
392 .sdev_attrs = ahci_sdev_attrs, \
393 .change_queue_depth = ata_scsi_change_queue_depth, \
394 .tag_alloc_policy = BLK_TAG_ALLOC_RR, \
395 .slave_configure = ata_scsi_slave_config
396
397extern struct ata_port_operations ahci_ops;
398extern struct ata_port_operations ahci_platform_ops;
399extern struct ata_port_operations ahci_pmp_retry_srst_ops;
400
401unsigned int ahci_dev_classify(struct ata_port *ap);
402void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
403 u32 opts);
404void ahci_save_initial_config(struct device *dev,
405 struct ahci_host_priv *hpriv);
406void ahci_init_controller(struct ata_host *host);
407int ahci_reset_controller(struct ata_host *host);
408
409int ahci_do_softreset(struct ata_link *link, unsigned int *class,
410 int pmp, unsigned long deadline,
411 int (*check_ready)(struct ata_link *link));
412
413int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
414 unsigned long deadline, bool *online);
415
416unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
417int ahci_stop_engine(struct ata_port *ap);
418void ahci_start_fis_rx(struct ata_port *ap);
419void ahci_start_engine(struct ata_port *ap);
420int ahci_check_ready(struct ata_link *link);
421int ahci_kick_engine(struct ata_port *ap);
422int ahci_port_resume(struct ata_port *ap);
423void ahci_set_em_messages(struct ahci_host_priv *hpriv,
424 struct ata_port_info *pi);
425int ahci_reset_em(struct ata_host *host);
426void ahci_print_info(struct ata_host *host, const char *scc_s);
427int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
428void ahci_error_handler(struct ata_port *ap);
429u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
430
431static inline void __iomem *__ahci_port_base(struct ata_host *host,
432 unsigned int port_no)
433{
434 struct ahci_host_priv *hpriv = host->private_data;
435 void __iomem *mmio = hpriv->mmio;
436
437 return mmio + 0x100 + (port_no * 0x80);
438}
439
440static inline void __iomem *ahci_port_base(struct ata_port *ap)
441{
442 return __ahci_port_base(ap->host, ap->port_no);
443}
444
445static inline int ahci_nr_ports(u32 cap)
446{
447 return (cap & 0x1f) + 1;
448}
449
450#endif
451