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69#include <linux/kernel.h>
70#include <linux/module.h>
71#include <linux/pci.h>
72#include <linux/init.h>
73#include <linux/blkdev.h>
74#include <linux/delay.h>
75#include <linux/device.h>
76#include <linux/gfp.h>
77#include <scsi/scsi_host.h>
78#include <linux/libata.h>
79#include <linux/dmi.h>
80
81#define DRV_NAME "ata_piix"
82#define DRV_VERSION "2.13"
83
84enum {
85 PIIX_IOCFG = 0x54,
86 ICH5_PMR = 0x90,
87 ICH5_PCS = 0x92,
88 PIIX_SIDPR_BAR = 5,
89 PIIX_SIDPR_LEN = 16,
90 PIIX_SIDPR_IDX = 0,
91 PIIX_SIDPR_DATA = 4,
92
93 PIIX_FLAG_CHECKINTR = (1 << 28),
94 PIIX_FLAG_SIDPR = (1 << 29),
95
96 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
97 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
98
99 PIIX_FLAG_PIO16 = (1 << 30),
100
101 PIIX_80C_PRI = (1 << 5) | (1 << 4),
102 PIIX_80C_SEC = (1 << 7) | (1 << 6),
103
104
105 P0 = 0,
106 P1 = 1,
107 P2 = 2,
108 P3 = 3,
109 IDE = -1,
110 NA = -2,
111 RV = -3,
112
113 PIIX_AHCI_DEVICE = 6,
114
115
116 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
117};
118
119enum piix_controller_ids {
120
121 piix_pata_mwdma,
122 piix_pata_33,
123 ich_pata_33,
124 ich_pata_66,
125 ich_pata_100,
126 ich_pata_100_nomwdma1,
127 ich5_sata,
128 ich6_sata,
129 ich6m_sata,
130 ich8_sata,
131 ich8_2port_sata,
132 ich8m_apple_sata,
133 tolapai_sata,
134 piix_pata_vmw,
135 ich8_sata_snb,
136 ich8_2port_sata_snb,
137 ich8_2port_sata_byt,
138};
139
140struct piix_map_db {
141 const u32 mask;
142 const u16 port_enable;
143 const int map[][4];
144};
145
146struct piix_host_priv {
147 const int *map;
148 u32 saved_iocfg;
149 void __iomem *sidpr;
150};
151
152static unsigned int in_module_init = 1;
153
154static const struct pci_device_id piix_pci_tbl[] = {
155
156 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
157
158 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
159
160
161 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
162
163 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
164
165 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
166
167 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
168
169 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
170
171 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
172
173 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
174
175 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
176
177 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
178
179 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
180
181 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
182
183 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
184 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
185
186 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187
188 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189
190 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191
192 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193
194 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
195 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
196
197 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198
199
200
201
202 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
203
204 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
205
206 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
207
208 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
209
210 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
211
212 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
213
214
215 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
216 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
217
218 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
219
220 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
221
222 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
223
224 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
225
226 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
227
228 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
229 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
230 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
231
232 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
233
234 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
235
236 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
237
238 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
239
240 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
241
242 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
243
244 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
245
246 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
247
248 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
249
250 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
251
252 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
253
254 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
255
256 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
257
258 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
259
260 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
261
262 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
263
264 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
265
266 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
267
268 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
269
270 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
271
272 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
273
274 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
275
276 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
277
278 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
279
280 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
281
282 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
283
284 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
285
286 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
287
288 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
289
290 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
291
292 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
293
294 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
295
296 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
297
298 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
299
300 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
301
302 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303
304 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
305
306 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
307
308 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
309
310 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
311
312 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
313
314 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
315
316 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
317
318 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
319
320 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
321
322 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
323 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
324
325 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
326
327 { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
328
329 { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
330
331 { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
332
333 { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
334
335 { }
336};
337
338static const struct piix_map_db ich5_map_db = {
339 .mask = 0x7,
340 .port_enable = 0x3,
341 .map = {
342
343 { P0, NA, P1, NA },
344 { P1, NA, P0, NA },
345 { RV, RV, RV, RV },
346 { RV, RV, RV, RV },
347 { P0, P1, IDE, IDE },
348 { P1, P0, IDE, IDE },
349 { IDE, IDE, P0, P1 },
350 { IDE, IDE, P1, P0 },
351 },
352};
353
354static const struct piix_map_db ich6_map_db = {
355 .mask = 0x3,
356 .port_enable = 0xf,
357 .map = {
358
359 { P0, P2, P1, P3 },
360 { IDE, IDE, P1, P3 },
361 { P0, P2, IDE, IDE },
362 { RV, RV, RV, RV },
363 },
364};
365
366static const struct piix_map_db ich6m_map_db = {
367 .mask = 0x3,
368 .port_enable = 0x5,
369
370
371
372
373
374 .map = {
375
376 { P0, P2, NA, NA },
377 { IDE, IDE, P1, P3 },
378 { P0, P2, IDE, IDE },
379 { RV, RV, RV, RV },
380 },
381};
382
383static const struct piix_map_db ich8_map_db = {
384 .mask = 0x3,
385 .port_enable = 0xf,
386 .map = {
387
388 { P0, P2, P1, P3 },
389 { RV, RV, RV, RV },
390 { P0, P2, IDE, IDE },
391 { RV, RV, RV, RV },
392 },
393};
394
395static const struct piix_map_db ich8_2port_map_db = {
396 .mask = 0x3,
397 .port_enable = 0x3,
398 .map = {
399
400 { P0, NA, P1, NA },
401 { RV, RV, RV, RV },
402 { RV, RV, RV, RV },
403 { RV, RV, RV, RV },
404 },
405};
406
407static const struct piix_map_db ich8m_apple_map_db = {
408 .mask = 0x3,
409 .port_enable = 0x1,
410 .map = {
411
412 { P0, NA, NA, NA },
413 { RV, RV, RV, RV },
414 { P0, P2, IDE, IDE },
415 { RV, RV, RV, RV },
416 },
417};
418
419static const struct piix_map_db tolapai_map_db = {
420 .mask = 0x3,
421 .port_enable = 0x3,
422 .map = {
423
424 { P0, NA, P1, NA },
425 { RV, RV, RV, RV },
426 { RV, RV, RV, RV },
427 { RV, RV, RV, RV },
428 },
429};
430
431static const struct piix_map_db *piix_map_db_table[] = {
432 [ich5_sata] = &ich5_map_db,
433 [ich6_sata] = &ich6_map_db,
434 [ich6m_sata] = &ich6m_map_db,
435 [ich8_sata] = &ich8_map_db,
436 [ich8_2port_sata] = &ich8_2port_map_db,
437 [ich8m_apple_sata] = &ich8m_apple_map_db,
438 [tolapai_sata] = &tolapai_map_db,
439 [ich8_sata_snb] = &ich8_map_db,
440 [ich8_2port_sata_snb] = &ich8_2port_map_db,
441 [ich8_2port_sata_byt] = &ich8_2port_map_db,
442};
443
444static const struct pci_bits piix_enable_bits[] = {
445 { 0x41U, 1U, 0x80UL, 0x80UL },
446 { 0x43U, 1U, 0x80UL, 0x80UL },
447};
448
449MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
450MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
451MODULE_LICENSE("GPL");
452MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
453MODULE_VERSION(DRV_VERSION);
454
455struct ich_laptop {
456 u16 device;
457 u16 subvendor;
458 u16 subdevice;
459};
460
461
462
463
464
465static const struct ich_laptop ich_laptop[] = {
466
467 { 0x27DF, 0x0005, 0x0280 },
468 { 0x27DF, 0x1025, 0x0102 },
469 { 0x27DF, 0x1025, 0x0110 },
470 { 0x27DF, 0x1028, 0x02b0 },
471 { 0x27DF, 0x1043, 0x1267 },
472 { 0x27DF, 0x103C, 0x30A1 },
473 { 0x27DF, 0x103C, 0x361a },
474 { 0x27DF, 0x1071, 0xD221 },
475 { 0x27DF, 0x152D, 0x0778 },
476 { 0x24CA, 0x1025, 0x0061 },
477 { 0x24CA, 0x1025, 0x003d },
478 { 0x24CA, 0x10CF, 0x11AB },
479 { 0x266F, 0x1025, 0x0066 },
480 { 0x2653, 0x1043, 0x82D8 },
481 { 0x27df, 0x104d, 0x900e },
482
483 { 0, }
484};
485
486static int piix_port_start(struct ata_port *ap)
487{
488 if (!(ap->flags & PIIX_FLAG_PIO16))
489 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
490
491 return ata_bmdma_port_start(ap);
492}
493
494
495
496
497
498
499
500
501
502
503
504
505static int ich_pata_cable_detect(struct ata_port *ap)
506{
507 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
508 struct piix_host_priv *hpriv = ap->host->private_data;
509 const struct ich_laptop *lap = &ich_laptop[0];
510 u8 mask;
511
512
513 while (lap->device) {
514 if (lap->device == pdev->device &&
515 lap->subvendor == pdev->subsystem_vendor &&
516 lap->subdevice == pdev->subsystem_device)
517 return ATA_CBL_PATA40_SHORT;
518
519 lap++;
520 }
521
522
523 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
524 if ((hpriv->saved_iocfg & mask) == 0)
525 return ATA_CBL_PATA40;
526 return ATA_CBL_PATA80;
527}
528
529
530
531
532
533
534
535
536
537static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
538{
539 struct ata_port *ap = link->ap;
540 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
541
542 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
543 return -ENOENT;
544 return ata_sff_prereset(link, deadline);
545}
546
547static DEFINE_SPINLOCK(piix_lock);
548
549static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
550 u8 pio)
551{
552 struct pci_dev *dev = to_pci_dev(ap->host->dev);
553 unsigned long flags;
554 unsigned int is_slave = (adev->devno != 0);
555 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
556 unsigned int slave_port = 0x44;
557 u16 master_data;
558 u8 slave_data;
559 u8 udma_enable;
560 int control = 0;
561
562
563
564
565
566
567 static const
568 u8 timings[][2] = { { 0, 0 },
569 { 0, 0 },
570 { 1, 0 },
571 { 2, 1 },
572 { 2, 3 }, };
573
574 if (pio >= 2)
575 control |= 1;
576 if (ata_pio_need_iordy(adev))
577 control |= 2;
578
579 if (adev->class == ATA_DEV_ATA)
580 control |= 4;
581
582
583
584
585 if (adev->pio_mode < XFER_PIO_0 + pio)
586
587 control |= 8;
588
589 spin_lock_irqsave(&piix_lock, flags);
590
591
592
593
594
595 pci_read_config_word(dev, master_port, &master_data);
596 if (is_slave) {
597
598 master_data &= 0xff0f;
599
600 master_data |= (control << 4);
601 pci_read_config_byte(dev, slave_port, &slave_data);
602 slave_data &= (ap->port_no ? 0x0f : 0xf0);
603
604 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
605 << (ap->port_no ? 4 : 0);
606 } else {
607
608 master_data &= 0xccf0;
609
610 master_data |= control;
611
612 master_data |=
613 (timings[pio][0] << 12) |
614 (timings[pio][1] << 8);
615 }
616
617
618 master_data |= 0x4000;
619 pci_write_config_word(dev, master_port, master_data);
620 if (is_slave)
621 pci_write_config_byte(dev, slave_port, slave_data);
622
623
624
625
626 if (ap->udma_mask) {
627 pci_read_config_byte(dev, 0x48, &udma_enable);
628 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
629 pci_write_config_byte(dev, 0x48, udma_enable);
630 }
631
632 spin_unlock_irqrestore(&piix_lock, flags);
633}
634
635
636
637
638
639
640
641
642
643
644
645
646static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
647{
648 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
649}
650
651
652
653
654
655
656
657
658
659
660
661
662
663static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
664{
665 struct pci_dev *dev = to_pci_dev(ap->host->dev);
666 unsigned long flags;
667 u8 speed = adev->dma_mode;
668 int devid = adev->devno + 2 * ap->port_no;
669 u8 udma_enable = 0;
670
671 if (speed >= XFER_UDMA_0) {
672 unsigned int udma = speed - XFER_UDMA_0;
673 u16 udma_timing;
674 u16 ideconf;
675 int u_clock, u_speed;
676
677 spin_lock_irqsave(&piix_lock, flags);
678
679 pci_read_config_byte(dev, 0x48, &udma_enable);
680
681
682
683
684
685
686
687
688 u_speed = min(2 - (udma & 1), udma);
689 if (udma == 5)
690 u_clock = 0x1000;
691 else if (udma > 2)
692 u_clock = 1;
693 else
694 u_clock = 0;
695
696 udma_enable |= (1 << devid);
697
698
699 pci_read_config_word(dev, 0x4A, &udma_timing);
700 udma_timing &= ~(3 << (4 * devid));
701 udma_timing |= u_speed << (4 * devid);
702 pci_write_config_word(dev, 0x4A, udma_timing);
703
704 if (isich) {
705
706 pci_read_config_word(dev, 0x54, &ideconf);
707 ideconf &= ~(0x1001 << devid);
708 ideconf |= u_clock << devid;
709
710
711 pci_write_config_word(dev, 0x54, ideconf);
712 }
713
714 pci_write_config_byte(dev, 0x48, udma_enable);
715
716 spin_unlock_irqrestore(&piix_lock, flags);
717 } else {
718
719 unsigned int mwdma = speed - XFER_MW_DMA_0;
720 const unsigned int needed_pio[3] = {
721 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
722 };
723 int pio = needed_pio[mwdma] - XFER_PIO_0;
724
725
726 piix_set_timings(ap, adev, pio);
727 }
728}
729
730
731
732
733
734
735
736
737
738
739
740
741static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
742{
743 do_pata_set_dmamode(ap, adev, 0);
744}
745
746
747
748
749
750
751
752
753
754
755
756
757static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
758{
759 do_pata_set_dmamode(ap, adev, 1);
760}
761
762
763
764
765
766
767
768
769
770static const int piix_sidx_map[] = {
771 [SCR_STATUS] = 0,
772 [SCR_ERROR] = 2,
773 [SCR_CONTROL] = 1,
774};
775
776static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
777{
778 struct ata_port *ap = link->ap;
779 struct piix_host_priv *hpriv = ap->host->private_data;
780
781 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
782 hpriv->sidpr + PIIX_SIDPR_IDX);
783}
784
785static int piix_sidpr_scr_read(struct ata_link *link,
786 unsigned int reg, u32 *val)
787{
788 struct piix_host_priv *hpriv = link->ap->host->private_data;
789
790 if (reg >= ARRAY_SIZE(piix_sidx_map))
791 return -EINVAL;
792
793 piix_sidpr_sel(link, reg);
794 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
795 return 0;
796}
797
798static int piix_sidpr_scr_write(struct ata_link *link,
799 unsigned int reg, u32 val)
800{
801 struct piix_host_priv *hpriv = link->ap->host->private_data;
802
803 if (reg >= ARRAY_SIZE(piix_sidx_map))
804 return -EINVAL;
805
806 piix_sidpr_sel(link, reg);
807 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
808 return 0;
809}
810
811static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
812 unsigned hints)
813{
814 return sata_link_scr_lpm(link, policy, false);
815}
816
817static bool piix_irq_check(struct ata_port *ap)
818{
819 if (unlikely(!ap->ioaddr.bmdma_addr))
820 return false;
821
822 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
823}
824
825#ifdef CONFIG_PM_SLEEP
826static int piix_broken_suspend(void)
827{
828 static const struct dmi_system_id sysids[] = {
829 {
830 .ident = "TECRA M3",
831 .matches = {
832 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
833 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
834 },
835 },
836 {
837 .ident = "TECRA M3",
838 .matches = {
839 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
840 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
841 },
842 },
843 {
844 .ident = "TECRA M3",
845 .matches = {
846 DMI_MATCH(DMI_OEM_STRING, "Tecra M3,"),
847 },
848 },
849 {
850 .ident = "TECRA M4",
851 .matches = {
852 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
853 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
854 },
855 },
856 {
857 .ident = "TECRA M4",
858 .matches = {
859 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
860 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
861 },
862 },
863 {
864 .ident = "TECRA M5",
865 .matches = {
866 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
867 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
868 },
869 },
870 {
871 .ident = "TECRA M6",
872 .matches = {
873 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
874 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
875 },
876 },
877 {
878 .ident = "TECRA M7",
879 .matches = {
880 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
881 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
882 },
883 },
884 {
885 .ident = "TECRA A8",
886 .matches = {
887 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
888 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
889 },
890 },
891 {
892 .ident = "Satellite R20",
893 .matches = {
894 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
895 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
896 },
897 },
898 {
899 .ident = "Satellite R25",
900 .matches = {
901 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
902 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
903 },
904 },
905 {
906 .ident = "Satellite U200",
907 .matches = {
908 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
909 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
910 },
911 },
912 {
913 .ident = "Satellite U200",
914 .matches = {
915 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
916 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
917 },
918 },
919 {
920 .ident = "Satellite Pro U200",
921 .matches = {
922 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
923 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
924 },
925 },
926 {
927 .ident = "Satellite U205",
928 .matches = {
929 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
930 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
931 },
932 },
933 {
934 .ident = "SATELLITE U205",
935 .matches = {
936 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
937 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
938 },
939 },
940 {
941 .ident = "Satellite Pro A120",
942 .matches = {
943 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
944 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
945 },
946 },
947 {
948 .ident = "Portege M500",
949 .matches = {
950 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
951 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
952 },
953 },
954 {
955 .ident = "VGN-BX297XP",
956 .matches = {
957 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
958 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
959 },
960 },
961
962 { }
963 };
964
965 if (dmi_check_system(sysids))
966 return 1;
967
968
969
970
971
972
973
974 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
975 dmi_match(DMI_PRODUCT_NAME, "000000") &&
976 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
977 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
978 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
979 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
980 dmi_match(DMI_BOARD_VERSION, "Version A0"))
981 return 1;
982
983 return 0;
984}
985
986static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
987{
988 struct ata_host *host = pci_get_drvdata(pdev);
989 unsigned long flags;
990 int rc = 0;
991
992 rc = ata_host_suspend(host, mesg);
993 if (rc)
994 return rc;
995
996
997
998
999
1000
1001 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1002 pci_save_state(pdev);
1003
1004
1005
1006
1007
1008 if (pdev->current_state == PCI_D0)
1009 pdev->current_state = PCI_UNKNOWN;
1010
1011
1012 spin_lock_irqsave(&host->lock, flags);
1013 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1014 spin_unlock_irqrestore(&host->lock, flags);
1015 } else
1016 ata_pci_device_do_suspend(pdev, mesg);
1017
1018 return 0;
1019}
1020
1021static int piix_pci_device_resume(struct pci_dev *pdev)
1022{
1023 struct ata_host *host = pci_get_drvdata(pdev);
1024 unsigned long flags;
1025 int rc;
1026
1027 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1028 spin_lock_irqsave(&host->lock, flags);
1029 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1030 spin_unlock_irqrestore(&host->lock, flags);
1031
1032 pci_set_power_state(pdev, PCI_D0);
1033 pci_restore_state(pdev);
1034
1035
1036
1037
1038
1039 rc = pci_reenable_device(pdev);
1040 if (rc)
1041 dev_err(&pdev->dev,
1042 "failed to enable device after resume (%d)\n",
1043 rc);
1044 } else
1045 rc = ata_pci_device_do_resume(pdev);
1046
1047 if (rc == 0)
1048 ata_host_resume(host);
1049
1050 return rc;
1051}
1052#endif
1053
1054static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1055{
1056 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1057}
1058
1059static struct scsi_host_template piix_sht = {
1060 ATA_BMDMA_SHT(DRV_NAME),
1061};
1062
1063static struct ata_port_operations piix_sata_ops = {
1064 .inherits = &ata_bmdma32_port_ops,
1065 .sff_irq_check = piix_irq_check,
1066 .port_start = piix_port_start,
1067};
1068
1069static struct ata_port_operations piix_pata_ops = {
1070 .inherits = &piix_sata_ops,
1071 .cable_detect = ata_cable_40wire,
1072 .set_piomode = piix_set_piomode,
1073 .set_dmamode = piix_set_dmamode,
1074 .prereset = piix_pata_prereset,
1075};
1076
1077static struct ata_port_operations piix_vmw_ops = {
1078 .inherits = &piix_pata_ops,
1079 .bmdma_status = piix_vmw_bmdma_status,
1080};
1081
1082static struct ata_port_operations ich_pata_ops = {
1083 .inherits = &piix_pata_ops,
1084 .cable_detect = ich_pata_cable_detect,
1085 .set_dmamode = ich_set_dmamode,
1086};
1087
1088static struct device_attribute *piix_sidpr_shost_attrs[] = {
1089 &dev_attr_link_power_management_policy,
1090 NULL
1091};
1092
1093static struct scsi_host_template piix_sidpr_sht = {
1094 ATA_BMDMA_SHT(DRV_NAME),
1095 .shost_attrs = piix_sidpr_shost_attrs,
1096};
1097
1098static struct ata_port_operations piix_sidpr_sata_ops = {
1099 .inherits = &piix_sata_ops,
1100 .hardreset = sata_std_hardreset,
1101 .scr_read = piix_sidpr_scr_read,
1102 .scr_write = piix_sidpr_scr_write,
1103 .set_lpm = piix_sidpr_set_lpm,
1104};
1105
1106static struct ata_port_info piix_port_info[] = {
1107 [piix_pata_mwdma] =
1108 {
1109 .flags = PIIX_PATA_FLAGS,
1110 .pio_mask = ATA_PIO4,
1111 .mwdma_mask = ATA_MWDMA12_ONLY,
1112 .port_ops = &piix_pata_ops,
1113 },
1114
1115 [piix_pata_33] =
1116 {
1117 .flags = PIIX_PATA_FLAGS,
1118 .pio_mask = ATA_PIO4,
1119 .mwdma_mask = ATA_MWDMA12_ONLY,
1120 .udma_mask = ATA_UDMA2,
1121 .port_ops = &piix_pata_ops,
1122 },
1123
1124 [ich_pata_33] =
1125 {
1126 .flags = PIIX_PATA_FLAGS,
1127 .pio_mask = ATA_PIO4,
1128 .mwdma_mask = ATA_MWDMA12_ONLY,
1129 .udma_mask = ATA_UDMA2,
1130 .port_ops = &ich_pata_ops,
1131 },
1132
1133 [ich_pata_66] =
1134 {
1135 .flags = PIIX_PATA_FLAGS,
1136 .pio_mask = ATA_PIO4,
1137 .mwdma_mask = ATA_MWDMA12_ONLY,
1138 .udma_mask = ATA_UDMA4,
1139 .port_ops = &ich_pata_ops,
1140 },
1141
1142 [ich_pata_100] =
1143 {
1144 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1145 .pio_mask = ATA_PIO4,
1146 .mwdma_mask = ATA_MWDMA12_ONLY,
1147 .udma_mask = ATA_UDMA5,
1148 .port_ops = &ich_pata_ops,
1149 },
1150
1151 [ich_pata_100_nomwdma1] =
1152 {
1153 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1154 .pio_mask = ATA_PIO4,
1155 .mwdma_mask = ATA_MWDMA2_ONLY,
1156 .udma_mask = ATA_UDMA5,
1157 .port_ops = &ich_pata_ops,
1158 },
1159
1160 [ich5_sata] =
1161 {
1162 .flags = PIIX_SATA_FLAGS,
1163 .pio_mask = ATA_PIO4,
1164 .mwdma_mask = ATA_MWDMA2,
1165 .udma_mask = ATA_UDMA6,
1166 .port_ops = &piix_sata_ops,
1167 },
1168
1169 [ich6_sata] =
1170 {
1171 .flags = PIIX_SATA_FLAGS,
1172 .pio_mask = ATA_PIO4,
1173 .mwdma_mask = ATA_MWDMA2,
1174 .udma_mask = ATA_UDMA6,
1175 .port_ops = &piix_sata_ops,
1176 },
1177
1178 [ich6m_sata] =
1179 {
1180 .flags = PIIX_SATA_FLAGS,
1181 .pio_mask = ATA_PIO4,
1182 .mwdma_mask = ATA_MWDMA2,
1183 .udma_mask = ATA_UDMA6,
1184 .port_ops = &piix_sata_ops,
1185 },
1186
1187 [ich8_sata] =
1188 {
1189 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1190 .pio_mask = ATA_PIO4,
1191 .mwdma_mask = ATA_MWDMA2,
1192 .udma_mask = ATA_UDMA6,
1193 .port_ops = &piix_sata_ops,
1194 },
1195
1196 [ich8_2port_sata] =
1197 {
1198 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1199 .pio_mask = ATA_PIO4,
1200 .mwdma_mask = ATA_MWDMA2,
1201 .udma_mask = ATA_UDMA6,
1202 .port_ops = &piix_sata_ops,
1203 },
1204
1205 [tolapai_sata] =
1206 {
1207 .flags = PIIX_SATA_FLAGS,
1208 .pio_mask = ATA_PIO4,
1209 .mwdma_mask = ATA_MWDMA2,
1210 .udma_mask = ATA_UDMA6,
1211 .port_ops = &piix_sata_ops,
1212 },
1213
1214 [ich8m_apple_sata] =
1215 {
1216 .flags = PIIX_SATA_FLAGS,
1217 .pio_mask = ATA_PIO4,
1218 .mwdma_mask = ATA_MWDMA2,
1219 .udma_mask = ATA_UDMA6,
1220 .port_ops = &piix_sata_ops,
1221 },
1222
1223 [piix_pata_vmw] =
1224 {
1225 .flags = PIIX_PATA_FLAGS,
1226 .pio_mask = ATA_PIO4,
1227 .mwdma_mask = ATA_MWDMA12_ONLY,
1228 .udma_mask = ATA_UDMA2,
1229 .port_ops = &piix_vmw_ops,
1230 },
1231
1232
1233
1234
1235
1236 [ich8_sata_snb] =
1237 {
1238 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1239 .pio_mask = ATA_PIO4,
1240 .mwdma_mask = ATA_MWDMA2,
1241 .udma_mask = ATA_UDMA6,
1242 .port_ops = &piix_sata_ops,
1243 },
1244
1245 [ich8_2port_sata_snb] =
1246 {
1247 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1248 | PIIX_FLAG_PIO16,
1249 .pio_mask = ATA_PIO4,
1250 .mwdma_mask = ATA_MWDMA2,
1251 .udma_mask = ATA_UDMA6,
1252 .port_ops = &piix_sata_ops,
1253 },
1254
1255 [ich8_2port_sata_byt] =
1256 {
1257 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1258 .pio_mask = ATA_PIO4,
1259 .mwdma_mask = ATA_MWDMA2,
1260 .udma_mask = ATA_UDMA6,
1261 .port_ops = &piix_sata_ops,
1262 },
1263
1264};
1265
1266#define AHCI_PCI_BAR 5
1267#define AHCI_GLOBAL_CTL 0x04
1268#define AHCI_ENABLE (1 << 31)
1269static int piix_disable_ahci(struct pci_dev *pdev)
1270{
1271 void __iomem *mmio;
1272 u32 tmp;
1273 int rc = 0;
1274
1275
1276
1277
1278
1279 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1280 !pci_resource_len(pdev, AHCI_PCI_BAR))
1281 return 0;
1282
1283 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1284 if (!mmio)
1285 return -ENOMEM;
1286
1287 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1288 if (tmp & AHCI_ENABLE) {
1289 tmp &= ~AHCI_ENABLE;
1290 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1291
1292 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1293 if (tmp & AHCI_ENABLE)
1294 rc = -EIO;
1295 }
1296
1297 pci_iounmap(pdev, mmio);
1298 return rc;
1299}
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1310{
1311 struct pci_dev *pdev = NULL;
1312 u16 cfg;
1313 int no_piix_dma = 0;
1314
1315 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1316
1317
1318 pci_read_config_word(pdev, 0x41, &cfg);
1319
1320 if (pdev->revision == 0x00)
1321 no_piix_dma = 1;
1322
1323 else if (cfg & (1<<14) && pdev->revision < 5)
1324 no_piix_dma = 2;
1325 }
1326 if (no_piix_dma)
1327 dev_warn(&ata_dev->dev,
1328 "450NX errata present, disabling IDE DMA%s\n",
1329 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1330 : "");
1331
1332 return no_piix_dma;
1333}
1334
1335static void piix_init_pcs(struct ata_host *host,
1336 const struct piix_map_db *map_db)
1337{
1338 struct pci_dev *pdev = to_pci_dev(host->dev);
1339 u16 pcs, new_pcs;
1340
1341 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1342
1343 new_pcs = pcs | map_db->port_enable;
1344
1345 if (new_pcs != pcs) {
1346 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1347 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1348 msleep(150);
1349 }
1350}
1351
1352static const int *piix_init_sata_map(struct pci_dev *pdev,
1353 struct ata_port_info *pinfo,
1354 const struct piix_map_db *map_db)
1355{
1356 const int *map;
1357 int i, invalid_map = 0;
1358 u8 map_value;
1359 char buf[32];
1360 char *p = buf, *end = buf + sizeof(buf);
1361
1362 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1363
1364 map = map_db->map[map_value & map_db->mask];
1365
1366 for (i = 0; i < 4; i++) {
1367 switch (map[i]) {
1368 case RV:
1369 invalid_map = 1;
1370 p += scnprintf(p, end - p, " XX");
1371 break;
1372
1373 case NA:
1374 p += scnprintf(p, end - p, " --");
1375 break;
1376
1377 case IDE:
1378 WARN_ON((i & 1) || map[i + 1] != IDE);
1379 pinfo[i / 2] = piix_port_info[ich_pata_100];
1380 i++;
1381 p += scnprintf(p, end - p, " IDE IDE");
1382 break;
1383
1384 default:
1385 p += scnprintf(p, end - p, " P%d", map[i]);
1386 if (i & 1)
1387 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1388 break;
1389 }
1390 }
1391 dev_info(&pdev->dev, "MAP [%s ]\n", buf);
1392
1393 if (invalid_map)
1394 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1395
1396 return map;
1397}
1398
1399static bool piix_no_sidpr(struct ata_host *host)
1400{
1401 struct pci_dev *pdev = to_pci_dev(host->dev);
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1422 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1423 pdev->subsystem_device == 0xb049) {
1424 dev_warn(host->dev,
1425 "Samsung DB-P70 detected, disabling SIDPR\n");
1426 return true;
1427 }
1428
1429 return false;
1430}
1431
1432static int piix_init_sidpr(struct ata_host *host)
1433{
1434 struct pci_dev *pdev = to_pci_dev(host->dev);
1435 struct piix_host_priv *hpriv = host->private_data;
1436 struct ata_link *link0 = &host->ports[0]->link;
1437 u32 scontrol;
1438 int i, rc;
1439
1440
1441 for (i = 0; i < 4; i++)
1442 if (hpriv->map[i] == IDE)
1443 return 0;
1444
1445
1446 if (piix_no_sidpr(host))
1447 return 0;
1448
1449 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1450 return 0;
1451
1452 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1453 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1454 return 0;
1455
1456 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1457 return 0;
1458
1459 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1460
1461
1462
1463
1464
1465 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1466
1467
1468
1469
1470
1471 if ((scontrol & 0xf00) != 0x300) {
1472 scontrol |= 0x300;
1473 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1474 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1475
1476 if ((scontrol & 0xf00) != 0x300) {
1477 dev_info(host->dev,
1478 "SCR access via SIDPR is available but doesn't work\n");
1479 return 0;
1480 }
1481 }
1482
1483
1484 for (i = 0; i < 2; i++) {
1485 struct ata_port *ap = host->ports[i];
1486
1487 ap->ops = &piix_sidpr_sata_ops;
1488
1489 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1490 rc = ata_slave_link_init(ap);
1491 if (rc)
1492 return rc;
1493 }
1494 }
1495
1496 return 0;
1497}
1498
1499static void piix_iocfg_bit18_quirk(struct ata_host *host)
1500{
1501 static const struct dmi_system_id sysids[] = {
1502 {
1503
1504
1505
1506
1507 .ident = "M570U",
1508 .matches = {
1509 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1510 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1511 },
1512 },
1513
1514 { }
1515 };
1516 struct pci_dev *pdev = to_pci_dev(host->dev);
1517 struct piix_host_priv *hpriv = host->private_data;
1518
1519 if (!dmi_check_system(sysids))
1520 return;
1521
1522
1523
1524
1525
1526 if (hpriv->saved_iocfg & (1 << 18)) {
1527 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1528 pci_write_config_dword(pdev, PIIX_IOCFG,
1529 hpriv->saved_iocfg & ~(1 << 18));
1530 }
1531}
1532
1533static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1534{
1535 static const struct dmi_system_id broken_systems[] = {
1536 {
1537 .ident = "HP Compaq 2510p",
1538 .matches = {
1539 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1540 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1541 },
1542
1543 .driver_data = (void *)0x1FUL,
1544 },
1545 {
1546 .ident = "HP Compaq nc6000",
1547 .matches = {
1548 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1549 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1550 },
1551
1552 .driver_data = (void *)0x1FUL,
1553 },
1554
1555 { }
1556 };
1557 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1558
1559 if (dmi) {
1560 unsigned long slot = (unsigned long)dmi->driver_data;
1561
1562 return slot == PCI_SLOT(pdev->devfn);
1563 }
1564
1565 return false;
1566}
1567
1568static int prefer_ms_hyperv = 1;
1569module_param(prefer_ms_hyperv, int, 0);
1570MODULE_PARM_DESC(prefer_ms_hyperv,
1571 "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1572 "0 - Use ATA drivers, "
1573 "1 (Default) - Use the paravirtualization drivers.");
1574
1575static void piix_ignore_devices_quirk(struct ata_host *host)
1576{
1577#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1578 static const struct dmi_system_id ignore_hyperv[] = {
1579 {
1580
1581
1582
1583
1584
1585
1586 .ident = "Hyper-V Virtual Machine",
1587 .matches = {
1588 DMI_MATCH(DMI_SYS_VENDOR,
1589 "Microsoft Corporation"),
1590 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1591 },
1592 },
1593 { }
1594 };
1595 static const struct dmi_system_id allow_virtual_pc[] = {
1596 {
1597
1598
1599
1600
1601
1602
1603 .ident = "MS Virtual PC 2007",
1604 .matches = {
1605 DMI_MATCH(DMI_SYS_VENDOR,
1606 "Microsoft Corporation"),
1607 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1608 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1609 },
1610 },
1611 { }
1612 };
1613 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1614 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1615
1616 if (ignore && !allow && prefer_ms_hyperv) {
1617 host->flags |= ATA_HOST_IGNORE_ATA;
1618 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1619 ignore->ident);
1620 }
1621#endif
1622}
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1640{
1641 struct device *dev = &pdev->dev;
1642 struct ata_port_info port_info[2];
1643 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1644 struct scsi_host_template *sht = &piix_sht;
1645 unsigned long port_flags;
1646 struct ata_host *host;
1647 struct piix_host_priv *hpriv;
1648 int rc;
1649
1650 ata_print_version_once(&pdev->dev, DRV_VERSION);
1651
1652
1653 if (!in_module_init && ent->driver_data >= ich5_sata)
1654 return -ENODEV;
1655
1656 if (piix_broken_system_poweroff(pdev)) {
1657 piix_port_info[ent->driver_data].flags |=
1658 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1659 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1660 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1661 "on poweroff and hibernation\n");
1662 }
1663
1664 port_info[0] = piix_port_info[ent->driver_data];
1665 port_info[1] = piix_port_info[ent->driver_data];
1666
1667 port_flags = port_info[0].flags;
1668
1669
1670 rc = pcim_enable_device(pdev);
1671 if (rc)
1672 return rc;
1673
1674 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1675 if (!hpriv)
1676 return -ENOMEM;
1677
1678
1679
1680
1681
1682
1683 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1684
1685
1686
1687
1688
1689 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1690 rc = piix_disable_ahci(pdev);
1691 if (rc)
1692 return rc;
1693 }
1694
1695
1696 if (port_flags & ATA_FLAG_SATA)
1697 hpriv->map = piix_init_sata_map(pdev, port_info,
1698 piix_map_db_table[ent->driver_data]);
1699
1700 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1701 if (rc)
1702 return rc;
1703 host->private_data = hpriv;
1704
1705
1706 if (port_flags & ATA_FLAG_SATA) {
1707 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1708 rc = piix_init_sidpr(host);
1709 if (rc)
1710 return rc;
1711 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1712 sht = &piix_sidpr_sht;
1713 }
1714
1715
1716 piix_iocfg_bit18_quirk(host);
1717
1718
1719
1720
1721
1722
1723
1724 if (port_flags & PIIX_FLAG_CHECKINTR)
1725 pci_intx(pdev, 1);
1726
1727 if (piix_check_450nx_errata(pdev)) {
1728
1729
1730
1731 host->ports[0]->mwdma_mask = 0;
1732 host->ports[0]->udma_mask = 0;
1733 host->ports[1]->mwdma_mask = 0;
1734 host->ports[1]->udma_mask = 0;
1735 }
1736 host->flags |= ATA_HOST_PARALLEL_SCAN;
1737
1738
1739 piix_ignore_devices_quirk(host);
1740
1741 pci_set_master(pdev);
1742 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1743}
1744
1745static void piix_remove_one(struct pci_dev *pdev)
1746{
1747 struct ata_host *host = pci_get_drvdata(pdev);
1748 struct piix_host_priv *hpriv = host->private_data;
1749
1750 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1751
1752 ata_pci_remove_one(pdev);
1753}
1754
1755static struct pci_driver piix_pci_driver = {
1756 .name = DRV_NAME,
1757 .id_table = piix_pci_tbl,
1758 .probe = piix_init_one,
1759 .remove = piix_remove_one,
1760#ifdef CONFIG_PM_SLEEP
1761 .suspend = piix_pci_device_suspend,
1762 .resume = piix_pci_device_resume,
1763#endif
1764};
1765
1766static int __init piix_init(void)
1767{
1768 int rc;
1769
1770 DPRINTK("pci_register_driver\n");
1771 rc = pci_register_driver(&piix_pci_driver);
1772 if (rc)
1773 return rc;
1774
1775 in_module_init = 0;
1776
1777 DPRINTK("done\n");
1778 return 0;
1779}
1780
1781static void __exit piix_exit(void)
1782{
1783 pci_unregister_driver(&piix_pci_driver);
1784}
1785
1786module_init(piix_init);
1787module_exit(piix_exit);
1788
