LXR linux/drivers/ata/pata

   1/*
   2 *      pata_hpt3x3             -       HPT3x3 driver
   3 *      (c) Copyright 2005-2006 Red Hat
   4 *
   5 *      Was pata_hpt34x but the naming was confusing as it supported the
   6 *      343 and 363 so it has been renamed.
   7 *
   8 *      Based on:
   9 *      linux/drivers/ide/pci/hpt34x.c          Version 0.40    Sept 10, 2002
  10 *      Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  11 *
  12 *      May be copied or modified under the terms of the GNU General Public
  13 *      License
  14 */
  15
  16#include <linux/kernel.h>
  17#include <linux/module.h>
  18#include <linux/pci.h>
  19#include <linux/blkdev.h>
  20#include <linux/delay.h>
  21#include <scsi/scsi_host.h>
  22#include <linux/libata.h>
  23
  24#define DRV_NAME        "pata_hpt3x3"
  25#define DRV_VERSION     "0.6.1"
  26
  27/**
  28 *      hpt3x3_set_piomode              -       PIO setup
  29 *      @ap: ATA interface
  30 *      @adev: device on the interface
  31 *
  32 *      Set our PIO requirements. This is fairly simple on the HPT3x3 as
  33 *      all we have to do is clear the MWDMA and UDMA bits then load the
  34 *      mode number.
  35 */
  36
  37static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
  38{
  39        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  40        u32 r1, r2;
  41        int dn = 2 * ap->port_no + adev->devno;
  42
  43        pci_read_config_dword(pdev, 0x44, &r1);
  44        pci_read_config_dword(pdev, 0x48, &r2);
  45        /* Load the PIO timing number */
  46        r1 &= ~(7 << (3 * dn));
  47        r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
  48        r2 &= ~(0x11 << dn);    /* Clear MWDMA and UDMA bits */
  49
  50        pci_write_config_dword(pdev, 0x44, r1);
  51        pci_write_config_dword(pdev, 0x48, r2);
  52}
  53
  54#if defined(CONFIG_PATA_HPT3X3_DMA)
  55/**
  56 *      hpt3x3_set_dmamode              -       DMA timing setup
  57 *      @ap: ATA interface
  58 *      @adev: Device being configured
  59 *
  60 *      Set up the channel for MWDMA or UDMA modes. Much the same as with
  61 *      PIO, load the mode number and then set MWDMA or UDMA flag.
  62 *
  63 *      0x44 : bit 0-2 master mode, 3-5 slave mode, etc
  64 *      0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
  65 */
  66
  67static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  68{
  69        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  70        u32 r1, r2;
  71        int dn = 2 * ap->port_no + adev->devno;
  72        int mode_num = adev->dma_mode & 0x0F;
  73
  74        pci_read_config_dword(pdev, 0x44, &r1);
  75        pci_read_config_dword(pdev, 0x48, &r2);
  76        /* Load the timing number */
  77        r1 &= ~(7 << (3 * dn));
  78        r1 |= (mode_num << (3 * dn));
  79        r2 &= ~(0x11 << dn);    /* Clear MWDMA and UDMA bits */
  80
  81        if (adev->dma_mode >= XFER_UDMA_0)
  82                r2 |= (0x01 << dn);     /* Ultra mode */
  83        else
  84                r2 |= (0x10 << dn);     /* MWDMA */
  85
  86        pci_write_config_dword(pdev, 0x44, r1);
  87        pci_write_config_dword(pdev, 0x48, r2);
  88}
  89
  90/**
  91 *      hpt3x3_freeze           -       DMA workaround
  92 *      @ap: port to freeze
  93 *
  94 *      When freezing an HPT3x3 we must stop any pending DMA before
  95 *      writing to the control register or the chip will hang
  96 */
  97
  98static void hpt3x3_freeze(struct ata_port *ap)
  99{
 100        void __iomem *mmio = ap->ioaddr.bmdma_addr;
 101
 102        iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START,
 103                        mmio + ATA_DMA_CMD);
 104        ata_sff_dma_pause(ap);
 105        ata_sff_freeze(ap);
 106}
 107
 108/**
 109 *      hpt3x3_bmdma_setup      -       DMA workaround
 110 *      @qc: Queued command
 111 *
 112 *      When issuing BMDMA we must clean up the error/active bits in
 113 *      software on this device
 114 */
 115
 116static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc)
 117{
 118        struct ata_port *ap = qc->ap;
 119        u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
 120        r |= ATA_DMA_INTR | ATA_DMA_ERR;
 121        iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
 122        return ata_bmdma_setup(qc);
 123}
 124
 125/**
 126 *      hpt3x3_atapi_dma        -       ATAPI DMA check
 127 *      @qc: Queued command
 128 *
 129 *      Just say no - we don't do ATAPI DMA
 130 */
 131
 132static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
 133{
 134        return 1;
 135}
 136
 137#endif /* CONFIG_PATA_HPT3X3_DMA */
 138
 139static struct scsi_host_template hpt3x3_sht = {
 140        ATA_BMDMA_SHT(DRV_NAME),
 141};
 142
 143static struct ata_port_operations hpt3x3_port_ops = {
 144        .inherits       = &ata_bmdma_port_ops,
 145        .cable_detect   = ata_cable_40wire,
 146        .set_piomode    = hpt3x3_set_piomode,
 147#if defined(CONFIG_PATA_HPT3X3_DMA)
 148        .set_dmamode    = hpt3x3_set_dmamode,
 149        .bmdma_setup    = hpt3x3_bmdma_setup,
 150        .check_atapi_dma= hpt3x3_atapi_dma,
 151        .freeze         = hpt3x3_freeze,
 152#endif
 153
 154};
 155
 156/**
 157 *      hpt3x3_init_chipset     -       chip setup
 158 *      @dev: PCI device
 159 *
 160 *      Perform the setup required at boot and on resume.
 161 */
 162
 163static void hpt3x3_init_chipset(struct pci_dev *dev)
 164{
 165        u16 cmd;
 166        /* Initialize the board */
 167        pci_write_config_word(dev, 0x80, 0x00);
 168        /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
 169        pci_read_config_word(dev, PCI_COMMAND, &cmd);
 170        if (cmd & PCI_COMMAND_MEMORY)
 171                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
 172        else
 173                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
 174}
 175
 176/**
 177 *      hpt3x3_init_one         -       Initialise an HPT343/363
 178 *      @pdev: PCI device
 179 *      @id: Entry in match table
 180 *
 181 *      Perform basic initialisation. We set the device up so we access all
 182 *      ports via BAR4. This is necessary to work around errata.
 183 */
 184
 185static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 186{
 187        static const struct ata_port_info info = {
 188                .flags = ATA_FLAG_SLAVE_POSS,
 189                .pio_mask = ATA_PIO4,
 190#if defined(CONFIG_PATA_HPT3X3_DMA)
 191                /* Further debug needed */
 192                .mwdma_mask = ATA_MWDMA2,
 193                .udma_mask = ATA_UDMA2,
 194#endif
 195                .port_ops = &hpt3x3_port_ops
 196        };
 197        /* Register offsets of taskfiles in BAR4 area */
 198        static const u8 offset_cmd[2] = { 0x20, 0x28 };
 199        static const u8 offset_ctl[2] = { 0x36, 0x3E };
 200        const struct ata_port_info *ppi[] = { &info, NULL };
 201        struct ata_host *host;
 202        int i, rc;
 203        void __iomem *base;
 204
 205        hpt3x3_init_chipset(pdev);
 206
 207        ata_print_version_once(&pdev->dev, DRV_VERSION);
 208
 209        host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
 210        if (!host)
 211                return -ENOMEM;
 212        /* acquire resources and fill host */
 213        rc = pcim_enable_device(pdev);
 214        if (rc)
 215                return rc;
 216
 217        /* Everything is relative to BAR4 if we set up this way */
 218        rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
 219        if (rc == -EBUSY)
 220                pcim_pin_device(pdev);
 221        if (rc)
 222                return rc;
 223        host->iomap = pcim_iomap_table(pdev);
 224        rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
 225        if (rc)
 226                return rc;
 227
 228        base = host->iomap[4];  /* Bus mastering base */
 229
 230        for (i = 0; i < host->n_ports; i++) {
 231                struct ata_port *ap = host->ports[i];
 232                struct ata_ioports *ioaddr = &ap->ioaddr;
 233
 234                ioaddr->cmd_addr = base + offset_cmd[i];
 235                ioaddr->altstatus_addr =
 236                ioaddr->ctl_addr = base + offset_ctl[i];
 237                ioaddr->scr_addr = NULL;
 238                ata_sff_std_ports(ioaddr);
 239                ioaddr->bmdma_addr = base + 8 * i;
 240
 241                ata_port_pbar_desc(ap, 4, -1, "ioport");
 242                ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
 243        }
 244        pci_set_master(pdev);
 245        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 246                                 IRQF_SHARED, &hpt3x3_sht);
 247}
 248
 249#ifdef CONFIG_PM_SLEEP
 250static int hpt3x3_reinit_one(struct pci_dev *dev)
 251{
 252        struct ata_host *host = pci_get_drvdata(dev);
 253        int rc;
 254
 255        rc = ata_pci_device_do_resume(dev);
 256        if (rc)
 257                return rc;
 258
 259        hpt3x3_init_chipset(dev);
 260
 261        ata_host_resume(host);
 262        return 0;
 263}
 264#endif
 265
 266static const struct pci_device_id hpt3x3[] = {
 267        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
 268
 269        { },
 270};
 271
 272static struct pci_driver hpt3x3_pci_driver = {
 273        .name           = DRV_NAME,
 274        .id_table       = hpt3x3,
 275        .probe          = hpt3x3_init_one,
 276        .remove         = ata_pci_remove_one,
 277#ifdef CONFIG_PM_SLEEP
 278        .suspend        = ata_pci_device_suspend,
 279        .resume         = hpt3x3_reinit_one,
 280#endif
 281};
 282
 283module_pci_driver(hpt3x3_pci_driver);
 284
 285MODULE_AUTHOR("Alan Cox");
 286MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
 287MODULE_LICENSE("GPL");
 288MODULE_DEVICE_TABLE(pci, hpt3x3);
 289MODULE_VERSION(DRV_VERSION);
 290