LXR linux/drivers/ata/pata

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *  pata_rdc            -       Driver for later RDC PATA controllers
   4 *
   5 *  This is actually a driver for hardware meeting
   6 *  INCITS 370-2004 (1510D): ATA Host Adapter Standards
   7 *
   8 *  Based on ata_piix.
   9 */
  10
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13#include <linux/pci.h>
  14#include <linux/blkdev.h>
  15#include <linux/delay.h>
  16#include <linux/device.h>
  17#include <linux/gfp.h>
  18#include <scsi/scsi_host.h>
  19#include <linux/libata.h>
  20#include <linux/dmi.h>
  21
  22#define DRV_NAME        "pata_rdc"
  23#define DRV_VERSION     "0.01"
  24
  25struct rdc_host_priv {
  26        u32 saved_iocfg;
  27};
  28
  29/**
  30 *      rdc_pata_cable_detect - Probe host controller cable detect info
  31 *      @ap: Port for which cable detect info is desired
  32 *
  33 *      Read 80c cable indicator from ATA PCI device's PCI config
  34 *      register.  This register is normally set by firmware (BIOS).
  35 *
  36 *      LOCKING:
  37 *      None (inherited from caller).
  38 */
  39
  40static int rdc_pata_cable_detect(struct ata_port *ap)
  41{
  42        struct rdc_host_priv *hpriv = ap->host->private_data;
  43        u8 mask;
  44
  45        /* check BIOS cable detect results */
  46        mask = 0x30 << (2 * ap->port_no);
  47        if ((hpriv->saved_iocfg & mask) == 0)
  48                return ATA_CBL_PATA40;
  49        return ATA_CBL_PATA80;
  50}
  51
  52/**
  53 *      rdc_pata_prereset - prereset for PATA host controller
  54 *      @link: Target link
  55 *      @deadline: deadline jiffies for the operation
  56 *
  57 *      LOCKING:
  58 *      None (inherited from caller).
  59 */
  60static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
  61{
  62        struct ata_port *ap = link->ap;
  63        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  64
  65        static const struct pci_bits rdc_enable_bits[] = {
  66                { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
  67                { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
  68        };
  69
  70        if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no]))
  71                return -ENOENT;
  72        return ata_sff_prereset(link, deadline);
  73}
  74
  75static DEFINE_SPINLOCK(rdc_lock);
  76
  77/**
  78 *      rdc_set_piomode - Initialize host controller PATA PIO timings
  79 *      @ap: Port whose timings we are configuring
  80 *      @adev: um
  81 *
  82 *      Set PIO mode for device, in host controller PCI config space.
  83 *
  84 *      LOCKING:
  85 *      None (inherited from caller).
  86 */
  87
  88static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
  89{
  90        unsigned int pio        = adev->pio_mode - XFER_PIO_0;
  91        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
  92        unsigned long flags;
  93        unsigned int is_slave   = (adev->devno != 0);
  94        unsigned int master_port= ap->port_no ? 0x42 : 0x40;
  95        unsigned int slave_port = 0x44;
  96        u16 master_data;
  97        u8 slave_data;
  98        u8 udma_enable;
  99        int control = 0;
 100
 101        static const     /* ISP  RTC */
 102        u8 timings[][2] = { { 0, 0 },
 103                            { 0, 0 },
 104                            { 1, 0 },
 105                            { 2, 1 },
 106                            { 2, 3 }, };
 107
 108        if (pio >= 2)
 109                control |= 1;   /* TIME1 enable */
 110        if (ata_pio_need_iordy(adev))
 111                control |= 2;   /* IE enable */
 112
 113        if (adev->class == ATA_DEV_ATA)
 114                control |= 4;   /* PPE enable */
 115
 116        spin_lock_irqsave(&rdc_lock, flags);
 117
 118        /* PIO configuration clears DTE unconditionally.  It will be
 119         * programmed in set_dmamode which is guaranteed to be called
 120         * after set_piomode if any DMA mode is available.
 121         */
 122        pci_read_config_word(dev, master_port, &master_data);
 123        if (is_slave) {
 124                /* clear TIME1|IE1|PPE1|DTE1 */
 125                master_data &= 0xff0f;
 126                /* Enable SITRE (separate slave timing register) */
 127                master_data |= 0x4000;
 128                /* enable PPE1, IE1 and TIME1 as needed */
 129                master_data |= (control << 4);
 130                pci_read_config_byte(dev, slave_port, &slave_data);
 131                slave_data &= (ap->port_no ? 0x0f : 0xf0);
 132                /* Load the timing nibble for this slave */
 133                slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
 134                                                << (ap->port_no ? 4 : 0);
 135        } else {
 136                /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
 137                master_data &= 0xccf0;
 138                /* Enable PPE, IE and TIME as appropriate */
 139                master_data |= control;
 140                /* load ISP and RCT */
 141                master_data |=
 142                        (timings[pio][0] << 12) |
 143                        (timings[pio][1] << 8);
 144        }
 145        pci_write_config_word(dev, master_port, master_data);
 146        if (is_slave)
 147                pci_write_config_byte(dev, slave_port, slave_data);
 148
 149        /* Ensure the UDMA bit is off - it will be turned back on if
 150           UDMA is selected */
 151
 152        pci_read_config_byte(dev, 0x48, &udma_enable);
 153        udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 154        pci_write_config_byte(dev, 0x48, udma_enable);
 155
 156        spin_unlock_irqrestore(&rdc_lock, flags);
 157}
 158
 159/**
 160 *      rdc_set_dmamode - Initialize host controller PATA PIO timings
 161 *      @ap: Port whose timings we are configuring
 162 *      @adev: Drive in question
 163 *
 164 *      Set UDMA mode for device, in host controller PCI config space.
 165 *
 166 *      LOCKING:
 167 *      None (inherited from caller).
 168 */
 169
 170static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 171{
 172        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 173        unsigned long flags;
 174        u8 master_port          = ap->port_no ? 0x42 : 0x40;
 175        u16 master_data;
 176        u8 speed                = adev->dma_mode;
 177        int devid               = adev->devno + 2 * ap->port_no;
 178        u8 udma_enable          = 0;
 179
 180        static const     /* ISP  RTC */
 181        u8 timings[][2] = { { 0, 0 },
 182                            { 0, 0 },
 183                            { 1, 0 },
 184                            { 2, 1 },
 185                            { 2, 3 }, };
 186
 187        spin_lock_irqsave(&rdc_lock, flags);
 188
 189        pci_read_config_word(dev, master_port, &master_data);
 190        pci_read_config_byte(dev, 0x48, &udma_enable);
 191
 192        if (speed >= XFER_UDMA_0) {
 193                unsigned int udma = adev->dma_mode - XFER_UDMA_0;
 194                u16 udma_timing;
 195                u16 ideconf;
 196                int u_clock, u_speed;
 197
 198                /*
 199                 * UDMA is handled by a combination of clock switching and
 200                 * selection of dividers
 201                 *
 202                 * Handy rule: Odd modes are UDMATIMx 01, even are 02
 203                 *             except UDMA0 which is 00
 204                 */
 205                u_speed = min(2 - (udma & 1), udma);
 206                if (udma == 5)
 207                        u_clock = 0x1000;       /* 100Mhz */
 208                else if (udma > 2)
 209                        u_clock = 1;            /* 66Mhz */
 210                else
 211                        u_clock = 0;            /* 33Mhz */
 212
 213                udma_enable |= (1 << devid);
 214
 215                /* Load the CT/RP selection */
 216                pci_read_config_word(dev, 0x4A, &udma_timing);
 217                udma_timing &= ~(3 << (4 * devid));
 218                udma_timing |= u_speed << (4 * devid);
 219                pci_write_config_word(dev, 0x4A, udma_timing);
 220
 221                /* Select a 33/66/100Mhz clock */
 222                pci_read_config_word(dev, 0x54, &ideconf);
 223                ideconf &= ~(0x1001 << devid);
 224                ideconf |= u_clock << devid;
 225                pci_write_config_word(dev, 0x54, ideconf);
 226        } else {
 227                /*
 228                 * MWDMA is driven by the PIO timings. We must also enable
 229                 * IORDY unconditionally along with TIME1. PPE has already
 230                 * been set when the PIO timing was set.
 231                 */
 232                unsigned int mwdma      = adev->dma_mode - XFER_MW_DMA_0;
 233                unsigned int control;
 234                u8 slave_data;
 235                const unsigned int needed_pio[3] = {
 236                        XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 237                };
 238                int pio = needed_pio[mwdma] - XFER_PIO_0;
 239
 240                control = 3;    /* IORDY|TIME1 */
 241
 242                /* If the drive MWDMA is faster than it can do PIO then
 243                   we must force PIO into PIO0 */
 244
 245                if (adev->pio_mode < needed_pio[mwdma])
 246                        /* Enable DMA timing only */
 247                        control |= 8;   /* PIO cycles in PIO0 */
 248
 249                if (adev->devno) {      /* Slave */
 250                        master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
 251                        master_data |= control << 4;
 252                        pci_read_config_byte(dev, 0x44, &slave_data);
 253                        slave_data &= (ap->port_no ? 0x0f : 0xf0);
 254                        /* Load the matching timing */
 255                        slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
 256                        pci_write_config_byte(dev, 0x44, slave_data);
 257                } else {        /* Master */
 258                        master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
 259                                                   and master timing bits */
 260                        master_data |= control;
 261                        master_data |=
 262                                (timings[pio][0] << 12) |
 263                                (timings[pio][1] << 8);
 264                }
 265
 266                udma_enable &= ~(1 << devid);
 267                pci_write_config_word(dev, master_port, master_data);
 268        }
 269        pci_write_config_byte(dev, 0x48, udma_enable);
 270
 271        spin_unlock_irqrestore(&rdc_lock, flags);
 272}
 273
 274static struct ata_port_operations rdc_pata_ops = {
 275        .inherits               = &ata_bmdma32_port_ops,
 276        .cable_detect           = rdc_pata_cable_detect,
 277        .set_piomode            = rdc_set_piomode,
 278        .set_dmamode            = rdc_set_dmamode,
 279        .prereset               = rdc_pata_prereset,
 280};
 281
 282static const struct ata_port_info rdc_port_info = {
 283
 284        .flags          = ATA_FLAG_SLAVE_POSS,
 285        .pio_mask       = ATA_PIO4,
 286        .mwdma_mask     = ATA_MWDMA12_ONLY,
 287        .udma_mask      = ATA_UDMA5,
 288        .port_ops       = &rdc_pata_ops,
 289};
 290
 291static struct scsi_host_template rdc_sht = {
 292        ATA_BMDMA_SHT(DRV_NAME),
 293};
 294
 295/**
 296 *      rdc_init_one - Register PIIX ATA PCI device with kernel services
 297 *      @pdev: PCI device to register
 298 *      @ent: Entry in rdc_pci_tbl matching with @pdev
 299 *
 300 *      Called from kernel PCI layer.  We probe for combined mode (sigh),
 301 *      and then hand over control to libata, for it to do the rest.
 302 *
 303 *      LOCKING:
 304 *      Inherited from PCI layer (may sleep).
 305 *
 306 *      RETURNS:
 307 *      Zero on success, or -ERRNO value.
 308 */
 309
 310static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 311{
 312        struct device *dev = &pdev->dev;
 313        struct ata_port_info port_info[2];
 314        const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
 315        struct ata_host *host;
 316        struct rdc_host_priv *hpriv;
 317        int rc;
 318
 319        ata_print_version_once(&pdev->dev, DRV_VERSION);
 320
 321        port_info[0] = rdc_port_info;
 322        port_info[1] = rdc_port_info;
 323
 324        /* enable device and prepare host */
 325        rc = pcim_enable_device(pdev);
 326        if (rc)
 327                return rc;
 328
 329        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
 330        if (!hpriv)
 331                return -ENOMEM;
 332
 333        /* Save IOCFG, this will be used for cable detection, quirk
 334         * detection and restoration on detach.
 335         */
 336        pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg);
 337
 338        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
 339        if (rc)
 340                return rc;
 341        host->private_data = hpriv;
 342
 343        pci_intx(pdev, 1);
 344
 345        host->flags |= ATA_HOST_PARALLEL_SCAN;
 346
 347        pci_set_master(pdev);
 348        return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht);
 349}
 350
 351static void rdc_remove_one(struct pci_dev *pdev)
 352{
 353        struct ata_host *host = pci_get_drvdata(pdev);
 354        struct rdc_host_priv *hpriv = host->private_data;
 355
 356        pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg);
 357
 358        ata_pci_remove_one(pdev);
 359}
 360
 361static const struct pci_device_id rdc_pci_tbl[] = {
 362        { PCI_DEVICE(0x17F3, 0x1011), },
 363        { PCI_DEVICE(0x17F3, 0x1012), },
 364        { }     /* terminate list */
 365};
 366
 367static struct pci_driver rdc_pci_driver = {
 368        .name                   = DRV_NAME,
 369        .id_table               = rdc_pci_tbl,
 370        .probe                  = rdc_init_one,
 371        .remove                 = rdc_remove_one,
 372#ifdef CONFIG_PM_SLEEP
 373        .suspend                = ata_pci_device_suspend,
 374        .resume                 = ata_pci_device_resume,
 375#endif
 376};
 377
 378
 379module_pci_driver(rdc_pci_driver);
 380
 381MODULE_AUTHOR("Alan Cox (based on ata_piix)");
 382MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers");
 383MODULE_LICENSE("GPL");
 384MODULE_DEVICE_TABLE(pci, rdc_pci_tbl);
 385MODULE_VERSION(DRV_VERSION);
 386