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25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <scsi/scsi_host.h>
31#include <linux/libata.h>
32
33#define DRV_NAME "pata_sil680"
34#define DRV_VERSION "0.4.9"
35
36#define SIL680_MMIO_BAR 5
37
38
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48
49
50static unsigned long sil680_selreg(struct ata_port *ap, int r)
51{
52 unsigned long base = 0xA0 + r;
53 base += (ap->port_no << 4);
54 return base;
55}
56
57
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59
60
61
62
63
64
65
66
67
68static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
69{
70 unsigned long base = 0xA0 + r;
71 base += (ap->port_no << 4);
72 base |= adev->devno ? 2 : 0;
73 return base;
74}
75
76
77
78
79
80
81
82
83
84
85static int sil680_cable_detect(struct ata_port *ap)
86{
87 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
88 unsigned long addr = sil680_selreg(ap, 0);
89 u8 ata66;
90 pci_read_config_byte(pdev, addr, &ata66);
91 if (ata66 & 1)
92 return ATA_CBL_PATA80;
93 else
94 return ATA_CBL_PATA40;
95}
96
97
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103
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105
106
107static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
108{
109 static const u16 speed_p[5] = {
110 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1
111 };
112 static const u16 speed_t[5] = {
113 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
114 };
115
116 unsigned long tfaddr = sil680_selreg(ap, 0x02);
117 unsigned long addr = sil680_seldev(ap, adev, 0x04);
118 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
119 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
120 int pio = adev->pio_mode - XFER_PIO_0;
121 int lowest_pio = pio;
122 int port_shift = 4 * adev->devno;
123 u16 reg;
124 u8 mode;
125
126 struct ata_device *pair = ata_dev_pair(adev);
127
128 if (pair != NULL && adev->pio_mode > pair->pio_mode)
129 lowest_pio = pair->pio_mode - XFER_PIO_0;
130
131 pci_write_config_word(pdev, addr, speed_p[pio]);
132 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
133
134 pci_read_config_word(pdev, tfaddr-2, ®);
135 pci_read_config_byte(pdev, addr_mask, &mode);
136
137 reg &= ~0x0200;
138 mode &= ~(3 << port_shift);
139
140 if (ata_pio_need_iordy(adev)) {
141 reg |= 0x0200;
142 mode |= 1 << port_shift;
143 }
144 pci_write_config_word(pdev, tfaddr-2, reg);
145 pci_write_config_byte(pdev, addr_mask, mode);
146}
147
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158
159static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
160{
161 static const u8 ultra_table[2][7] = {
162 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },
163 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },
164 };
165 static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
166
167 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
168 unsigned long ma = sil680_seldev(ap, adev, 0x08);
169 unsigned long ua = sil680_seldev(ap, adev, 0x0C);
170 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
171 int port_shift = adev->devno * 4;
172 u8 scsc, mode;
173 u16 multi, ultra;
174
175 pci_read_config_byte(pdev, 0x8A, &scsc);
176 pci_read_config_byte(pdev, addr_mask, &mode);
177 pci_read_config_word(pdev, ma, &multi);
178 pci_read_config_word(pdev, ua, &ultra);
179
180
181 ultra &= ~0x3F;
182 mode &= ~(0x03 << port_shift);
183
184
185 scsc = (scsc & 0x30) ? 1 : 0;
186
187 if (adev->dma_mode >= XFER_UDMA_0) {
188 multi = 0x10C1;
189 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
190 mode |= (0x03 << port_shift);
191 } else {
192 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
193 mode |= (0x02 << port_shift);
194 }
195 pci_write_config_byte(pdev, addr_mask, mode);
196 pci_write_config_word(pdev, ma, multi);
197 pci_write_config_word(pdev, ua, ultra);
198}
199
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210
211
212static void sil680_sff_exec_command(struct ata_port *ap,
213 const struct ata_taskfile *tf)
214{
215 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
216 iowrite8(tf->command, ap->ioaddr.command_addr);
217 ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
218}
219
220static bool sil680_sff_irq_check(struct ata_port *ap)
221{
222 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
223 unsigned long addr = sil680_selreg(ap, 1);
224 u8 val;
225
226 pci_read_config_byte(pdev, addr, &val);
227
228 return val & 0x08;
229}
230
231static struct scsi_host_template sil680_sht = {
232 ATA_BMDMA_SHT(DRV_NAME),
233};
234
235
236static struct ata_port_operations sil680_port_ops = {
237 .inherits = &ata_bmdma32_port_ops,
238 .sff_exec_command = sil680_sff_exec_command,
239 .sff_irq_check = sil680_sff_irq_check,
240 .cable_detect = sil680_cable_detect,
241 .set_piomode = sil680_set_piomode,
242 .set_dmamode = sil680_set_dmamode,
243};
244
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253
254
255static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
256{
257 u8 tmpbyte = 0;
258
259
260 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
261 pdev->revision ? 1 : 255);
262
263 pci_write_config_byte(pdev, 0x80, 0x00);
264 pci_write_config_byte(pdev, 0x84, 0x00);
265
266 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
267
268 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
269 tmpbyte & 1, tmpbyte & 0x30);
270
271 *try_mmio = 0;
272#ifdef CONFIG_PPC
273 if (machine_is(cell))
274 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
275#endif
276
277 switch (tmpbyte & 0x30) {
278 case 0x00:
279
280 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
281 break;
282 case 0x30:
283
284
285 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
286 break;
287 case 0x10:
288
289 break;
290 case 0x20:
291
292 break;
293 }
294
295 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
296 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
297 tmpbyte & 1, tmpbyte & 0x30);
298
299 pci_write_config_byte(pdev, 0xA1, 0x72);
300 pci_write_config_word(pdev, 0xA2, 0x328A);
301 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
302 pci_write_config_dword(pdev, 0xA8, 0x43924392);
303 pci_write_config_dword(pdev, 0xAC, 0x40094009);
304 pci_write_config_byte(pdev, 0xB1, 0x72);
305 pci_write_config_word(pdev, 0xB2, 0x328A);
306 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
307 pci_write_config_dword(pdev, 0xB8, 0x43924392);
308 pci_write_config_dword(pdev, 0xBC, 0x40094009);
309
310 switch (tmpbyte & 0x30) {
311 case 0x00:
312 printk(KERN_INFO "sil680: 100MHz clock.\n");
313 break;
314 case 0x10:
315 printk(KERN_INFO "sil680: 133MHz clock.\n");
316 break;
317 case 0x20:
318 printk(KERN_INFO "sil680: Using PCI clock.\n");
319 break;
320
321 case 0x30:
322 printk(KERN_ERR "sil680: Clock disabled ?\n");
323 }
324 return tmpbyte & 0x30;
325}
326
327static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
328{
329 static const struct ata_port_info info = {
330 .flags = ATA_FLAG_SLAVE_POSS,
331 .pio_mask = ATA_PIO4,
332 .mwdma_mask = ATA_MWDMA2,
333 .udma_mask = ATA_UDMA6,
334 .port_ops = &sil680_port_ops
335 };
336 static const struct ata_port_info info_slow = {
337 .flags = ATA_FLAG_SLAVE_POSS,
338 .pio_mask = ATA_PIO4,
339 .mwdma_mask = ATA_MWDMA2,
340 .udma_mask = ATA_UDMA5,
341 .port_ops = &sil680_port_ops
342 };
343 const struct ata_port_info *ppi[] = { &info, NULL };
344 struct ata_host *host;
345 void __iomem *mmio_base;
346 int rc, try_mmio;
347
348 ata_print_version_once(&pdev->dev, DRV_VERSION);
349
350 rc = pcim_enable_device(pdev);
351 if (rc)
352 return rc;
353
354 switch (sil680_init_chip(pdev, &try_mmio)) {
355 case 0:
356 ppi[0] = &info_slow;
357 break;
358 case 0x30:
359 return -ENODEV;
360 }
361
362 if (!try_mmio)
363 goto use_ioports;
364
365
366
367
368 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
369 if (rc)
370 goto use_ioports;
371
372
373 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
374 if (!host)
375 return -ENOMEM;
376 host->iomap = pcim_iomap_table(pdev);
377
378
379 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
380 if (rc)
381 return rc;
382 pci_set_master(pdev);
383
384
385 mmio_base = host->iomap[SIL680_MMIO_BAR];
386 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
387 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
388 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
389 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
390 ata_sff_std_ports(&host->ports[0]->ioaddr);
391 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
392 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
393 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
394 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
395 ata_sff_std_ports(&host->ports[1]->ioaddr);
396
397
398 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
399 IRQF_SHARED, &sil680_sht);
400
401use_ioports:
402 return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
403}
404
405#ifdef CONFIG_PM_SLEEP
406static int sil680_reinit_one(struct pci_dev *pdev)
407{
408 struct ata_host *host = pci_get_drvdata(pdev);
409 int try_mmio, rc;
410
411 rc = ata_pci_device_do_resume(pdev);
412 if (rc)
413 return rc;
414 sil680_init_chip(pdev, &try_mmio);
415 ata_host_resume(host);
416 return 0;
417}
418#endif
419
420static const struct pci_device_id sil680[] = {
421 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
422
423 { },
424};
425
426static struct pci_driver sil680_pci_driver = {
427 .name = DRV_NAME,
428 .id_table = sil680,
429 .probe = sil680_init_one,
430 .remove = ata_pci_remove_one,
431#ifdef CONFIG_PM_SLEEP
432 .suspend = ata_pci_device_suspend,
433 .resume = sil680_reinit_one,
434#endif
435};
436
437module_pci_driver(sil680_pci_driver);
438
439MODULE_AUTHOR("Alan Cox");
440MODULE_DESCRIPTION("low-level driver for SI680 PATA");
441MODULE_LICENSE("GPL");
442MODULE_DEVICE_TABLE(pci, sil680);
443MODULE_VERSION(DRV_VERSION);
444