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43#ifndef IPHASE_H
44#define IPHASE_H
45
46
47
48
49#define IF_IADBG_INIT_ADAPTER 0x00000001
50#define IF_IADBG_TX 0x00000002
51#define IF_IADBG_RX 0x00000004
52#define IF_IADBG_QUERY_INFO 0x00000008
53#define IF_IADBG_SHUTDOWN 0x00000010
54#define IF_IADBG_INTR 0x00000020
55#define IF_IADBG_TXPKT 0x00000040
56#define IF_IADBG_RXPKT 0x00000080
57#define IF_IADBG_ERR 0x00000100
58#define IF_IADBG_EVENT 0x00000200
59#define IF_IADBG_DIS_INTR 0x00001000
60#define IF_IADBG_EN_INTR 0x00002000
61#define IF_IADBG_LOUD 0x00004000
62#define IF_IADBG_VERY_LOUD 0x00008000
63#define IF_IADBG_CBR 0x00100000
64#define IF_IADBG_UBR 0x00200000
65#define IF_IADBG_ABR 0x00400000
66#define IF_IADBG_DESC 0x01000000
67#define IF_IADBG_SUNI_STAT 0x02000000
68#define IF_IADBG_RESET 0x04000000
69
70#define IF_IADBG(f) if (IADebugFlag & (f))
71
72#ifdef CONFIG_ATM_IA_DEBUG
73
74#define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
75#define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
76#define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
77
78#define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
79#define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
80#define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
81#define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
82#define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
83
84#define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
85#define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
86#define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
87
88#define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
89#define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
90#define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
91#define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
92
93#define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
94#define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
95#define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
96#define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
97#define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
98
99#else
100#define IF_LOUD(A)
101#define IF_VERY_LOUD(A)
102#define IF_INIT_ADAPTER(A)
103#define IF_INIT(A)
104#define IF_SUNI_STAT(A)
105#define IF_PVC_CHKPKT(A)
106#define IF_QUERY_INFO(A)
107#define IF_COPY_OVER(A)
108#define IF_HANG(A)
109#define IF_INTR(A)
110#define IF_DIS_INTR(A)
111#define IF_EN_INTR(A)
112#define IF_TX(A)
113#define IF_RX(A)
114#define IF_TXDEBUG(A)
115#define IF_VC(A)
116#define IF_ERR(A)
117#define IF_CBR(A)
118#define IF_UBR(A)
119#define IF_ABR(A)
120#define IF_SHUTDOWN(A)
121#define DbgPrint(A)
122#define IF_EVENT(A)
123#define IF_TXPKT(A)
124#define IF_RXPKT(A)
125#endif
126
127#define ATM_DESC(skb) (skb->protocol)
128#define IA_SKB_STATE(skb) (skb->protocol)
129#define IA_DLED 1
130#define IA_TX_DONE 2
131
132
133#define IA_CMD 0x7749
134typedef struct {
135 int cmd;
136 int sub_cmd;
137 int len;
138 u32 maddr;
139 int status;
140 void __user *buf;
141} IA_CMDBUF, *PIA_CMDBUF;
142
143
144#define MEMDUMP 0x01
145
146
147#define MEMDUMP_SEGREG 0x2
148#define MEMDUMP_DEV 0x1
149#define MEMDUMP_REASSREG 0x3
150#define MEMDUMP_FFL 0x4
151#define READ_REG 0x5
152#define WAKE_DBG_WAIT 0x6
153
154
155
156#define Boolean(x) ((x) ? 1 : 0)
157#define NR_VCI 1024
158#define NR_VCI_LD 10
159#define NR_VCI_4K 4096
160#define NR_VCI_4K_LD 12
161#define MEM_VALID 0xfffffff0
162
163#ifndef PCI_VENDOR_ID_IPHASE
164#define PCI_VENDOR_ID_IPHASE 0x107e
165#endif
166#ifndef PCI_DEVICE_ID_IPHASE_5575
167#define PCI_DEVICE_ID_IPHASE_5575 0x0008
168#endif
169#define DEV_LABEL "ia"
170#define PCR 207692
171#define ICR 100000
172#define MCR 0
173#define TBE 1000
174#define FRTT 1
175#define RIF 2
176#define RDF 4
177#define NRMCODE 5
178#define TRMCODE 3
179#define CDFCODE 6
180#define ATDFCODE 2
181
182
183#define TX_PACKET_RAM 0x00000
184#define DFL_TX_BUF_SZ 10240
185#define DFL_TX_BUFFERS 50
186
187#define REASS_RAM_SIZE 0x10000
188#define RX_PACKET_RAM 0x80000
189#define DFL_RX_BUF_SZ 10240
190#define DFL_RX_BUFFERS 50
191
192
193struct cpcs_trailer
194{
195 u_short control;
196 u_short length;
197 u_int crc32;
198};
199
200struct cpcs_trailer_desc
201{
202 struct cpcs_trailer *cpcs;
203 dma_addr_t dma_addr;
204};
205
206struct ia_vcc
207{
208 int rxing;
209 int txing;
210 int NumCbrEntry;
211 u32 pcr;
212 u32 saved_tx_quota;
213 int flow_inc;
214 struct sk_buff_head txing_skb;
215 int ltimeout;
216 u8 vc_desc_cnt;
217
218};
219
220struct abr_vc_table
221{
222 u_char status;
223 u_char rdf;
224 u_short air;
225 u_int res[3];
226 u_int req_rm_cell_data1;
227 u_int req_rm_cell_data2;
228 u_int add_rm_cell_data1;
229 u_int add_rm_cell_data2;
230};
231
232
233struct main_vc
234{
235 u_short type;
236#define ABR 0x8000
237#define UBR 0xc000
238#define CBR 0x0000
239
240 u_short nrm;
241 u_short trm;
242 u_short rm_timestamp_hi;
243 u_short rm_timestamp_lo:8,
244 crm:8;
245 u_short remainder;
246 u_short next_vc_sched;
247 u_short present_desc;
248 u_short last_cell_slot;
249 u_short pcr;
250 u_short fraction;
251 u_short icr;
252 u_short atdf;
253 u_short mcr;
254 u_short acr;
255 u_short unack:8,
256 status:8;
257#define UIOLI 0x80
258#define CRC_APPEND 0x40
259#define ABR_STATE 0x02
260
261};
262
263
264
265struct ext_vc
266{
267 u_short atm_hdr1;
268 u_short atm_hdr2;
269 u_short last_desc;
270 u_short out_of_rate_link;
271};
272
273
274#define DLE_ENTRIES 256
275#define DMA_INT_ENABLE 0x0002
276#define TX_DLE_PSI 0x0001
277#define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
278
279
280struct dle
281{
282 u32 sys_pkt_addr;
283 u32 local_pkt_addr;
284 u32 bytes;
285 u16 prq_wr_ptr_data;
286 u16 mode;
287};
288
289struct dle_q
290{
291 struct dle *start;
292 struct dle *end;
293 struct dle *read;
294 struct dle *write;
295};
296
297struct free_desc_q
298{
299 int desc;
300 struct free_desc_q *next;
301};
302
303struct tx_buf_desc {
304 unsigned short desc_mode;
305 unsigned short vc_index;
306 unsigned short res1;
307 unsigned short bytes;
308 unsigned short buf_start_hi;
309 unsigned short buf_start_lo;
310 unsigned short res2[10];
311};
312
313
314struct rx_buf_desc {
315 unsigned short desc_mode;
316 unsigned short vc_index;
317 unsigned short vpi;
318 unsigned short bytes;
319 unsigned short buf_start_hi;
320 unsigned short buf_start_lo;
321 unsigned short dma_start_hi;
322 unsigned short dma_start_lo;
323 unsigned short crc_upper;
324 unsigned short crc_lower;
325 unsigned short res:8, timeout:8;
326 unsigned short res2[5];
327};
328
329
330
331#define EPROM_SIZE 0x40000
332#define MAC1_LEN 4
333#define MAC2_LEN 2
334
335
336#define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
337#define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000
338#define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
339#define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
340#define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
341#define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE
342#define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
343#define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
344
345
346#define IPHASE5575_BUS_CONTROL_REG 0x00
347#define IPHASE5575_BUS_STATUS_REG 0x01
348#define IPHASE5575_MAC1 0x02
349#define IPHASE5575_REV 0x03
350#define IPHASE5575_MAC2 0x03
351#define IPHASE5575_EXT_RESET 0x04
352#define IPHASE5575_INT_RESET 0x05
353#define IPHASE5575_PCI_ADDR_PAGE 0x07
354#define IPHASE5575_EEPROM_ACCESS 0x0a
355#define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
356#define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
357#define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
358#define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
359#define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f
360
361
362#define CTRL_FE_RST 0x80000000
363#define CTRL_LED 0x40000000
364#define CTRL_25MBPHY 0x10000000
365#define CTRL_ENCMBMEM 0x08000000
366#define CTRL_ENOFFSEG 0x01000000
367#define CTRL_ERRMASK 0x00400000
368#define CTRL_DLETMASK 0x00100000
369#define CTRL_DLERMASK 0x00080000
370#define CTRL_FEMASK 0x00040000
371#define CTRL_SEGMASK 0x00020000
372#define CTRL_REASSMASK 0x00010000
373#define CTRL_CSPREEMPT 0x00002000
374#define CTRL_B128 0x00000200
375#define CTRL_B64 0x00000100
376#define CTRL_B48 0x00000080
377#define CTRL_B32 0x00000040
378#define CTRL_B16 0x00000020
379#define CTRL_B8 0x00000010
380
381
382#define STAT_CMEMSIZ 0xc0000000
383#define STAT_ADPARCK 0x20000000
384#define STAT_RESVD 0x1fffff80
385#define STAT_ERRINT 0x00000040
386#define STAT_MARKINT 0x00000020
387#define STAT_DLETINT 0x00000010
388#define STAT_DLERINT 0x00000008
389#define STAT_FEINT 0x00000004
390#define STAT_SEGINT 0x00000002
391#define STAT_REASSINT 0x00000001
392
393
394
395
396
397#define IDLEHEADHI 0x00
398#define IDLEHEADLO 0x01
399#define MAXRATE 0x02
400
401#define RATE155 0x64b1
402#define MAX_ATM_155 352768
403#define RATE25 0x5f9d
404
405#define STPARMS 0x03
406#define STPARMS_1K 0x008c
407#define STPARMS_2K 0x0049
408#define STPARMS_4K 0x0026
409#define COMP_EN 0x4000
410#define CBR_EN 0x2000
411#define ABR_EN 0x0800
412#define UBR_EN 0x0400
413
414#define ABRUBR_ARB 0x04
415#define RM_TYPE 0x05
416
417#define RM_TYPE_4_0 0x0100
418
419#define SEG_COMMAND_REG 0x17
420
421#define RESET_SEG 0x0055
422#define RESET_SEG_STATE 0x00aa
423#define RESET_TX_CELL_CTR 0x00cc
424
425#define CBR_PTR_BASE 0x20
426#define ABR_SBPTR_BASE 0x22
427#define UBR_SBPTR_BASE 0x23
428#define ABRWQ_BASE 0x26
429#define UBRWQ_BASE 0x27
430#define VCT_BASE 0x28
431#define VCTE_BASE 0x29
432#define CBR_TAB_BEG 0x2c
433#define CBR_TAB_END 0x2d
434#define PRQ_ST_ADR 0x30
435#define PRQ_ED_ADR 0x31
436#define PRQ_RD_PTR 0x32
437#define PRQ_WR_PTR 0x33
438#define TCQ_ST_ADR 0x34
439#define TCQ_ED_ADR 0x35
440#define TCQ_RD_PTR 0x36
441#define TCQ_WR_PTR 0x37
442#define SEG_QUEUE_BASE 0x40
443#define SEG_DESC_BASE 0x41
444#define MODE_REG_0 0x45
445#define T_ONLINE 0x0002
446
447#define MODE_REG_1 0x46
448#define MODE_REG_1_VAL 0x0400
449
450#define SEG_INTR_STATUS_REG 0x47
451#define SEG_MASK_REG 0x48
452#define TRANSMIT_DONE 0x0200
453#define TCQ_NOT_EMPTY 0x1000
454
455
456#define CELL_CTR_HIGH_AUTO 0x49
457#define CELL_CTR_HIGH_NOAUTO 0xc9
458#define CELL_CTR_LO_AUTO 0x4a
459#define CELL_CTR_LO_NOAUTO 0xca
460
461
462#define NEXTDESC 0x59
463#define NEXTVC 0x5a
464#define PSLOTCNT 0x5d
465#define NEWDN 0x6a
466#define NEWVC 0x6b
467#define SBPTR 0x6c
468#define ABRWQ_WRPTR 0x6f
469#define ABRWQ_RDPTR 0x70
470#define UBRWQ_WRPTR 0x71
471#define UBRWQ_RDPTR 0x72
472#define CBR_VC 0x73
473#define ABR_SBVC 0x75
474#define UBR_SBVC 0x76
475#define ABRNEXTLINK 0x78
476#define UBRNEXTLINK 0x79
477
478
479
480
481
482#define MODE_REG 0x00
483#define R_ONLINE 0x0002
484#define IGN_RAW_FL 0x0004
485
486#define PROTOCOL_ID 0x01
487#define REASS_MASK_REG 0x02
488#define REASS_INTR_STATUS_REG 0x03
489
490#define RX_PKT_CTR_OF 0x8000
491#define RX_ERR_CTR_OF 0x4000
492#define RX_CELL_CTR_OF 0x1000
493#define RX_FREEQ_EMPT 0x0200
494#define RX_EXCPQ_FL 0x0080
495#define RX_RAWQ_FL 0x0010
496#define RX_EXCP_RCVD 0x0008
497#define RX_PKT_RCVD 0x0004
498#define RX_RAW_RCVD 0x0001
499
500#define DRP_PKT_CNTR 0x04
501#define ERR_CNTR 0x05
502#define RAW_BASE_ADR 0x08
503#define CELL_CTR0 0x0c
504#define CELL_CTR1 0x0d
505#define REASS_COMMAND_REG 0x0f
506
507#define RESET_REASS 0x0055
508#define RESET_REASS_STATE 0x00aa
509#define RESET_DRP_PKT_CNTR 0x00f1
510#define RESET_ERR_CNTR 0x00f2
511#define RESET_CELL_CNTR 0x00f8
512#define RESET_REASS_ALL_REGS 0x00ff
513
514#define REASS_DESC_BASE 0x10
515#define VC_LKUP_BASE 0x11
516#define REASS_TABLE_BASE 0x12
517#define REASS_QUEUE_BASE 0x13
518#define PKT_TM_CNT 0x16
519#define TMOUT_RANGE 0x17
520#define INTRVL_CNTR 0x18
521#define TMOUT_INDX 0x19
522#define VP_LKUP_BASE 0x1c
523#define VP_FILTER 0x1d
524#define ABR_LKUP_BASE 0x1e
525#define FREEQ_ST_ADR 0x24
526#define FREEQ_ED_ADR 0x25
527#define FREEQ_RD_PTR 0x26
528#define FREEQ_WR_PTR 0x27
529#define PCQ_ST_ADR 0x28
530#define PCQ_ED_ADR 0x29
531#define PCQ_RD_PTR 0x2a
532#define PCQ_WR_PTR 0x2b
533#define EXCP_Q_ST_ADR 0x2c
534#define EXCP_Q_ED_ADR 0x2d
535#define EXCP_Q_RD_PTR 0x2e
536#define EXCP_Q_WR_PTR 0x2f
537#define CC_FIFO_ST_ADR 0x34
538#define CC_FIFO_ED_ADR 0x35
539#define CC_FIFO_RD_PTR 0x36
540#define CC_FIFO_WR_PTR 0x37
541#define STATE_REG 0x38
542#define BUF_SIZE 0x42
543#define XTRA_RM_OFFSET 0x44
544#define DRP_PKT_CNTR_NC 0x84
545#define ERR_CNTR_NC 0x85
546#define CELL_CNTR0_NC 0x8c
547#define CELL_CNTR1_NC 0x8d
548
549
550#define EXCPQ_EMPTY 0x0040
551#define PCQ_EMPTY 0x0010
552#define FREEQ_EMPTY 0x0004
553
554
555
556
557
558
559
560
561
562#define IPHASE5575_TX_COUNTER 0x200
563#define IPHASE5575_RX_COUNTER 0x280
564#define IPHASE5575_TX_LIST_ADDR 0x300
565#define IPHASE5575_RX_LIST_ADDR 0x380
566
567
568
569
570
571#define TX_DESC_BASE 0x0000
572#define TX_COMP_Q 0x1000
573#define PKT_RDY_Q 0x1400
574#define CBR_SCHED_TABLE 0x1800
575#define UBR_SCHED_TABLE 0x3000
576#define UBR_WAIT_Q 0x4000
577#define ABR_SCHED_TABLE 0x5000
578#define ABR_WAIT_Q 0x5800
579#define EXT_VC_TABLE 0x6000
580#define MAIN_VC_TABLE 0x8000
581#define SCHEDSZ 1024
582#define TX_DESC_TABLE_SZ 128
583
584
585
586#define DESC_MODE 0x0
587#define VC_INDEX 0x1
588#define BYTE_CNT 0x3
589#define PKT_START_HI 0x4
590#define PKT_START_LO 0x5
591
592
593#define EOM_EN 0x0800
594#define AAL5 0x0100
595#define APP_CRC32 0x0400
596#define CMPL_INT 0x1000
597
598#define TABLE_ADDRESS(db, dn, to) \
599 (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
600
601
602#define RX_DESC_BASE 0x0000
603#define VP_TABLE 0x5c00
604#define EXCEPTION_Q 0x5e00
605#define FREE_BUF_DESC_Q 0x6000
606#define PKT_COMP_Q 0x6800
607#define REASS_TABLE 0x7000
608#define RX_VC_TABLE 0x7800
609#define ABR_VC_TABLE 0x8000
610#define RX_DESC_TABLE_SZ 736
611
612#define VP_TABLE_SZ 256
613#define RX_VC_TABLE_SZ 1024
614#define REASS_TABLE_SZ 1024
615
616#define RX_ACT 0x8000
617#define RX_VPVC 0x4000
618#define RX_CNG 0x0040
619#define RX_CER 0x0008
620#define RX_PTE 0x0004
621#define RX_OFL 0x0002
622#define NUM_RX_EXCP 32
623
624
625#define NO_AAL5_PKT 0x0000
626#define AAL5_PKT_REASSEMBLED 0x4000
627#define AAL5_PKT_TERMINATED 0x8000
628#define RAW_PKT 0xc000
629#define REASS_ABR 0x2000
630
631
632#define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE
633#define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE
634#define PHY_BASE IPHASE5575_FRONT_END_REG_BASE
635#define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
636#define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
637
638typedef volatile u_int ffreg_t;
639typedef u_int rreg_t;
640
641typedef struct _ffredn_t {
642 ffreg_t idlehead_high;
643 ffreg_t idlehead_low;
644 ffreg_t maxrate;
645 ffreg_t stparms;
646 ffreg_t abrubr_abr;
647 ffreg_t rm_type;
648 u_int filler5[0x17 - 0x06];
649 ffreg_t cmd_reg;
650 u_int filler18[0x20 - 0x18];
651 ffreg_t cbr_base;
652 ffreg_t vbr_base;
653 ffreg_t abr_base;
654 ffreg_t ubr_base;
655 u_int filler24;
656 ffreg_t vbrwq_base;
657 ffreg_t abrwq_base;
658 ffreg_t ubrwq_base;
659 ffreg_t vct_base;
660 ffreg_t vcte_base;
661 u_int filler2a[0x2C - 0x2A];
662 ffreg_t cbr_tab_beg;
663 ffreg_t cbr_tab_end;
664 ffreg_t cbr_pointer;
665 u_int filler2f[0x30 - 0x2F];
666 ffreg_t prq_st_adr;
667 ffreg_t prq_ed_adr;
668 ffreg_t prq_rd_ptr;
669 ffreg_t prq_wr_ptr;
670 ffreg_t tcq_st_adr;
671 ffreg_t tcq_ed_adr;
672 ffreg_t tcq_rd_ptr;
673 ffreg_t tcq_wr_ptr;
674 u_int filler38[0x40 - 0x38];
675 ffreg_t queue_base;
676 ffreg_t desc_base;
677 u_int filler42[0x45 - 0x42];
678 ffreg_t mode_reg_0;
679 ffreg_t mode_reg_1;
680 ffreg_t intr_status_reg;
681 ffreg_t mask_reg;
682 ffreg_t cell_ctr_high1;
683 ffreg_t cell_ctr_lo1;
684 ffreg_t state_reg;
685 u_int filler4c[0x58 - 0x4c];
686 ffreg_t curr_desc_num;
687 ffreg_t next_desc;
688 ffreg_t next_vc;
689 u_int filler5b[0x5d - 0x5b];
690 ffreg_t present_slot_cnt;
691 u_int filler5e[0x6a - 0x5e];
692 ffreg_t new_desc_num;
693 ffreg_t new_vc;
694 ffreg_t sched_tbl_ptr;
695 ffreg_t vbrwq_wptr;
696 ffreg_t vbrwq_rptr;
697 ffreg_t abrwq_wptr;
698 ffreg_t abrwq_rptr;
699 ffreg_t ubrwq_wptr;
700 ffreg_t ubrwq_rptr;
701 ffreg_t cbr_vc;
702 ffreg_t vbr_sb_vc;
703 ffreg_t abr_sb_vc;
704 ffreg_t ubr_sb_vc;
705 ffreg_t vbr_next_link;
706 ffreg_t abr_next_link;
707 ffreg_t ubr_next_link;
708 u_int filler7a[0x7c-0x7a];
709 ffreg_t out_rate_head;
710 u_int filler7d[0xca-0x7d];
711 ffreg_t cell_ctr_high1_nc;
712 ffreg_t cell_ctr_lo1_nc;
713 u_int fillercc[0x100-0xcc];
714} ffredn_t;
715
716typedef struct _rfredn_t {
717 rreg_t mode_reg_0;
718 rreg_t protocol_id;
719 rreg_t mask_reg;
720 rreg_t intr_status_reg;
721 rreg_t drp_pkt_cntr;
722 rreg_t err_cntr;
723 u_int filler6[0x08 - 0x06];
724 rreg_t raw_base_adr;
725 u_int filler2[0x0c - 0x09];
726 rreg_t cell_ctr0;
727 rreg_t cell_ctr1;
728 u_int filler3[0x0f - 0x0e];
729 rreg_t cmd_reg;
730 rreg_t desc_base;
731 rreg_t vc_lkup_base;
732 rreg_t reass_base;
733 rreg_t queue_base;
734 u_int filler14[0x16 - 0x14];
735 rreg_t pkt_tm_cnt;
736 rreg_t tmout_range;
737 rreg_t intrvl_cntr;
738 rreg_t tmout_indx;
739 u_int filler1a[0x1c - 0x1a];
740 rreg_t vp_lkup_base;
741 rreg_t vp_filter;
742 rreg_t abr_lkup_base;
743 u_int filler1f[0x24 - 0x1f];
744 rreg_t fdq_st_adr;
745 rreg_t fdq_ed_adr;
746 rreg_t fdq_rd_ptr;
747 rreg_t fdq_wr_ptr;
748 rreg_t pcq_st_adr;
749 rreg_t pcq_ed_adr;
750 rreg_t pcq_rd_ptr;
751 rreg_t pcq_wr_ptr;
752 rreg_t excp_st_adr;
753 rreg_t excp_ed_adr;
754 rreg_t excp_rd_ptr;
755 rreg_t excp_wr_ptr;
756 u_int filler30[0x34 - 0x30];
757 rreg_t raw_st_adr;
758 rreg_t raw_ed_adr;
759 rreg_t raw_rd_ptr;
760 rreg_t raw_wr_ptr;
761 rreg_t state_reg;
762 u_int filler39[0x42 - 0x39];
763 rreg_t buf_size;
764 u_int filler43;
765 rreg_t xtra_rm_offset;
766 u_int filler45[0x84 - 0x45];
767 rreg_t drp_pkt_cntr_nc;
768 rreg_t err_cntr_nc;
769 u_int filler86[0x8c - 0x86];
770 rreg_t cell_ctr0_nc;
771 rreg_t cell_ctr1_nc;
772 u_int filler8e[0x100-0x8e];
773} rfredn_t;
774
775typedef struct {
776
777 ffredn_t ffredn;
778 rfredn_t rfredn;
779} ia_regs_t;
780
781typedef struct {
782 u_short f_vc_type;
783 u_short f_nrm;
784 u_short f_nrmexp;
785 u_short reserved6;
786 u_short f_crm;
787 u_short reserved10;
788 u_short reserved12;
789 u_short reserved14;
790 u_short last_cell_slot;
791 u_short f_pcr;
792 u_short fraction;
793 u_short f_icr;
794 u_short f_cdf;
795 u_short f_mcr;
796 u_short f_acr;
797 u_short f_status;
798} f_vc_abr_entry;
799
800typedef struct {
801 u_short r_status_rdf;
802 u_short r_air;
803 u_short reserved4[14];
804} r_vc_abr_entry;
805
806#define MRM 3
807
808typedef struct srv_cls_param {
809 u32 class_type;
810 u32 pcr;
811
812 u32 scr;
813 u32 max_burst_size;
814
815
816 u32 mcr;
817 u32 icr;
818 u32 tbe;
819 u32 frtt;
820
821#if 0
822bits 31 30 29 28 27-25 24-22 21-19 18-9
823-----------------------------------------------------------------------------
824| NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |
825-----------------------------------------------------------------------------
826#endif
827
828 u8 nrm;
829
830 u8 trm;
831 u16 adtf;
832 u8 cdf;
833 u8 rif;
834 u8 rdf;
835 u8 reserved;
836} srv_cls_param_t;
837
838struct testTable_t {
839 u16 lastTime;
840 u16 fract;
841 u8 vc_status;
842};
843
844typedef struct {
845 u16 vci;
846 u16 error;
847} RX_ERROR_Q;
848
849typedef struct {
850 u8 active: 1;
851 u8 abr: 1;
852 u8 ubr: 1;
853 u8 cnt: 5;
854#define VC_ACTIVE 0x01
855#define VC_ABR 0x02
856#define VC_UBR 0x04
857} vcstatus_t;
858
859struct ia_rfL_t {
860 u32 fdq_st;
861 u32 fdq_ed;
862 u32 fdq_rd;
863 u32 fdq_wr;
864 u32 pcq_st;
865 u32 pcq_ed;
866 u32 pcq_rd;
867 u32 pcq_wr;
868};
869
870struct ia_ffL_t {
871 u32 prq_st;
872 u32 prq_ed;
873 u32 prq_wr;
874 u32 tcq_st;
875 u32 tcq_ed;
876 u32 tcq_rd;
877};
878
879struct desc_tbl_t {
880 u32 timestamp;
881 struct ia_vcc *iavcc;
882 struct sk_buff *txskb;
883};
884
885typedef struct ia_rtn_q {
886 struct desc_tbl_t data;
887 struct ia_rtn_q *next, *tail;
888} IARTN_Q;
889
890#define SUNI_LOSV 0x04
891enum ia_suni {
892 SUNI_MASTER_RESET = 0x000,
893 SUNI_MASTER_CONFIG = 0x004,
894 SUNI_MASTER_INTR_STAT = 0x008,
895 SUNI_RESERVED1 = 0x00c,
896 SUNI_MASTER_CLK_MONITOR = 0x010,
897 SUNI_MASTER_CONTROL = 0x014,
898
899 SUNI_RSOP_CONTROL = 0x040,
900 SUNI_RSOP_STATUS = 0x044,
901 SUNI_RSOP_SECTION_BIP8L = 0x048,
902 SUNI_RSOP_SECTION_BIP8M = 0x04c,
903
904 SUNI_TSOP_CONTROL = 0x050,
905 SUNI_TSOP_DIAG = 0x054,
906
907 SUNI_RLOP_CS = 0x060,
908 SUNI_RLOP_INTR = 0x064,
909 SUNI_RLOP_LINE_BIP24L = 0x068,
910 SUNI_RLOP_LINE_BIP24 = 0x06c,
911 SUNI_RLOP_LINE_BIP24M = 0x070,
912 SUNI_RLOP_LINE_FEBEL = 0x074,
913 SUNI_RLOP_LINE_FEBE = 0x078,
914 SUNI_RLOP_LINE_FEBEM = 0x07c,
915
916 SUNI_TLOP_CONTROL = 0x080,
917 SUNI_TLOP_DISG = 0x084,
918
919 SUNI_RPOP_CS = 0x0c0,
920 SUNI_RPOP_INTR = 0x0c4,
921 SUNI_RPOP_RESERVED = 0x0c8,
922 SUNI_RPOP_INTR_ENA = 0x0cc,
923
924 SUNI_RPOP_PATH_SIG = 0x0dc,
925 SUNI_RPOP_BIP8L = 0x0e0,
926 SUNI_RPOP_BIP8M = 0x0e4,
927 SUNI_RPOP_FEBEL = 0x0e8,
928 SUNI_RPOP_FEBEM = 0x0ec,
929
930 SUNI_TPOP_CNTRL_DAIG = 0x100,
931 SUNI_TPOP_POINTER_CTRL = 0x104,
932 SUNI_TPOP_SOURCER_CTRL = 0x108,
933
934 SUNI_TPOP_ARB_PRTL = 0x114,
935 SUNI_TPOP_ARB_PRTM = 0x118,
936 SUNI_TPOP_RESERVED2 = 0x11c,
937 SUNI_TPOP_PATH_SIG = 0x120,
938 SUNI_TPOP_PATH_STATUS = 0x124,
939
940 SUNI_RACP_CS = 0x140,
941 SUNI_RACP_INTR = 0x144,
942 SUNI_RACP_HDR_PATTERN = 0x148,
943 SUNI_RACP_HDR_MASK = 0x14c,
944 SUNI_RACP_CORR_HCS = 0x150,
945 SUNI_RACP_UNCORR_HCS = 0x154,
946
947 SUNI_TACP_CONTROL = 0x180,
948 SUNI_TACP_IDLE_HDR_PAT = 0x184,
949 SUNI_TACP_IDLE_PAY_PAY = 0x188,
950
951
952
953
954 SUNI_RESERVED_TEST = 0x204
955};
956
957typedef struct _SUNI_STATS_
958{
959 u32 valid;
960 u32 carrier_detect;
961
962 u16 rsop_oof_state;
963 u16 rsop_lof_state;
964 u16 rsop_los_state;
965 u32 rsop_los_count;
966 u32 rsop_bse_count;
967
968 u16 rlop_ferf_state;
969 u16 rlop_lais_state;
970 u32 rlop_lbe_count;
971 u32 rlop_febe_count;
972
973 u16 rpop_lop_state;
974 u16 rpop_pais_state;
975 u16 rpop_pyel_state;
976 u32 rpop_bip_count;
977 u32 rpop_febe_count;
978 u16 rpop_psig;
979
980 u16 racp_hp_state;
981 u32 racp_fu_count;
982 u32 racp_fo_count;
983 u32 racp_chcs_count;
984 u32 racp_uchcs_count;
985} IA_SUNI_STATS;
986
987typedef struct iadev_priv {
988
989 u32 __iomem *phy;
990 u32 __iomem *dma;
991 u32 __iomem *reg;
992 u32 __iomem *seg_reg;
993
994 u32 __iomem *reass_reg;
995
996 u32 __iomem *ram;
997 void __iomem *seg_ram;
998 void __iomem *reass_ram;
999 struct dle_q tx_dle_q;
1000 struct free_desc_q *tx_free_desc_qhead;
1001 struct sk_buff_head tx_dma_q, tx_backlog;
1002 spinlock_t tx_lock;
1003 IARTN_Q tx_return_q;
1004 u32 close_pending;
1005 wait_queue_head_t close_wait;
1006 wait_queue_head_t timeout_wait;
1007 struct cpcs_trailer_desc *tx_buf;
1008 u16 num_tx_desc, tx_buf_sz, rate_limit;
1009 u32 tx_cell_cnt, tx_pkt_cnt;
1010 void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
1011 struct dle_q rx_dle_q;
1012 struct free_desc_q *rx_free_desc_qhead;
1013 struct sk_buff_head rx_dma_q;
1014 spinlock_t rx_lock;
1015 struct atm_vcc **rx_open;
1016 u16 num_rx_desc, rx_buf_sz, rxing;
1017 u32 rx_pkt_ram, rx_tmp_cnt;
1018 unsigned long rx_tmp_jif;
1019 void __iomem *RX_DESC_BASE_ADDR;
1020 u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
1021 struct atm_dev *next_board;
1022 struct pci_dev *pci;
1023 int mem;
1024 unsigned int real_base;
1025 void __iomem *base;
1026 unsigned int pci_map_size;
1027 unsigned char irq;
1028 unsigned char bus;
1029 unsigned char dev_fn;
1030 u_short phy_type;
1031 u_short num_vc, memSize, memType;
1032 struct ia_ffL_t ffL;
1033 struct ia_rfL_t rfL;
1034
1035
1036 unsigned char carrier_detect;
1037
1038
1039 unsigned int tx_dma_cnt;
1040 unsigned int rx_dma_cnt;
1041 unsigned int NumEnabledCBR;
1042
1043 unsigned int rx_mark_cnt;
1044 unsigned int CbrTotEntries;
1045 unsigned int CbrRemEntries;
1046 unsigned int CbrEntryPt;
1047 unsigned int Granularity;
1048
1049 unsigned int sum_mcr, sum_cbr, LineRate;
1050 unsigned int n_abr;
1051 struct desc_tbl_t *desc_tbl;
1052 u_short host_tcq_wr;
1053 struct testTable_t **testTable;
1054 dma_addr_t tx_dle_dma;
1055 dma_addr_t rx_dle_dma;
1056} IADEV;
1057
1058
1059#define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1060#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1061
1062
1063enum ia_mb25 {
1064 MB25_MASTER_CTRL = 0x00,
1065 MB25_INTR_STATUS = 0x04,
1066 MB25_DIAG_CONTROL = 0x08,
1067 MB25_LED_HEC = 0x0c,
1068 MB25_LOW_BYTE_COUNTER = 0x10,
1069 MB25_HIGH_BYTE_COUNTER = 0x14
1070};
1071
1072
1073
1074
1075#define MB25_MC_UPLO 0x80
1076#define MB25_MC_DREC 0x40
1077#define MB25_MC_ECEIO 0x20
1078#define MB25_MC_TDPC 0x10
1079#define MB25_MC_DRIC 0x08
1080#define MB25_MC_HALTTX 0x04
1081#define MB25_MC_UMS 0x02
1082#define MB25_MC_ENABLED 0x01
1083
1084
1085
1086
1087#define MB25_IS_GSB 0x40
1088#define MB25_IS_HECECR 0x20
1089#define MB25_IS_SCR 0x10
1090#define MB25_IS_TPE 0x08
1091#define MB25_IS_RSCC 0x04
1092#define MB25_IS_RCSE 0x02
1093#define MB25_IS_RFIFOO 0x01
1094
1095
1096
1097
1098#define MB25_DC_FTXCD 0x80
1099#define MB25_DC_RXCOS 0x40
1100#define MB25_DC_ECEIO 0x20
1101#define MB25_DC_RLFLUSH 0x10
1102#define MB25_DC_IXPE 0x08
1103#define MB25_DC_IXHECE 0x04
1104#define MB25_DC_LB_MASK 0x03
1105
1106#define MB25_DC_LL 0x03
1107#define MB25_DC_PL 0x02
1108#define MB25_DC_NM 0x00
1109
1110#define FE_MASK 0x00F0
1111#define FE_MULTI_MODE 0x0000
1112#define FE_SINGLE_MODE 0x0010
1113#define FE_UTP_OPTION 0x0020
1114#define FE_25MBIT_PHY 0x0040
1115#define FE_DS3_PHY 0x0080
1116#define FE_E3_PHY 0x0090
1117
1118
1119enum suni_pm7345 {
1120 SUNI_CONFIG = 0x000,
1121 SUNI_INTR_ENBL = 0x004,
1122 SUNI_INTR_STAT = 0x008,
1123 SUNI_CONTROL = 0x00c,
1124 SUNI_ID_RESET = 0x010,
1125 SUNI_DATA_LINK_CTRL = 0x014,
1126 SUNI_RBOC_CONF_INTR_ENBL = 0x018,
1127 SUNI_RBOC_STAT = 0x01c,
1128 SUNI_DS3_FRM_CFG = 0x020,
1129 SUNI_DS3_FRM_INTR_ENBL = 0x024,
1130 SUNI_DS3_FRM_INTR_STAT = 0x028,
1131 SUNI_DS3_FRM_STAT = 0x02c,
1132 SUNI_RFDL_CFG = 0x030,
1133 SUNI_RFDL_ENBL_STAT = 0x034,
1134 SUNI_RFDL_STAT = 0x038,
1135 SUNI_RFDL_DATA = 0x03c,
1136 SUNI_PMON_CHNG = 0x040,
1137 SUNI_PMON_INTR_ENBL_STAT = 0x044,
1138
1139 SUNI_PMON_LCV_EVT_CNT_LSB = 0x050,
1140 SUNI_PMON_LCV_EVT_CNT_MSB = 0x054,
1141 SUNI_PMON_FBE_EVT_CNT_LSB = 0x058,
1142 SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c,
1143 SUNI_PMON_SEZ_DET_CNT_LSB = 0x060,
1144 SUNI_PMON_SEZ_DET_CNT_MSB = 0x064,
1145 SUNI_PMON_PE_EVT_CNT_LSB = 0x068,
1146 SUNI_PMON_PE_EVT_CNT_MSB = 0x06c,
1147 SUNI_PMON_PPE_EVT_CNT_LSB = 0x070,
1148 SUNI_PMON_PPE_EVT_CNT_MSB = 0x074,
1149 SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078,
1150 SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c,
1151 SUNI_DS3_TRAN_CFG = 0x080,
1152 SUNI_DS3_TRAN_DIAG = 0x084,
1153
1154 SUNI_XFDL_CFG = 0x090,
1155 SUNI_XFDL_INTR_ST = 0x094,
1156 SUNI_XFDL_XMIT_DATA = 0x098,
1157 SUNI_XBOC_CODE = 0x09c,
1158 SUNI_SPLR_CFG = 0x0a0,
1159 SUNI_SPLR_INTR_EN = 0x0a4,
1160 SUNI_SPLR_INTR_ST = 0x0a8,
1161 SUNI_SPLR_STATUS = 0x0ac,
1162 SUNI_SPLT_CFG = 0x0b0,
1163 SUNI_SPLT_CNTL = 0x0b4,
1164 SUNI_SPLT_DIAG_G1 = 0x0b8,
1165 SUNI_SPLT_F1 = 0x0bc,
1166 SUNI_CPPM_LOC_METERS = 0x0c0,
1167 SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4,
1168 SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8,
1169 SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc,
1170 SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0,
1171 SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4,
1172 SUNI_CPPM_FEBE_CNT_LSB = 0x0d8,
1173 SUNI_CPPM_FEBE_CNT_MSB = 0x0dc,
1174 SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0,
1175 SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4,
1176 SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8,
1177 SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec,
1178 SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0,
1179 SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4,
1180 SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8,
1181 SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc,
1182 SUNI_RXCP_CTRL = 0x100,
1183 SUNI_RXCP_FCTRL = 0x104,
1184 SUNI_RXCP_INTR_EN_STS = 0x108,
1185 SUNI_RXCP_IDLE_PAT_H1 = 0x10c,
1186 SUNI_RXCP_IDLE_PAT_H2 = 0x110,
1187 SUNI_RXCP_IDLE_PAT_H3 = 0x114,
1188 SUNI_RXCP_IDLE_PAT_H4 = 0x118,
1189 SUNI_RXCP_IDLE_MASK_H1 = 0x11c,
1190 SUNI_RXCP_IDLE_MASK_H2 = 0x120,
1191 SUNI_RXCP_IDLE_MASK_H3 = 0x124,
1192 SUNI_RXCP_IDLE_MASK_H4 = 0x128,
1193 SUNI_RXCP_CELL_PAT_H1 = 0x12c,
1194 SUNI_RXCP_CELL_PAT_H2 = 0x130,
1195 SUNI_RXCP_CELL_PAT_H3 = 0x134,
1196 SUNI_RXCP_CELL_PAT_H4 = 0x138,
1197 SUNI_RXCP_CELL_MASK_H1 = 0x13c,
1198 SUNI_RXCP_CELL_MASK_H2 = 0x140,
1199 SUNI_RXCP_CELL_MASK_H3 = 0x144,
1200 SUNI_RXCP_CELL_MASK_H4 = 0x148,
1201 SUNI_RXCP_HCS_CS = 0x14c,
1202 SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150,
1203
1204 SUNI_TXCP_CTRL = 0x160,
1205 SUNI_TXCP_INTR_EN_STS = 0x164,
1206 SUNI_TXCP_IDLE_PAT_H1 = 0x168,
1207 SUNI_TXCP_IDLE_PAT_H2 = 0x16c,
1208 SUNI_TXCP_IDLE_PAT_H3 = 0x170,
1209 SUNI_TXCP_IDLE_PAT_H4 = 0x174,
1210 SUNI_TXCP_IDLE_PAT_H5 = 0x178,
1211 SUNI_TXCP_IDLE_PAYLOAD = 0x17c,
1212 SUNI_E3_FRM_FRAM_OPTIONS = 0x180,
1213 SUNI_E3_FRM_MAINT_OPTIONS = 0x184,
1214 SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188,
1215 SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c,
1216 SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190,
1217 SUNI_E3_FRM_MAINT_INTR_IND = 0x194,
1218 SUNI_E3_FRM_MAINT_STAT = 0x198,
1219 SUNI_RESERVED4 = 0x19c,
1220 SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0,
1221 SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4,
1222 SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8,
1223 SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac,
1224 SUNI_TTB_CTRL = 0x1b0,
1225 SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4,
1226 SUNI_TTB_IND_ADDR = 0x1b8,
1227 SUNI_TTB_IND_DATA = 0x1bc,
1228 SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0,
1229 SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4,
1230
1231 SUNI_MASTER_TEST = 0x200,
1232
1233};
1234
1235#define SUNI_PM7345_T suni_pm7345_t
1236#define SUNI_PM7345 0x20
1237#define SUNI_PM5346 0x30
1238
1239
1240
1241#define SUNI_PM7345_CLB 0x01
1242#define SUNI_PM7345_PLB 0x02
1243#define SUNI_PM7345_DLB 0x04
1244#define SUNI_PM7345_LLB 0x80
1245#define SUNI_PM7345_E3ENBL 0x40
1246#define SUNI_PM7345_LOOPT 0x10
1247#define SUNI_PM7345_FIFOBP 0x20
1248#define SUNI_PM7345_FRMRBP 0x08
1249
1250
1251
1252#define SUNI_DS3_COFAE 0x80
1253#define SUNI_DS3_REDE 0x40
1254#define SUNI_DS3_CBITE 0x20
1255#define SUNI_DS3_FERFE 0x10
1256#define SUNI_DS3_IDLE 0x08
1257#define SUNI_DS3_AISE 0x04
1258#define SUNI_DS3_OOFE 0x02
1259#define SUNI_DS3_LOSE 0x01
1260
1261
1262
1263
1264#define SUNI_DS3_ACE 0x80
1265#define SUNI_DS3_REDV 0x40
1266#define SUNI_DS3_CBITV 0x20
1267#define SUNI_DS3_FERFV 0x10
1268#define SUNI_DS3_IDLV 0x08
1269#define SUNI_DS3_AISV 0x04
1270#define SUNI_DS3_OOFV 0x02
1271#define SUNI_DS3_LOSV 0x01
1272
1273
1274
1275
1276#define SUNI_E3_CZDI 0x40
1277#define SUNI_E3_LOSI 0x20
1278#define SUNI_E3_LCVI 0x10
1279#define SUNI_E3_COFAI 0x08
1280#define SUNI_E3_OOFI 0x04
1281#define SUNI_E3_LOS 0x02
1282#define SUNI_E3_OOF 0x01
1283
1284
1285
1286
1287#define SUNI_E3_AISD 0x80
1288#define SUNI_E3_FERF_RAI 0x40
1289#define SUNI_E3_FEBE 0x20
1290
1291
1292
1293
1294#define SUNI_DS3_HCSPASS 0x80
1295#define SUNI_DS3_HCSDQDB 0x40
1296#define SUNI_DS3_HCSADD 0x20
1297#define SUNI_DS3_HCK 0x10
1298#define SUNI_DS3_BLOCK 0x08
1299#define SUNI_DS3_DSCR 0x04
1300#define SUNI_DS3_OOCDV 0x02
1301#define SUNI_DS3_FIFORST 0x01
1302
1303
1304
1305
1306#define SUNI_DS3_OOCDE 0x80
1307#define SUNI_DS3_HCSE 0x40
1308#define SUNI_DS3_FIFOE 0x20
1309#define SUNI_DS3_OOCDI 0x10
1310#define SUNI_DS3_UHCSI 0x08
1311#define SUNI_DS3_COCAI 0x04
1312#define SUNI_DS3_FOVRI 0x02
1313#define SUNI_DS3_FUDRI 0x01
1314
1315
1316
1317
1318#define MEM_SIZE_MASK 0x000F
1319#define MEM_SIZE_128K 0x0000
1320#define MEM_SIZE_512K 0x0001
1321#define MEM_SIZE_1M 0x0002
1322
1323
1324#define FE_MASK 0x00F0
1325#define FE_MULTI_MODE 0x0000
1326#define FE_SINGLE_MODE 0x0010
1327#define FE_UTP_OPTION 0x0020
1328
1329#define NOVRAM_SIZE 64
1330#define CMD_LEN 10
1331
1332
1333
1334
1335
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1344
1345
1346#define EXTEND 0x100
1347#define IAWRITE 0x140
1348#define IAREAD 0x180
1349#define ERASE 0x1c0
1350
1351#define EWDS 0x00
1352#define WRAL 0x10
1353#define ERAL 0x20
1354#define EWEN 0x30
1355
1356
1357
1358
1359
1360
1361#define NVCE 0x02
1362#define NVSK 0x01
1363#define NVDO 0x08
1364#define NVDI 0x04
1365
1366
1367
1368
1369
1370
1371
1372#define CFG_AND(val) { \
1373 u32 t; \
1374 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1375 t &= (val); \
1376 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1377 }
1378
1379
1380
1381
1382
1383
1384
1385
1386#define CFG_OR(val) { \
1387 u32 t; \
1388 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1389 t |= (val); \
1390 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1391 }
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403#define NVRAM_CMD(cmd) { \
1404 int i; \
1405 u_short c = cmd; \
1406 CFG_AND(~(NVCE|NVSK)); \
1407 CFG_OR(NVCE); \
1408 for (i=0; i<CMD_LEN; i++) { \
1409 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1410 c <<= 1; \
1411 } \
1412 }
1413
1414
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1418
1419
1420#define NVRAM_CLR_CE {CFG_AND(~NVCE)}
1421
1422
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1425
1426
1427
1428
1429#define NVRAM_CLKOUT(bitval) { \
1430 CFG_AND(~NVDI); \
1431 CFG_OR((bitval) ? NVDI : 0); \
1432 CFG_OR(NVSK); \
1433 CFG_AND( ~NVSK); \
1434 }
1435
1436
1437
1438
1439
1440
1441
1442
1443#define NVRAM_CLKIN(value) { \
1444 u32 _t; \
1445 CFG_OR(NVSK); \
1446 CFG_AND(~NVSK); \
1447 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1448 value = (_t & NVDO) ? 1 : 0; \
1449 }
1450
1451
1452#endif
1453