LXR linux/drivers/block/rsxx/rsxx

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3* Filename: rsxx_priv.h
   4*
   5* Authors: Joshua Morris <josh.h.morris@us.ibm.com>
   6*       Philip Kelleher <pjk1939@linux.vnet.ibm.com>
   7*
   8* (C) Copyright 2013 IBM Corporation
   9*/
  10
  11#ifndef __RSXX_PRIV_H__
  12#define __RSXX_PRIV_H__
  13
  14#include <linux/semaphore.h>
  15
  16#include <linux/fs.h>
  17#include <linux/interrupt.h>
  18#include <linux/mutex.h>
  19#include <linux/pci.h>
  20#include <linux/spinlock.h>
  21#include <linux/sysfs.h>
  22#include <linux/workqueue.h>
  23#include <linux/bio.h>
  24#include <linux/vmalloc.h>
  25#include <linux/timer.h>
  26#include <linux/ioctl.h>
  27#include <linux/delay.h>
  28
  29#include "rsxx.h"
  30#include "rsxx_cfg.h"
  31
  32struct proc_cmd;
  33
  34#define PCI_DEVICE_ID_FS70_FLASH        0x04A9
  35#define PCI_DEVICE_ID_FS80_FLASH        0x04AA
  36
  37#define RS70_PCI_REV_SUPPORTED  4
  38
  39#define DRIVER_NAME "rsxx"
  40#define DRIVER_VERSION "4.0.3.2516"
  41
  42/* Block size is 4096 */
  43#define RSXX_HW_BLK_SHIFT               12
  44#define RSXX_HW_BLK_SIZE                (1 << RSXX_HW_BLK_SHIFT)
  45#define RSXX_HW_BLK_MASK                (RSXX_HW_BLK_SIZE - 1)
  46
  47#define MAX_CREG_DATA8  32
  48#define LOG_BUF_SIZE8   128
  49
  50#define RSXX_MAX_OUTSTANDING_CMDS       255
  51#define RSXX_CS_IDX_MASK                0xff
  52
  53#define STATUS_BUFFER_SIZE8     4096
  54#define COMMAND_BUFFER_SIZE8    4096
  55
  56#define RSXX_MAX_TARGETS        8
  57
  58struct dma_tracker_list;
  59
  60/* DMA Command/Status Buffer structure */
  61struct rsxx_cs_buffer {
  62        dma_addr_t      dma_addr;
  63        void            *buf;
  64        u32             idx;
  65};
  66
  67struct rsxx_dma_stats {
  68        u32 crc_errors;
  69        u32 hard_errors;
  70        u32 soft_errors;
  71        u32 writes_issued;
  72        u32 writes_failed;
  73        u32 reads_issued;
  74        u32 reads_failed;
  75        u32 reads_retried;
  76        u32 discards_issued;
  77        u32 discards_failed;
  78        u32 done_rescheduled;
  79        u32 issue_rescheduled;
  80        u32 dma_sw_err;
  81        u32 dma_hw_fault;
  82        u32 dma_cancelled;
  83        u32 sw_q_depth;         /* Number of DMAs on the SW queue. */
  84        atomic_t hw_q_depth;    /* Number of DMAs queued to HW. */
  85};
  86
  87struct rsxx_dma_ctrl {
  88        struct rsxx_cardinfo            *card;
  89        int                             id;
  90        void                            __iomem *regmap;
  91        struct rsxx_cs_buffer           status;
  92        struct rsxx_cs_buffer           cmd;
  93        u16                             e_cnt;
  94        spinlock_t                      queue_lock;
  95        struct list_head                queue;
  96        struct workqueue_struct         *issue_wq;
  97        struct work_struct              issue_dma_work;
  98        struct workqueue_struct         *done_wq;
  99        struct work_struct              dma_done_work;
 100        struct timer_list               activity_timer;
 101        struct dma_tracker_list         *trackers;
 102        struct rsxx_dma_stats           stats;
 103        struct mutex                    work_lock;
 104};
 105
 106struct rsxx_cardinfo {
 107        struct pci_dev          *dev;
 108        unsigned int            halt;
 109        unsigned int            eeh_state;
 110
 111        void                    __iomem *regmap;
 112        spinlock_t              irq_lock;
 113        unsigned int            isr_mask;
 114        unsigned int            ier_mask;
 115
 116        struct rsxx_card_cfg    config;
 117        int                     config_valid;
 118
 119        /* Embedded CPU Communication */
 120        struct {
 121                spinlock_t              lock;
 122                bool                    active;
 123                struct creg_cmd         *active_cmd;
 124                struct workqueue_struct *creg_wq;
 125                struct work_struct      done_work;
 126                struct list_head        queue;
 127                unsigned int            q_depth;
 128                /* Cache the creg status to prevent ioreads */
 129                struct {
 130                        u32             stat;
 131                        u32             failed_cancel_timer;
 132                        u32             creg_timeout;
 133                } creg_stats;
 134                struct timer_list       cmd_timer;
 135                struct mutex            reset_lock;
 136                int                     reset;
 137        } creg_ctrl;
 138
 139        struct {
 140                char tmp[MAX_CREG_DATA8];
 141                char buf[LOG_BUF_SIZE8]; /* terminated */
 142                int buf_len;
 143        } log;
 144
 145        struct workqueue_struct *event_wq;
 146        struct work_struct      event_work;
 147        unsigned int            state;
 148        u64                     size8;
 149
 150        /* Lock the device attach/detach function */
 151        struct mutex            dev_lock;
 152
 153        /* Block Device Variables */
 154        bool                    bdev_attached;
 155        int                     disk_id;
 156        int                     major;
 157        struct gendisk          *gendisk;
 158        struct {
 159                /* Used to convert a byte address to a device address. */
 160                u64 lower_mask;
 161                u64 upper_shift;
 162                u64 upper_mask;
 163                u64 target_mask;
 164                u64 target_shift;
 165        } _stripe;
 166        unsigned int            dma_fault;
 167
 168        int                     scrub_hard;
 169
 170        int                     n_targets;
 171        struct rsxx_dma_ctrl    *ctrl;
 172
 173        struct dentry           *debugfs_dir;
 174};
 175
 176enum rsxx_pci_regmap {
 177        HWID            = 0x00, /* Hardware Identification Register */
 178        SCRATCH         = 0x04, /* Scratch/Debug Register */
 179        RESET           = 0x08, /* Reset Register */
 180        ISR             = 0x10, /* Interrupt Status Register */
 181        IER             = 0x14, /* Interrupt Enable Register */
 182        IPR             = 0x18, /* Interrupt Poll Register */
 183        CB_ADD_LO       = 0x20, /* Command Host Buffer Address [31:0] */
 184        CB_ADD_HI       = 0x24, /* Command Host Buffer Address [63:32]*/
 185        HW_CMD_IDX      = 0x28, /* Hardware Processed Command Index */
 186        SW_CMD_IDX      = 0x2C, /* Software Processed Command Index */
 187        SB_ADD_LO       = 0x30, /* Status Host Buffer Address [31:0] */
 188        SB_ADD_HI       = 0x34, /* Status Host Buffer Address [63:32] */
 189        HW_STATUS_CNT   = 0x38, /* Hardware Status Counter */
 190        SW_STATUS_CNT   = 0x3C, /* Deprecated */
 191        CREG_CMD        = 0x40, /* CPU Command Register */
 192        CREG_ADD        = 0x44, /* CPU Address Register */
 193        CREG_CNT        = 0x48, /* CPU Count Register */
 194        CREG_STAT       = 0x4C, /* CPU Status Register */
 195        CREG_DATA0      = 0x50, /* CPU Data Registers */
 196        CREG_DATA1      = 0x54,
 197        CREG_DATA2      = 0x58,
 198        CREG_DATA3      = 0x5C,
 199        CREG_DATA4      = 0x60,
 200        CREG_DATA5      = 0x64,
 201        CREG_DATA6      = 0x68,
 202        CREG_DATA7      = 0x6c,
 203        INTR_COAL       = 0x70, /* Interrupt Coalescing Register */
 204        HW_ERROR        = 0x74, /* Card Error Register */
 205        PCI_DEBUG0      = 0x78, /* PCI Debug Registers */
 206        PCI_DEBUG1      = 0x7C,
 207        PCI_DEBUG2      = 0x80,
 208        PCI_DEBUG3      = 0x84,
 209        PCI_DEBUG4      = 0x88,
 210        PCI_DEBUG5      = 0x8C,
 211        PCI_DEBUG6      = 0x90,
 212        PCI_DEBUG7      = 0x94,
 213        PCI_POWER_THROTTLE = 0x98,
 214        PERF_CTRL       = 0x9c,
 215        PERF_TIMER_LO   = 0xa0,
 216        PERF_TIMER_HI   = 0xa4,
 217        PERF_RD512_LO   = 0xa8,
 218        PERF_RD512_HI   = 0xac,
 219        PERF_WR512_LO   = 0xb0,
 220        PERF_WR512_HI   = 0xb4,
 221        PCI_RECONFIG    = 0xb8,
 222};
 223
 224enum rsxx_intr {
 225        CR_INTR_DMA0    = 0x00000001,
 226        CR_INTR_CREG    = 0x00000002,
 227        CR_INTR_DMA1    = 0x00000004,
 228        CR_INTR_EVENT   = 0x00000008,
 229        CR_INTR_DMA2    = 0x00000010,
 230        CR_INTR_DMA3    = 0x00000020,
 231        CR_INTR_DMA4    = 0x00000040,
 232        CR_INTR_DMA5    = 0x00000080,
 233        CR_INTR_DMA6    = 0x00000100,
 234        CR_INTR_DMA7    = 0x00000200,
 235        CR_INTR_ALL_C   = 0x0000003f,
 236        CR_INTR_ALL_G   = 0x000003ff,
 237        CR_INTR_DMA_ALL = 0x000003f5,
 238        CR_INTR_ALL     = 0xffffffff,
 239};
 240
 241static inline int CR_INTR_DMA(int N)
 242{
 243        static const unsigned int _CR_INTR_DMA[] = {
 244                CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
 245                CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
 246        };
 247        return _CR_INTR_DMA[N];
 248}
 249enum rsxx_pci_reset {
 250        DMA_QUEUE_RESET         = 0x00000001,
 251};
 252
 253enum rsxx_hw_fifo_flush {
 254        RSXX_FLUSH_BUSY         = 0x00000002,
 255        RSXX_FLUSH_TIMEOUT      = 0x00000004,
 256};
 257
 258enum rsxx_pci_revision {
 259        RSXX_DISCARD_SUPPORT = 2,
 260        RSXX_EEH_SUPPORT     = 3,
 261};
 262
 263enum rsxx_creg_cmd {
 264        CREG_CMD_TAG_MASK       = 0x0000FF00,
 265        CREG_OP_WRITE           = 0x000000C0,
 266        CREG_OP_READ            = 0x000000E0,
 267};
 268
 269enum rsxx_creg_addr {
 270        CREG_ADD_CARD_CMD               = 0x80001000,
 271        CREG_ADD_CARD_STATE             = 0x80001004,
 272        CREG_ADD_CARD_SIZE              = 0x8000100c,
 273        CREG_ADD_CAPABILITIES           = 0x80001050,
 274        CREG_ADD_LOG                    = 0x80002000,
 275        CREG_ADD_NUM_TARGETS            = 0x80003000,
 276        CREG_ADD_CRAM                   = 0xA0000000,
 277        CREG_ADD_CONFIG                 = 0xB0000000,
 278};
 279
 280enum rsxx_creg_card_cmd {
 281        CARD_CMD_STARTUP                = 1,
 282        CARD_CMD_SHUTDOWN               = 2,
 283        CARD_CMD_LOW_LEVEL_FORMAT       = 3,
 284        CARD_CMD_FPGA_RECONFIG_BR       = 4,
 285        CARD_CMD_FPGA_RECONFIG_MAIN     = 5,
 286        CARD_CMD_BACKUP                 = 6,
 287        CARD_CMD_RESET                  = 7,
 288        CARD_CMD_deprecated             = 8,
 289        CARD_CMD_UNINITIALIZE           = 9,
 290        CARD_CMD_DSTROY_EMERGENCY       = 10,
 291        CARD_CMD_DSTROY_NORMAL          = 11,
 292        CARD_CMD_DSTROY_EXTENDED        = 12,
 293        CARD_CMD_DSTROY_ABORT           = 13,
 294};
 295
 296enum rsxx_card_state {
 297        CARD_STATE_SHUTDOWN             = 0x00000001,
 298        CARD_STATE_STARTING             = 0x00000002,
 299        CARD_STATE_FORMATTING           = 0x00000004,
 300        CARD_STATE_UNINITIALIZED        = 0x00000008,
 301        CARD_STATE_GOOD                 = 0x00000010,
 302        CARD_STATE_SHUTTING_DOWN        = 0x00000020,
 303        CARD_STATE_FAULT                = 0x00000040,
 304        CARD_STATE_RD_ONLY_FAULT        = 0x00000080,
 305        CARD_STATE_DSTROYING            = 0x00000100,
 306};
 307
 308enum rsxx_led {
 309        LED_DEFAULT     = 0x0,
 310        LED_IDENTIFY    = 0x1,
 311        LED_SOAK        = 0x2,
 312};
 313
 314enum rsxx_creg_flash_lock {
 315        CREG_FLASH_LOCK         = 1,
 316        CREG_FLASH_UNLOCK       = 2,
 317};
 318
 319enum rsxx_card_capabilities {
 320        CARD_CAP_SUBPAGE_WRITES = 0x00000080,
 321};
 322
 323enum rsxx_creg_stat {
 324        CREG_STAT_STATUS_MASK   = 0x00000003,
 325        CREG_STAT_SUCCESS       = 0x1,
 326        CREG_STAT_ERROR         = 0x2,
 327        CREG_STAT_CHAR_PENDING  = 0x00000004, /* Character I/O pending bit */
 328        CREG_STAT_LOG_PENDING   = 0x00000008, /* HW log message pending bit */
 329        CREG_STAT_TAG_MASK      = 0x0000ff00,
 330};
 331
 332enum rsxx_dma_finish {
 333        FREE_DMA        = 0x0,
 334        COMPLETE_DMA    = 0x1,
 335};
 336
 337static inline unsigned int CREG_DATA(int N)
 338{
 339        return CREG_DATA0 + (N << 2);
 340}
 341
 342/*----------------- Convenient Log Wrappers -------------------*/
 343#define CARD_TO_DEV(__CARD)     (&(__CARD)->dev->dev)
 344
 345/***** config.c *****/
 346int rsxx_load_config(struct rsxx_cardinfo *card);
 347
 348/***** core.c *****/
 349void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 350void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 351void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
 352                                 unsigned int intr);
 353void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
 354                                  unsigned int intr);
 355
 356/***** dev.c *****/
 357int rsxx_attach_dev(struct rsxx_cardinfo *card);
 358void rsxx_detach_dev(struct rsxx_cardinfo *card);
 359int rsxx_setup_dev(struct rsxx_cardinfo *card);
 360void rsxx_destroy_dev(struct rsxx_cardinfo *card);
 361int rsxx_dev_init(void);
 362void rsxx_dev_cleanup(void);
 363
 364/***** dma.c ****/
 365typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
 366                                void *cb_data,
 367                                unsigned int status);
 368int rsxx_dma_setup(struct rsxx_cardinfo *card);
 369void rsxx_dma_destroy(struct rsxx_cardinfo *card);
 370int rsxx_dma_init(void);
 371int rsxx_cleanup_dma_queue(struct rsxx_dma_ctrl *ctrl,
 372                                struct list_head *q,
 373                                unsigned int done);
 374int rsxx_dma_cancel(struct rsxx_dma_ctrl *ctrl);
 375void rsxx_dma_cleanup(void);
 376void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
 377int rsxx_dma_configure(struct rsxx_cardinfo *card);
 378blk_status_t rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
 379                           struct bio *bio,
 380                           atomic_t *n_dmas,
 381                           rsxx_dma_cb cb,
 382                           void *cb_data);
 383int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
 384int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
 385int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
 386
 387/***** cregs.c *****/
 388int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
 389                        unsigned int size8,
 390                        void *data,
 391                        int byte_stream);
 392int rsxx_creg_read(struct rsxx_cardinfo *card,
 393                       u32 addr,
 394                       unsigned int size8,
 395                       void *data,
 396                       int byte_stream);
 397int rsxx_read_hw_log(struct rsxx_cardinfo *card);
 398int rsxx_get_card_state(struct rsxx_cardinfo *card,
 399                            unsigned int *state);
 400int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
 401int rsxx_get_num_targets(struct rsxx_cardinfo *card,
 402                             unsigned int *n_targets);
 403int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
 404                                   u32 *capabilities);
 405int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
 406int rsxx_creg_setup(struct rsxx_cardinfo *card);
 407void rsxx_creg_destroy(struct rsxx_cardinfo *card);
 408int rsxx_creg_init(void);
 409void rsxx_creg_cleanup(void);
 410int rsxx_reg_access(struct rsxx_cardinfo *card,
 411                        struct rsxx_reg_access __user *ucmd,
 412                        int read);
 413void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
 414void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
 415
 416
 417
 418#endif /* __DRIVERS_BLOCK_RSXX_H__ */
 419