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7#include <linux/debugfs.h>
8#include <linux/device.h>
9#include <linux/dma-direction.h>
10#include <linux/dma-mapping.h>
11#include <linux/idr.h>
12#include <linux/interrupt.h>
13#include <linux/list.h>
14#include <linux/mhi.h>
15#include <linux/mod_devicetable.h>
16#include <linux/module.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/wait.h>
20#include "internal.h"
21
22static DEFINE_IDA(mhi_controller_ida);
23
24const char * const mhi_ee_str[MHI_EE_MAX] = {
25 [MHI_EE_PBL] = "PRIMARY BOOTLOADER",
26 [MHI_EE_SBL] = "SECONDARY BOOTLOADER",
27 [MHI_EE_AMSS] = "MISSION MODE",
28 [MHI_EE_RDDM] = "RAMDUMP DOWNLOAD MODE",
29 [MHI_EE_WFW] = "WLAN FIRMWARE",
30 [MHI_EE_PTHRU] = "PASS THROUGH",
31 [MHI_EE_EDL] = "EMERGENCY DOWNLOAD",
32 [MHI_EE_FP] = "FLASH PROGRAMMER",
33 [MHI_EE_DISABLE_TRANSITION] = "DISABLE",
34 [MHI_EE_NOT_SUPPORTED] = "NOT SUPPORTED",
35};
36
37const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = {
38 [DEV_ST_TRANSITION_PBL] = "PBL",
39 [DEV_ST_TRANSITION_READY] = "READY",
40 [DEV_ST_TRANSITION_SBL] = "SBL",
41 [DEV_ST_TRANSITION_MISSION_MODE] = "MISSION MODE",
42 [DEV_ST_TRANSITION_FP] = "FLASH PROGRAMMER",
43 [DEV_ST_TRANSITION_SYS_ERR] = "SYS ERROR",
44 [DEV_ST_TRANSITION_DISABLE] = "DISABLE",
45};
46
47const char * const mhi_state_str[MHI_STATE_MAX] = {
48 [MHI_STATE_RESET] = "RESET",
49 [MHI_STATE_READY] = "READY",
50 [MHI_STATE_M0] = "M0",
51 [MHI_STATE_M1] = "M1",
52 [MHI_STATE_M2] = "M2",
53 [MHI_STATE_M3] = "M3",
54 [MHI_STATE_M3_FAST] = "M3 FAST",
55 [MHI_STATE_BHI] = "BHI",
56 [MHI_STATE_SYS_ERR] = "SYS ERROR",
57};
58
59const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX] = {
60 [MHI_CH_STATE_TYPE_RESET] = "RESET",
61 [MHI_CH_STATE_TYPE_STOP] = "STOP",
62 [MHI_CH_STATE_TYPE_START] = "START",
63};
64
65static const char * const mhi_pm_state_str[] = {
66 [MHI_PM_STATE_DISABLE] = "DISABLE",
67 [MHI_PM_STATE_POR] = "POWER ON RESET",
68 [MHI_PM_STATE_M0] = "M0",
69 [MHI_PM_STATE_M2] = "M2",
70 [MHI_PM_STATE_M3_ENTER] = "M?->M3",
71 [MHI_PM_STATE_M3] = "M3",
72 [MHI_PM_STATE_M3_EXIT] = "M3->M0",
73 [MHI_PM_STATE_FW_DL_ERR] = "Firmware Download Error",
74 [MHI_PM_STATE_SYS_ERR_DETECT] = "SYS ERROR Detect",
75 [MHI_PM_STATE_SYS_ERR_PROCESS] = "SYS ERROR Process",
76 [MHI_PM_STATE_SHUTDOWN_PROCESS] = "SHUTDOWN Process",
77 [MHI_PM_STATE_LD_ERR_FATAL_DETECT] = "Linkdown or Error Fatal Detect",
78};
79
80const char *to_mhi_pm_state_str(enum mhi_pm_state state)
81{
82 int index = find_last_bit((unsigned long *)&state, 32);
83
84 if (index >= ARRAY_SIZE(mhi_pm_state_str))
85 return "Invalid State";
86
87 return mhi_pm_state_str[index];
88}
89
90static ssize_t serial_number_show(struct device *dev,
91 struct device_attribute *attr,
92 char *buf)
93{
94 struct mhi_device *mhi_dev = to_mhi_device(dev);
95 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
96
97 return snprintf(buf, PAGE_SIZE, "Serial Number: %u\n",
98 mhi_cntrl->serial_number);
99}
100static DEVICE_ATTR_RO(serial_number);
101
102static ssize_t oem_pk_hash_show(struct device *dev,
103 struct device_attribute *attr,
104 char *buf)
105{
106 struct mhi_device *mhi_dev = to_mhi_device(dev);
107 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
108 int i, cnt = 0;
109
110 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++)
111 cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
112 "OEMPKHASH[%d]: 0x%x\n", i,
113 mhi_cntrl->oem_pk_hash[i]);
114
115 return cnt;
116}
117static DEVICE_ATTR_RO(oem_pk_hash);
118
119static struct attribute *mhi_dev_attrs[] = {
120 &dev_attr_serial_number.attr,
121 &dev_attr_oem_pk_hash.attr,
122 NULL,
123};
124ATTRIBUTE_GROUPS(mhi_dev);
125
126
127static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl,
128 struct mhi_ring *ring,
129 u64 len)
130{
131 ring->alloc_size = len + (len - 1);
132 ring->pre_aligned = dma_alloc_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
133 &ring->dma_handle, GFP_KERNEL);
134 if (!ring->pre_aligned)
135 return -ENOMEM;
136
137 ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1);
138 ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle);
139
140 return 0;
141}
142
143void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl)
144{
145 int i;
146 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
147
148 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
149 if (mhi_event->offload_ev)
150 continue;
151
152 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
153 }
154
155 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
156}
157
158int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)
159{
160 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
161 struct device *dev = &mhi_cntrl->mhi_dev->dev;
162 unsigned long irq_flags = IRQF_SHARED | IRQF_NO_SUSPEND;
163 int i, ret;
164
165
166 if (mhi_cntrl->irq_flags)
167 irq_flags = mhi_cntrl->irq_flags;
168
169
170 ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler,
171 mhi_intvec_threaded_handler,
172 irq_flags,
173 "bhi", mhi_cntrl);
174 if (ret)
175 return ret;
176
177 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
178 if (mhi_event->offload_ev)
179 continue;
180
181 if (mhi_event->irq >= mhi_cntrl->nr_irqs) {
182 dev_err(dev, "irq %d not available for event ring\n",
183 mhi_event->irq);
184 ret = -EINVAL;
185 goto error_request;
186 }
187
188 ret = request_irq(mhi_cntrl->irq[mhi_event->irq],
189 mhi_irq_handler,
190 irq_flags,
191 "mhi", mhi_event);
192 if (ret) {
193 dev_err(dev, "Error requesting irq:%d for ev:%d\n",
194 mhi_cntrl->irq[mhi_event->irq], i);
195 goto error_request;
196 }
197 }
198
199 return 0;
200
201error_request:
202 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
203 if (mhi_event->offload_ev)
204 continue;
205
206 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
207 }
208 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
209
210 return ret;
211}
212
213void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl)
214{
215 int i;
216 struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt;
217 struct mhi_cmd *mhi_cmd;
218 struct mhi_event *mhi_event;
219 struct mhi_ring *ring;
220
221 mhi_cmd = mhi_cntrl->mhi_cmd;
222 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) {
223 ring = &mhi_cmd->ring;
224 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
225 ring->pre_aligned, ring->dma_handle);
226 ring->base = NULL;
227 ring->iommu_base = 0;
228 }
229
230 dma_free_coherent(mhi_cntrl->cntrl_dev,
231 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
232 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
233
234 mhi_event = mhi_cntrl->mhi_event;
235 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
236 if (mhi_event->offload_ev)
237 continue;
238
239 ring = &mhi_event->ring;
240 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
241 ring->pre_aligned, ring->dma_handle);
242 ring->base = NULL;
243 ring->iommu_base = 0;
244 }
245
246 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
247 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
248 mhi_ctxt->er_ctxt_addr);
249
250 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
251 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
252 mhi_ctxt->chan_ctxt_addr);
253
254 kfree(mhi_ctxt);
255 mhi_cntrl->mhi_ctxt = NULL;
256}
257
258int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)
259{
260 struct mhi_ctxt *mhi_ctxt;
261 struct mhi_chan_ctxt *chan_ctxt;
262 struct mhi_event_ctxt *er_ctxt;
263 struct mhi_cmd_ctxt *cmd_ctxt;
264 struct mhi_chan *mhi_chan;
265 struct mhi_event *mhi_event;
266 struct mhi_cmd *mhi_cmd;
267 u32 tmp;
268 int ret = -ENOMEM, i;
269
270 atomic_set(&mhi_cntrl->dev_wake, 0);
271 atomic_set(&mhi_cntrl->pending_pkts, 0);
272
273 mhi_ctxt = kzalloc(sizeof(*mhi_ctxt), GFP_KERNEL);
274 if (!mhi_ctxt)
275 return -ENOMEM;
276
277
278 mhi_ctxt->chan_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
279 sizeof(*mhi_ctxt->chan_ctxt) *
280 mhi_cntrl->max_chan,
281 &mhi_ctxt->chan_ctxt_addr,
282 GFP_KERNEL);
283 if (!mhi_ctxt->chan_ctxt)
284 goto error_alloc_chan_ctxt;
285
286 mhi_chan = mhi_cntrl->mhi_chan;
287 chan_ctxt = mhi_ctxt->chan_ctxt;
288 for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) {
289
290 if (mhi_chan->offload_ch)
291 continue;
292
293 tmp = chan_ctxt->chcfg;
294 tmp &= ~CHAN_CTX_CHSTATE_MASK;
295 tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT);
296 tmp &= ~CHAN_CTX_BRSTMODE_MASK;
297 tmp |= (mhi_chan->db_cfg.brstmode << CHAN_CTX_BRSTMODE_SHIFT);
298 tmp &= ~CHAN_CTX_POLLCFG_MASK;
299 tmp |= (mhi_chan->db_cfg.pollcfg << CHAN_CTX_POLLCFG_SHIFT);
300 chan_ctxt->chcfg = tmp;
301
302 chan_ctxt->chtype = mhi_chan->type;
303 chan_ctxt->erindex = mhi_chan->er_index;
304
305 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
306 mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp;
307 }
308
309
310 mhi_ctxt->er_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
311 sizeof(*mhi_ctxt->er_ctxt) *
312 mhi_cntrl->total_ev_rings,
313 &mhi_ctxt->er_ctxt_addr,
314 GFP_KERNEL);
315 if (!mhi_ctxt->er_ctxt)
316 goto error_alloc_er_ctxt;
317
318 er_ctxt = mhi_ctxt->er_ctxt;
319 mhi_event = mhi_cntrl->mhi_event;
320 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
321 mhi_event++) {
322 struct mhi_ring *ring = &mhi_event->ring;
323
324
325 if (mhi_event->offload_ev)
326 continue;
327
328 tmp = er_ctxt->intmod;
329 tmp &= ~EV_CTX_INTMODC_MASK;
330 tmp &= ~EV_CTX_INTMODT_MASK;
331 tmp |= (mhi_event->intmod << EV_CTX_INTMODT_SHIFT);
332 er_ctxt->intmod = tmp;
333
334 er_ctxt->ertype = MHI_ER_TYPE_VALID;
335 er_ctxt->msivec = mhi_event->irq;
336 mhi_event->db_cfg.db_mode = true;
337
338 ring->el_size = sizeof(struct mhi_tre);
339 ring->len = ring->el_size * ring->elements;
340 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
341 if (ret)
342 goto error_alloc_er;
343
344
345
346
347
348 ring->rp = ring->wp = ring->base;
349 er_ctxt->rbase = ring->iommu_base;
350 er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase;
351 er_ctxt->rlen = ring->len;
352 ring->ctxt_wp = &er_ctxt->wp;
353 }
354
355
356 ret = -ENOMEM;
357 mhi_ctxt->cmd_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
358 sizeof(*mhi_ctxt->cmd_ctxt) *
359 NR_OF_CMD_RINGS,
360 &mhi_ctxt->cmd_ctxt_addr,
361 GFP_KERNEL);
362 if (!mhi_ctxt->cmd_ctxt)
363 goto error_alloc_er;
364
365 mhi_cmd = mhi_cntrl->mhi_cmd;
366 cmd_ctxt = mhi_ctxt->cmd_ctxt;
367 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
368 struct mhi_ring *ring = &mhi_cmd->ring;
369
370 ring->el_size = sizeof(struct mhi_tre);
371 ring->elements = CMD_EL_PER_RING;
372 ring->len = ring->el_size * ring->elements;
373 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
374 if (ret)
375 goto error_alloc_cmd;
376
377 ring->rp = ring->wp = ring->base;
378 cmd_ctxt->rbase = ring->iommu_base;
379 cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase;
380 cmd_ctxt->rlen = ring->len;
381 ring->ctxt_wp = &cmd_ctxt->wp;
382 }
383
384 mhi_cntrl->mhi_ctxt = mhi_ctxt;
385
386 return 0;
387
388error_alloc_cmd:
389 for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) {
390 struct mhi_ring *ring = &mhi_cmd->ring;
391
392 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
393 ring->pre_aligned, ring->dma_handle);
394 }
395 dma_free_coherent(mhi_cntrl->cntrl_dev,
396 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
397 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
398 i = mhi_cntrl->total_ev_rings;
399 mhi_event = mhi_cntrl->mhi_event + i;
400
401error_alloc_er:
402 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
403 struct mhi_ring *ring = &mhi_event->ring;
404
405 if (mhi_event->offload_ev)
406 continue;
407
408 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
409 ring->pre_aligned, ring->dma_handle);
410 }
411 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
412 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
413 mhi_ctxt->er_ctxt_addr);
414
415error_alloc_er_ctxt:
416 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
417 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
418 mhi_ctxt->chan_ctxt_addr);
419
420error_alloc_chan_ctxt:
421 kfree(mhi_ctxt);
422
423 return ret;
424}
425
426int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
427{
428 u32 val;
429 int i, ret;
430 struct mhi_chan *mhi_chan;
431 struct mhi_event *mhi_event;
432 void __iomem *base = mhi_cntrl->regs;
433 struct device *dev = &mhi_cntrl->mhi_dev->dev;
434 struct {
435 u32 offset;
436 u32 mask;
437 u32 shift;
438 u32 val;
439 } reg_info[] = {
440 {
441 CCABAP_HIGHER, U32_MAX, 0,
442 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
443 },
444 {
445 CCABAP_LOWER, U32_MAX, 0,
446 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
447 },
448 {
449 ECABAP_HIGHER, U32_MAX, 0,
450 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
451 },
452 {
453 ECABAP_LOWER, U32_MAX, 0,
454 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
455 },
456 {
457 CRCBAP_HIGHER, U32_MAX, 0,
458 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
459 },
460 {
461 CRCBAP_LOWER, U32_MAX, 0,
462 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
463 },
464 {
465 MHICFG, MHICFG_NER_MASK, MHICFG_NER_SHIFT,
466 mhi_cntrl->total_ev_rings,
467 },
468 {
469 MHICFG, MHICFG_NHWER_MASK, MHICFG_NHWER_SHIFT,
470 mhi_cntrl->hw_ev_rings,
471 },
472 {
473 MHICTRLBASE_HIGHER, U32_MAX, 0,
474 upper_32_bits(mhi_cntrl->iova_start),
475 },
476 {
477 MHICTRLBASE_LOWER, U32_MAX, 0,
478 lower_32_bits(mhi_cntrl->iova_start),
479 },
480 {
481 MHIDATABASE_HIGHER, U32_MAX, 0,
482 upper_32_bits(mhi_cntrl->iova_start),
483 },
484 {
485 MHIDATABASE_LOWER, U32_MAX, 0,
486 lower_32_bits(mhi_cntrl->iova_start),
487 },
488 {
489 MHICTRLLIMIT_HIGHER, U32_MAX, 0,
490 upper_32_bits(mhi_cntrl->iova_stop),
491 },
492 {
493 MHICTRLLIMIT_LOWER, U32_MAX, 0,
494 lower_32_bits(mhi_cntrl->iova_stop),
495 },
496 {
497 MHIDATALIMIT_HIGHER, U32_MAX, 0,
498 upper_32_bits(mhi_cntrl->iova_stop),
499 },
500 {
501 MHIDATALIMIT_LOWER, U32_MAX, 0,
502 lower_32_bits(mhi_cntrl->iova_stop),
503 },
504 { 0, 0, 0 }
505 };
506
507 dev_dbg(dev, "Initializing MHI registers\n");
508
509
510 ret = mhi_read_reg_field(mhi_cntrl, base, CHDBOFF, CHDBOFF_CHDBOFF_MASK,
511 CHDBOFF_CHDBOFF_SHIFT, &val);
512 if (ret) {
513 dev_err(dev, "Unable to read CHDBOFF register\n");
514 return -EIO;
515 }
516
517
518 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
519 mhi_cntrl->wake_set = false;
520
521
522 mhi_chan = mhi_cntrl->mhi_chan;
523 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++)
524 mhi_chan->tre_ring.db_addr = base + val;
525
526
527 ret = mhi_read_reg_field(mhi_cntrl, base, ERDBOFF, ERDBOFF_ERDBOFF_MASK,
528 ERDBOFF_ERDBOFF_SHIFT, &val);
529 if (ret) {
530 dev_err(dev, "Unable to read ERDBOFF register\n");
531 return -EIO;
532 }
533
534
535 mhi_event = mhi_cntrl->mhi_event;
536 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
537 if (mhi_event->offload_ev)
538 continue;
539
540 mhi_event->ring.db_addr = base + val;
541 }
542
543
544 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
545
546
547 for (i = 0; reg_info[i].offset; i++)
548 mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset,
549 reg_info[i].mask, reg_info[i].shift,
550 reg_info[i].val);
551
552 return 0;
553}
554
555void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
556 struct mhi_chan *mhi_chan)
557{
558 struct mhi_ring *buf_ring;
559 struct mhi_ring *tre_ring;
560 struct mhi_chan_ctxt *chan_ctxt;
561 u32 tmp;
562
563 buf_ring = &mhi_chan->buf_ring;
564 tre_ring = &mhi_chan->tre_ring;
565 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
566
567 if (!chan_ctxt->rbase)
568 return;
569
570 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
571 tre_ring->pre_aligned, tre_ring->dma_handle);
572 vfree(buf_ring->base);
573
574 buf_ring->base = tre_ring->base = NULL;
575 tre_ring->ctxt_wp = NULL;
576 chan_ctxt->rbase = 0;
577 chan_ctxt->rlen = 0;
578 chan_ctxt->rp = 0;
579 chan_ctxt->wp = 0;
580
581 tmp = chan_ctxt->chcfg;
582 tmp &= ~CHAN_CTX_CHSTATE_MASK;
583 tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT);
584 chan_ctxt->chcfg = tmp;
585
586
587 smp_wmb();
588}
589
590int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
591 struct mhi_chan *mhi_chan)
592{
593 struct mhi_ring *buf_ring;
594 struct mhi_ring *tre_ring;
595 struct mhi_chan_ctxt *chan_ctxt;
596 u32 tmp;
597 int ret;
598
599 buf_ring = &mhi_chan->buf_ring;
600 tre_ring = &mhi_chan->tre_ring;
601 tre_ring->el_size = sizeof(struct mhi_tre);
602 tre_ring->len = tre_ring->el_size * tre_ring->elements;
603 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
604 ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len);
605 if (ret)
606 return -ENOMEM;
607
608 buf_ring->el_size = sizeof(struct mhi_buf_info);
609 buf_ring->len = buf_ring->el_size * buf_ring->elements;
610 buf_ring->base = vzalloc(buf_ring->len);
611
612 if (!buf_ring->base) {
613 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
614 tre_ring->pre_aligned, tre_ring->dma_handle);
615 return -ENOMEM;
616 }
617
618 tmp = chan_ctxt->chcfg;
619 tmp &= ~CHAN_CTX_CHSTATE_MASK;
620 tmp |= (MHI_CH_STATE_ENABLED << CHAN_CTX_CHSTATE_SHIFT);
621 chan_ctxt->chcfg = tmp;
622
623 chan_ctxt->rbase = tre_ring->iommu_base;
624 chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase;
625 chan_ctxt->rlen = tre_ring->len;
626 tre_ring->ctxt_wp = &chan_ctxt->wp;
627
628 tre_ring->rp = tre_ring->wp = tre_ring->base;
629 buf_ring->rp = buf_ring->wp = buf_ring->base;
630 mhi_chan->db_cfg.db_mode = 1;
631
632
633 smp_wmb();
634
635 return 0;
636}
637
638static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,
639 const struct mhi_controller_config *config)
640{
641 struct mhi_event *mhi_event;
642 const struct mhi_event_config *event_cfg;
643 struct device *dev = mhi_cntrl->cntrl_dev;
644 int i, num;
645
646 num = config->num_events;
647 mhi_cntrl->total_ev_rings = num;
648 mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event),
649 GFP_KERNEL);
650 if (!mhi_cntrl->mhi_event)
651 return -ENOMEM;
652
653
654 mhi_event = mhi_cntrl->mhi_event;
655 for (i = 0; i < num; i++) {
656 event_cfg = &config->event_cfg[i];
657
658 mhi_event->er_index = i;
659 mhi_event->ring.elements = event_cfg->num_elements;
660 mhi_event->intmod = event_cfg->irq_moderation_ms;
661 mhi_event->irq = event_cfg->irq;
662
663 if (event_cfg->channel != U32_MAX) {
664
665 mhi_event->chan = event_cfg->channel;
666 if (mhi_event->chan >= mhi_cntrl->max_chan) {
667 dev_err(dev,
668 "Event Ring channel not available\n");
669 goto error_ev_cfg;
670 }
671
672 mhi_event->mhi_chan =
673 &mhi_cntrl->mhi_chan[mhi_event->chan];
674 }
675
676
677 mhi_event->priority = 1;
678
679 mhi_event->db_cfg.brstmode = event_cfg->mode;
680 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode))
681 goto error_ev_cfg;
682
683 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
684 mhi_event->db_cfg.process_db = mhi_db_brstmode;
685 else
686 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable;
687
688 mhi_event->data_type = event_cfg->data_type;
689
690 switch (mhi_event->data_type) {
691 case MHI_ER_DATA:
692 mhi_event->process_event = mhi_process_data_event_ring;
693 break;
694 case MHI_ER_CTRL:
695 mhi_event->process_event = mhi_process_ctrl_ev_ring;
696 break;
697 default:
698 dev_err(dev, "Event Ring type not supported\n");
699 goto error_ev_cfg;
700 }
701
702 mhi_event->hw_ring = event_cfg->hardware_event;
703 if (mhi_event->hw_ring)
704 mhi_cntrl->hw_ev_rings++;
705 else
706 mhi_cntrl->sw_ev_rings++;
707
708 mhi_event->cl_manage = event_cfg->client_managed;
709 mhi_event->offload_ev = event_cfg->offload_channel;
710 mhi_event++;
711 }
712
713 return 0;
714
715error_ev_cfg:
716
717 kfree(mhi_cntrl->mhi_event);
718 return -EINVAL;
719}
720
721static int parse_ch_cfg(struct mhi_controller *mhi_cntrl,
722 const struct mhi_controller_config *config)
723{
724 const struct mhi_channel_config *ch_cfg;
725 struct device *dev = mhi_cntrl->cntrl_dev;
726 int i;
727 u32 chan;
728
729 mhi_cntrl->max_chan = config->max_channels;
730
731
732
733
734
735
736 mhi_cntrl->mhi_chan = vzalloc(mhi_cntrl->max_chan *
737 sizeof(*mhi_cntrl->mhi_chan));
738 if (!mhi_cntrl->mhi_chan)
739 return -ENOMEM;
740
741 INIT_LIST_HEAD(&mhi_cntrl->lpm_chans);
742
743
744 for (i = 0; i < config->num_channels; i++) {
745 struct mhi_chan *mhi_chan;
746
747 ch_cfg = &config->ch_cfg[i];
748
749 chan = ch_cfg->num;
750 if (chan >= mhi_cntrl->max_chan) {
751 dev_err(dev, "Channel %d not available\n", chan);
752 goto error_chan_cfg;
753 }
754
755 mhi_chan = &mhi_cntrl->mhi_chan[chan];
756 mhi_chan->name = ch_cfg->name;
757 mhi_chan->chan = chan;
758
759 mhi_chan->tre_ring.elements = ch_cfg->num_elements;
760 if (!mhi_chan->tre_ring.elements)
761 goto error_chan_cfg;
762
763
764
765
766
767
768
769
770 mhi_chan->buf_ring.elements = ch_cfg->local_elements;
771 if (!mhi_chan->buf_ring.elements)
772 mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements;
773 mhi_chan->er_index = ch_cfg->event_ring;
774 mhi_chan->dir = ch_cfg->dir;
775
776
777
778
779
780
781 mhi_chan->type = ch_cfg->type;
782 if (!mhi_chan->type)
783 mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir;
784
785 mhi_chan->ee_mask = ch_cfg->ee_mask;
786 mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg;
787 mhi_chan->lpm_notify = ch_cfg->lpm_notify;
788 mhi_chan->offload_ch = ch_cfg->offload_channel;
789 mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch;
790 mhi_chan->pre_alloc = ch_cfg->auto_queue;
791
792
793
794
795
796 if (mhi_chan->pre_alloc && mhi_chan->dir != DMA_FROM_DEVICE) {
797 dev_err(dev, "Invalid channel configuration\n");
798 goto error_chan_cfg;
799 }
800
801
802
803
804
805 if ((mhi_chan->dir == DMA_BIDIRECTIONAL ||
806 mhi_chan->dir == DMA_NONE) && !mhi_chan->offload_ch) {
807 dev_err(dev, "Invalid channel configuration\n");
808 goto error_chan_cfg;
809 }
810
811 if (!mhi_chan->offload_ch) {
812 mhi_chan->db_cfg.brstmode = ch_cfg->doorbell;
813 if (MHI_INVALID_BRSTMODE(mhi_chan->db_cfg.brstmode)) {
814 dev_err(dev, "Invalid Door bell mode\n");
815 goto error_chan_cfg;
816 }
817 }
818
819 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
820 mhi_chan->db_cfg.process_db = mhi_db_brstmode;
821 else
822 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable;
823
824 mhi_chan->configured = true;
825
826 if (mhi_chan->lpm_notify)
827 list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans);
828 }
829
830 return 0;
831
832error_chan_cfg:
833 vfree(mhi_cntrl->mhi_chan);
834
835 return -EINVAL;
836}
837
838static int parse_config(struct mhi_controller *mhi_cntrl,
839 const struct mhi_controller_config *config)
840{
841 int ret;
842
843
844 ret = parse_ch_cfg(mhi_cntrl, config);
845 if (ret)
846 return ret;
847
848
849 ret = parse_ev_cfg(mhi_cntrl, config);
850 if (ret)
851 goto error_ev_cfg;
852
853 mhi_cntrl->timeout_ms = config->timeout_ms;
854 if (!mhi_cntrl->timeout_ms)
855 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
856
857 mhi_cntrl->bounce_buf = config->use_bounce_buf;
858 mhi_cntrl->buffer_len = config->buf_len;
859 if (!mhi_cntrl->buffer_len)
860 mhi_cntrl->buffer_len = MHI_MAX_MTU;
861
862
863 mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2;
864 if (config->m2_no_db)
865 mhi_cntrl->db_access &= ~MHI_PM_M2;
866
867 return 0;
868
869error_ev_cfg:
870 vfree(mhi_cntrl->mhi_chan);
871
872 return ret;
873}
874
875int mhi_register_controller(struct mhi_controller *mhi_cntrl,
876 const struct mhi_controller_config *config)
877{
878 struct mhi_event *mhi_event;
879 struct mhi_chan *mhi_chan;
880 struct mhi_cmd *mhi_cmd;
881 struct mhi_device *mhi_dev;
882 u32 soc_info;
883 int ret, i;
884
885 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
886 !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
887 !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
888 !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
889 !mhi_cntrl->irq || !mhi_cntrl->reg_len)
890 return -EINVAL;
891
892 ret = parse_config(mhi_cntrl, config);
893 if (ret)
894 return -EINVAL;
895
896 mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS,
897 sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL);
898 if (!mhi_cntrl->mhi_cmd) {
899 ret = -ENOMEM;
900 goto err_free_event;
901 }
902
903 INIT_LIST_HEAD(&mhi_cntrl->transition_list);
904 mutex_init(&mhi_cntrl->pm_mutex);
905 rwlock_init(&mhi_cntrl->pm_lock);
906 spin_lock_init(&mhi_cntrl->transition_lock);
907 spin_lock_init(&mhi_cntrl->wlock);
908 INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker);
909 init_waitqueue_head(&mhi_cntrl->state_event);
910
911 mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI);
912 if (!mhi_cntrl->hiprio_wq) {
913 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n");
914 ret = -ENOMEM;
915 goto err_free_cmd;
916 }
917
918 mhi_cmd = mhi_cntrl->mhi_cmd;
919 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++)
920 spin_lock_init(&mhi_cmd->lock);
921
922 mhi_event = mhi_cntrl->mhi_event;
923 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
924
925 if (mhi_event->offload_ev)
926 continue;
927
928 mhi_event->mhi_cntrl = mhi_cntrl;
929 spin_lock_init(&mhi_event->lock);
930 if (mhi_event->data_type == MHI_ER_CTRL)
931 tasklet_init(&mhi_event->task, mhi_ctrl_ev_task,
932 (ulong)mhi_event);
933 else
934 tasklet_init(&mhi_event->task, mhi_ev_task,
935 (ulong)mhi_event);
936 }
937
938 mhi_chan = mhi_cntrl->mhi_chan;
939 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
940 mutex_init(&mhi_chan->mutex);
941 init_completion(&mhi_chan->completion);
942 rwlock_init(&mhi_chan->lock);
943
944
945 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index];
946 mhi_chan->intmod = mhi_event->intmod;
947 }
948
949 if (mhi_cntrl->bounce_buf) {
950 mhi_cntrl->map_single = mhi_map_single_use_bb;
951 mhi_cntrl->unmap_single = mhi_unmap_single_use_bb;
952 } else {
953 mhi_cntrl->map_single = mhi_map_single_no_bb;
954 mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;
955 }
956
957
958 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,
959 SOC_HW_VERSION_OFFS, &soc_info);
960 if (ret)
961 goto err_destroy_wq;
962
963 mhi_cntrl->family_number = (soc_info & SOC_HW_VERSION_FAM_NUM_BMSK) >>
964 SOC_HW_VERSION_FAM_NUM_SHFT;
965 mhi_cntrl->device_number = (soc_info & SOC_HW_VERSION_DEV_NUM_BMSK) >>
966 SOC_HW_VERSION_DEV_NUM_SHFT;
967 mhi_cntrl->major_version = (soc_info & SOC_HW_VERSION_MAJOR_VER_BMSK) >>
968 SOC_HW_VERSION_MAJOR_VER_SHFT;
969 mhi_cntrl->minor_version = (soc_info & SOC_HW_VERSION_MINOR_VER_BMSK) >>
970 SOC_HW_VERSION_MINOR_VER_SHFT;
971
972 mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL);
973 if (mhi_cntrl->index < 0) {
974 ret = mhi_cntrl->index;
975 goto err_destroy_wq;
976 }
977
978
979 mhi_dev = mhi_alloc_device(mhi_cntrl);
980 if (IS_ERR(mhi_dev)) {
981 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n");
982 ret = PTR_ERR(mhi_dev);
983 goto err_ida_free;
984 }
985
986 mhi_dev->dev_type = MHI_DEVICE_CONTROLLER;
987 mhi_dev->mhi_cntrl = mhi_cntrl;
988 dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index);
989 mhi_dev->name = dev_name(&mhi_dev->dev);
990
991
992 device_init_wakeup(&mhi_dev->dev, true);
993
994 ret = device_add(&mhi_dev->dev);
995 if (ret)
996 goto err_release_dev;
997
998 mhi_cntrl->mhi_dev = mhi_dev;
999
1000 mhi_create_debugfs(mhi_cntrl);
1001
1002 return 0;
1003
1004err_release_dev:
1005 put_device(&mhi_dev->dev);
1006err_ida_free:
1007 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1008err_destroy_wq:
1009 destroy_workqueue(mhi_cntrl->hiprio_wq);
1010err_free_cmd:
1011 kfree(mhi_cntrl->mhi_cmd);
1012err_free_event:
1013 kfree(mhi_cntrl->mhi_event);
1014 vfree(mhi_cntrl->mhi_chan);
1015
1016 return ret;
1017}
1018EXPORT_SYMBOL_GPL(mhi_register_controller);
1019
1020void mhi_unregister_controller(struct mhi_controller *mhi_cntrl)
1021{
1022 struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev;
1023 struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan;
1024 unsigned int i;
1025
1026 mhi_destroy_debugfs(mhi_cntrl);
1027
1028 destroy_workqueue(mhi_cntrl->hiprio_wq);
1029 kfree(mhi_cntrl->mhi_cmd);
1030 kfree(mhi_cntrl->mhi_event);
1031
1032
1033 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
1034 if (!mhi_chan->mhi_dev)
1035 continue;
1036
1037 put_device(&mhi_chan->mhi_dev->dev);
1038 }
1039 vfree(mhi_cntrl->mhi_chan);
1040
1041 device_del(&mhi_dev->dev);
1042 put_device(&mhi_dev->dev);
1043
1044 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1045}
1046EXPORT_SYMBOL_GPL(mhi_unregister_controller);
1047
1048struct mhi_controller *mhi_alloc_controller(void)
1049{
1050 struct mhi_controller *mhi_cntrl;
1051
1052 mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL);
1053
1054 return mhi_cntrl;
1055}
1056EXPORT_SYMBOL_GPL(mhi_alloc_controller);
1057
1058void mhi_free_controller(struct mhi_controller *mhi_cntrl)
1059{
1060 kfree(mhi_cntrl);
1061}
1062EXPORT_SYMBOL_GPL(mhi_free_controller);
1063
1064int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
1065{
1066 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1067 u32 bhi_off, bhie_off;
1068 int ret;
1069
1070 mutex_lock(&mhi_cntrl->pm_mutex);
1071
1072 ret = mhi_init_dev_ctxt(mhi_cntrl);
1073 if (ret)
1074 goto error_dev_ctxt;
1075
1076 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
1077 if (ret) {
1078 dev_err(dev, "Error getting BHI offset\n");
1079 goto error_reg_offset;
1080 }
1081
1082 if (bhi_off >= mhi_cntrl->reg_len) {
1083 dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
1084 bhi_off, mhi_cntrl->reg_len);
1085 ret = -EINVAL;
1086 goto error_reg_offset;
1087 }
1088 mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
1089
1090 if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
1091 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
1092 &bhie_off);
1093 if (ret) {
1094 dev_err(dev, "Error getting BHIE offset\n");
1095 goto error_reg_offset;
1096 }
1097
1098 if (bhie_off >= mhi_cntrl->reg_len) {
1099 dev_err(dev,
1100 "BHIe offset: 0x%x is out of range: 0x%zx\n",
1101 bhie_off, mhi_cntrl->reg_len);
1102 ret = -EINVAL;
1103 goto error_reg_offset;
1104 }
1105 mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
1106 }
1107
1108 if (mhi_cntrl->rddm_size) {
1109
1110
1111
1112
1113 memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
1114 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
1115 4);
1116
1117
1118
1119 mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
1120 mhi_cntrl->rddm_size);
1121 if (mhi_cntrl->rddm_image)
1122 mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
1123 }
1124
1125 mutex_unlock(&mhi_cntrl->pm_mutex);
1126
1127 return 0;
1128
1129error_reg_offset:
1130 mhi_deinit_dev_ctxt(mhi_cntrl);
1131
1132error_dev_ctxt:
1133 mutex_unlock(&mhi_cntrl->pm_mutex);
1134
1135 return ret;
1136}
1137EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up);
1138
1139void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
1140{
1141 if (mhi_cntrl->fbc_image) {
1142 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1143 mhi_cntrl->fbc_image = NULL;
1144 }
1145
1146 if (mhi_cntrl->rddm_image) {
1147 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
1148 mhi_cntrl->rddm_image = NULL;
1149 }
1150
1151 mhi_cntrl->bhi = NULL;
1152 mhi_cntrl->bhie = NULL;
1153
1154 mhi_deinit_dev_ctxt(mhi_cntrl);
1155}
1156EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
1157
1158static void mhi_release_device(struct device *dev)
1159{
1160 struct mhi_device *mhi_dev = to_mhi_device(dev);
1161
1162
1163
1164
1165
1166
1167
1168 if (mhi_dev->ul_chan)
1169 mhi_dev->ul_chan->mhi_dev = NULL;
1170
1171 if (mhi_dev->dl_chan)
1172 mhi_dev->dl_chan->mhi_dev = NULL;
1173
1174 kfree(mhi_dev);
1175}
1176
1177struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl)
1178{
1179 struct mhi_device *mhi_dev;
1180 struct device *dev;
1181
1182 mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL);
1183 if (!mhi_dev)
1184 return ERR_PTR(-ENOMEM);
1185
1186 dev = &mhi_dev->dev;
1187 device_initialize(dev);
1188 dev->bus = &mhi_bus_type;
1189 dev->release = mhi_release_device;
1190
1191 if (mhi_cntrl->mhi_dev) {
1192
1193 dev->parent = &mhi_cntrl->mhi_dev->dev;
1194 } else {
1195
1196 dev->parent = mhi_cntrl->cntrl_dev;
1197 }
1198
1199 mhi_dev->mhi_cntrl = mhi_cntrl;
1200 mhi_dev->dev_wake = 0;
1201
1202 return mhi_dev;
1203}
1204
1205static int mhi_driver_probe(struct device *dev)
1206{
1207 struct mhi_device *mhi_dev = to_mhi_device(dev);
1208 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1209 struct device_driver *drv = dev->driver;
1210 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1211 struct mhi_event *mhi_event;
1212 struct mhi_chan *ul_chan = mhi_dev->ul_chan;
1213 struct mhi_chan *dl_chan = mhi_dev->dl_chan;
1214 int ret;
1215
1216
1217 ret = mhi_device_get_sync(mhi_dev);
1218 if (ret)
1219 return ret;
1220
1221 ret = -EINVAL;
1222
1223 if (ul_chan) {
1224
1225
1226
1227
1228 if (ul_chan->lpm_notify && !mhi_drv->status_cb)
1229 goto exit_probe;
1230
1231
1232 if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb)
1233 goto exit_probe;
1234
1235 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb;
1236 }
1237
1238 ret = -EINVAL;
1239 if (dl_chan) {
1240
1241
1242
1243
1244 if (dl_chan->lpm_notify && !mhi_drv->status_cb)
1245 goto exit_probe;
1246
1247
1248 if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb)
1249 goto exit_probe;
1250
1251 mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index];
1252
1253
1254
1255
1256
1257
1258 if (mhi_event->cl_manage && !mhi_drv->status_cb)
1259 goto exit_probe;
1260
1261 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb;
1262 }
1263
1264
1265 ret = mhi_drv->probe(mhi_dev, mhi_dev->id);
1266 if (ret)
1267 goto exit_probe;
1268
1269 mhi_device_put(mhi_dev);
1270
1271 return ret;
1272
1273exit_probe:
1274 mhi_unprepare_from_transfer(mhi_dev);
1275
1276 mhi_device_put(mhi_dev);
1277
1278 return ret;
1279}
1280
1281static int mhi_driver_remove(struct device *dev)
1282{
1283 struct mhi_device *mhi_dev = to_mhi_device(dev);
1284 struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver);
1285 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1286 struct mhi_chan *mhi_chan;
1287 enum mhi_ch_state ch_state[] = {
1288 MHI_CH_STATE_DISABLED,
1289 MHI_CH_STATE_DISABLED
1290 };
1291 int dir;
1292
1293
1294 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1295 return 0;
1296
1297
1298 for (dir = 0; dir < 2; dir++) {
1299 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1300
1301 if (!mhi_chan)
1302 continue;
1303
1304
1305 write_lock_irq(&mhi_chan->lock);
1306 mhi_chan->ccs = MHI_EV_CC_INVALID;
1307 complete_all(&mhi_chan->completion);
1308 write_unlock_irq(&mhi_chan->lock);
1309
1310
1311 mutex_lock(&mhi_chan->mutex);
1312 write_lock_irq(&mhi_chan->lock);
1313 ch_state[dir] = mhi_chan->ch_state;
1314 mhi_chan->ch_state = MHI_CH_STATE_SUSPENDED;
1315 write_unlock_irq(&mhi_chan->lock);
1316
1317
1318 if (!mhi_chan->offload_ch)
1319 mhi_reset_chan(mhi_cntrl, mhi_chan);
1320
1321 mutex_unlock(&mhi_chan->mutex);
1322 }
1323
1324 mhi_drv->remove(mhi_dev);
1325
1326
1327 for (dir = 0; dir < 2; dir++) {
1328 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1329
1330 if (!mhi_chan)
1331 continue;
1332
1333 mutex_lock(&mhi_chan->mutex);
1334
1335 if ((ch_state[dir] == MHI_CH_STATE_ENABLED ||
1336 ch_state[dir] == MHI_CH_STATE_STOP) &&
1337 !mhi_chan->offload_ch)
1338 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan);
1339
1340 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
1341
1342 mutex_unlock(&mhi_chan->mutex);
1343 }
1344
1345 while (mhi_dev->dev_wake)
1346 mhi_device_put(mhi_dev);
1347
1348 return 0;
1349}
1350
1351int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner)
1352{
1353 struct device_driver *driver = &mhi_drv->driver;
1354
1355 if (!mhi_drv->probe || !mhi_drv->remove)
1356 return -EINVAL;
1357
1358 driver->bus = &mhi_bus_type;
1359 driver->owner = owner;
1360 driver->probe = mhi_driver_probe;
1361 driver->remove = mhi_driver_remove;
1362
1363 return driver_register(driver);
1364}
1365EXPORT_SYMBOL_GPL(__mhi_driver_register);
1366
1367void mhi_driver_unregister(struct mhi_driver *mhi_drv)
1368{
1369 driver_unregister(&mhi_drv->driver);
1370}
1371EXPORT_SYMBOL_GPL(mhi_driver_unregister);
1372
1373static int mhi_uevent(struct device *dev, struct kobj_uevent_env *env)
1374{
1375 struct mhi_device *mhi_dev = to_mhi_device(dev);
1376
1377 return add_uevent_var(env, "MODALIAS=" MHI_DEVICE_MODALIAS_FMT,
1378 mhi_dev->name);
1379}
1380
1381static int mhi_match(struct device *dev, struct device_driver *drv)
1382{
1383 struct mhi_device *mhi_dev = to_mhi_device(dev);
1384 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1385 const struct mhi_device_id *id;
1386
1387
1388
1389
1390
1391 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1392 return 0;
1393
1394 for (id = mhi_drv->id_table; id->chan[0]; id++)
1395 if (!strcmp(mhi_dev->name, id->chan)) {
1396 mhi_dev->id = id;
1397 return 1;
1398 }
1399
1400 return 0;
1401};
1402
1403struct bus_type mhi_bus_type = {
1404 .name = "mhi",
1405 .dev_name = "mhi",
1406 .match = mhi_match,
1407 .uevent = mhi_uevent,
1408 .dev_groups = mhi_dev_groups,
1409};
1410
1411static int __init mhi_init(void)
1412{
1413 mhi_debugfs_init();
1414 return bus_register(&mhi_bus_type);
1415}
1416
1417static void __exit mhi_exit(void)
1418{
1419 mhi_debugfs_exit();
1420 bus_unregister(&mhi_bus_type);
1421}
1422
1423postcore_initcall(mhi_init);
1424module_exit(mhi_exit);
1425
1426MODULE_LICENSE("GPL v2");
1427MODULE_DESCRIPTION("MHI Host Interface");
1428
