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27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/clk.h>
30#include <linux/debugfs.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33#include <linux/module.h>
34#include <linux/of_device.h>
35#include <linux/platform_device.h>
36#include <linux/slab.h>
37#include <dt-bindings/clock/bcm2835.h>
38
39#define CM_PASSWORD 0x5a000000
40
41#define CM_GNRICCTL 0x000
42#define CM_GNRICDIV 0x004
43# define CM_DIV_FRAC_BITS 12
44# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
45
46#define CM_VPUCTL 0x008
47#define CM_VPUDIV 0x00c
48#define CM_SYSCTL 0x010
49#define CM_SYSDIV 0x014
50#define CM_PERIACTL 0x018
51#define CM_PERIADIV 0x01c
52#define CM_PERIICTL 0x020
53#define CM_PERIIDIV 0x024
54#define CM_H264CTL 0x028
55#define CM_H264DIV 0x02c
56#define CM_ISPCTL 0x030
57#define CM_ISPDIV 0x034
58#define CM_V3DCTL 0x038
59#define CM_V3DDIV 0x03c
60#define CM_CAM0CTL 0x040
61#define CM_CAM0DIV 0x044
62#define CM_CAM1CTL 0x048
63#define CM_CAM1DIV 0x04c
64#define CM_CCP2CTL 0x050
65#define CM_CCP2DIV 0x054
66#define CM_DSI0ECTL 0x058
67#define CM_DSI0EDIV 0x05c
68#define CM_DSI0PCTL 0x060
69#define CM_DSI0PDIV 0x064
70#define CM_DPICTL 0x068
71#define CM_DPIDIV 0x06c
72#define CM_GP0CTL 0x070
73#define CM_GP0DIV 0x074
74#define CM_GP1CTL 0x078
75#define CM_GP1DIV 0x07c
76#define CM_GP2CTL 0x080
77#define CM_GP2DIV 0x084
78#define CM_HSMCTL 0x088
79#define CM_HSMDIV 0x08c
80#define CM_OTPCTL 0x090
81#define CM_OTPDIV 0x094
82#define CM_PCMCTL 0x098
83#define CM_PCMDIV 0x09c
84#define CM_PWMCTL 0x0a0
85#define CM_PWMDIV 0x0a4
86#define CM_SLIMCTL 0x0a8
87#define CM_SLIMDIV 0x0ac
88#define CM_SMICTL 0x0b0
89#define CM_SMIDIV 0x0b4
90
91#define CM_TCNTCTL 0x0c0
92# define CM_TCNT_SRC1_SHIFT 12
93#define CM_TCNTCNT 0x0c4
94#define CM_TECCTL 0x0c8
95#define CM_TECDIV 0x0cc
96#define CM_TD0CTL 0x0d0
97#define CM_TD0DIV 0x0d4
98#define CM_TD1CTL 0x0d8
99#define CM_TD1DIV 0x0dc
100#define CM_TSENSCTL 0x0e0
101#define CM_TSENSDIV 0x0e4
102#define CM_TIMERCTL 0x0e8
103#define CM_TIMERDIV 0x0ec
104#define CM_UARTCTL 0x0f0
105#define CM_UARTDIV 0x0f4
106#define CM_VECCTL 0x0f8
107#define CM_VECDIV 0x0fc
108#define CM_PULSECTL 0x190
109#define CM_PULSEDIV 0x194
110#define CM_SDCCTL 0x1a8
111#define CM_SDCDIV 0x1ac
112#define CM_ARMCTL 0x1b0
113#define CM_AVEOCTL 0x1b8
114#define CM_AVEODIV 0x1bc
115#define CM_EMMCCTL 0x1c0
116#define CM_EMMCDIV 0x1c4
117#define CM_EMMC2CTL 0x1d0
118#define CM_EMMC2DIV 0x1d4
119
120
121# define CM_ENABLE BIT(4)
122# define CM_KILL BIT(5)
123# define CM_GATE_BIT 6
124# define CM_GATE BIT(CM_GATE_BIT)
125# define CM_BUSY BIT(7)
126# define CM_BUSYD BIT(8)
127# define CM_FRAC BIT(9)
128# define CM_SRC_SHIFT 0
129# define CM_SRC_BITS 4
130# define CM_SRC_MASK 0xf
131# define CM_SRC_GND 0
132# define CM_SRC_OSC 1
133# define CM_SRC_TESTDEBUG0 2
134# define CM_SRC_TESTDEBUG1 3
135# define CM_SRC_PLLA_CORE 4
136# define CM_SRC_PLLA_PER 4
137# define CM_SRC_PLLC_CORE0 5
138# define CM_SRC_PLLC_PER 5
139# define CM_SRC_PLLC_CORE1 8
140# define CM_SRC_PLLD_CORE 6
141# define CM_SRC_PLLD_PER 6
142# define CM_SRC_PLLH_AUX 7
143# define CM_SRC_PLLC_CORE1 8
144# define CM_SRC_PLLC_CORE2 9
145
146#define CM_OSCCOUNT 0x100
147
148#define CM_PLLA 0x104
149# define CM_PLL_ANARST BIT(8)
150# define CM_PLLA_HOLDPER BIT(7)
151# define CM_PLLA_LOADPER BIT(6)
152# define CM_PLLA_HOLDCORE BIT(5)
153# define CM_PLLA_LOADCORE BIT(4)
154# define CM_PLLA_HOLDCCP2 BIT(3)
155# define CM_PLLA_LOADCCP2 BIT(2)
156# define CM_PLLA_HOLDDSI0 BIT(1)
157# define CM_PLLA_LOADDSI0 BIT(0)
158
159#define CM_PLLC 0x108
160# define CM_PLLC_HOLDPER BIT(7)
161# define CM_PLLC_LOADPER BIT(6)
162# define CM_PLLC_HOLDCORE2 BIT(5)
163# define CM_PLLC_LOADCORE2 BIT(4)
164# define CM_PLLC_HOLDCORE1 BIT(3)
165# define CM_PLLC_LOADCORE1 BIT(2)
166# define CM_PLLC_HOLDCORE0 BIT(1)
167# define CM_PLLC_LOADCORE0 BIT(0)
168
169#define CM_PLLD 0x10c
170# define CM_PLLD_HOLDPER BIT(7)
171# define CM_PLLD_LOADPER BIT(6)
172# define CM_PLLD_HOLDCORE BIT(5)
173# define CM_PLLD_LOADCORE BIT(4)
174# define CM_PLLD_HOLDDSI1 BIT(3)
175# define CM_PLLD_LOADDSI1 BIT(2)
176# define CM_PLLD_HOLDDSI0 BIT(1)
177# define CM_PLLD_LOADDSI0 BIT(0)
178
179#define CM_PLLH 0x110
180# define CM_PLLH_LOADRCAL BIT(2)
181# define CM_PLLH_LOADAUX BIT(1)
182# define CM_PLLH_LOADPIX BIT(0)
183
184#define CM_LOCK 0x114
185# define CM_LOCK_FLOCKH BIT(12)
186# define CM_LOCK_FLOCKD BIT(11)
187# define CM_LOCK_FLOCKC BIT(10)
188# define CM_LOCK_FLOCKB BIT(9)
189# define CM_LOCK_FLOCKA BIT(8)
190
191#define CM_EVENT 0x118
192#define CM_DSI1ECTL 0x158
193#define CM_DSI1EDIV 0x15c
194#define CM_DSI1PCTL 0x160
195#define CM_DSI1PDIV 0x164
196#define CM_DFTCTL 0x168
197#define CM_DFTDIV 0x16c
198
199#define CM_PLLB 0x170
200# define CM_PLLB_HOLDARM BIT(1)
201# define CM_PLLB_LOADARM BIT(0)
202
203#define A2W_PLLA_CTRL 0x1100
204#define A2W_PLLC_CTRL 0x1120
205#define A2W_PLLD_CTRL 0x1140
206#define A2W_PLLH_CTRL 0x1160
207#define A2W_PLLB_CTRL 0x11e0
208# define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
209# define A2W_PLL_CTRL_PWRDN BIT(16)
210# define A2W_PLL_CTRL_PDIV_MASK 0x000007000
211# define A2W_PLL_CTRL_PDIV_SHIFT 12
212# define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
213# define A2W_PLL_CTRL_NDIV_SHIFT 0
214
215#define A2W_PLLA_ANA0 0x1010
216#define A2W_PLLC_ANA0 0x1030
217#define A2W_PLLD_ANA0 0x1050
218#define A2W_PLLH_ANA0 0x1070
219#define A2W_PLLB_ANA0 0x10f0
220
221#define A2W_PLL_KA_SHIFT 7
222#define A2W_PLL_KA_MASK GENMASK(9, 7)
223#define A2W_PLL_KI_SHIFT 19
224#define A2W_PLL_KI_MASK GENMASK(21, 19)
225#define A2W_PLL_KP_SHIFT 15
226#define A2W_PLL_KP_MASK GENMASK(18, 15)
227
228#define A2W_PLLH_KA_SHIFT 19
229#define A2W_PLLH_KA_MASK GENMASK(21, 19)
230#define A2W_PLLH_KI_LOW_SHIFT 22
231#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
232#define A2W_PLLH_KI_HIGH_SHIFT 0
233#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
234#define A2W_PLLH_KP_SHIFT 1
235#define A2W_PLLH_KP_MASK GENMASK(4, 1)
236
237#define A2W_XOSC_CTRL 0x1190
238# define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
239# define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
240# define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
241# define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
242# define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
243# define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
244# define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
245# define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
246
247#define A2W_PLLA_FRAC 0x1200
248#define A2W_PLLC_FRAC 0x1220
249#define A2W_PLLD_FRAC 0x1240
250#define A2W_PLLH_FRAC 0x1260
251#define A2W_PLLB_FRAC 0x12e0
252# define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
253# define A2W_PLL_FRAC_BITS 20
254
255#define A2W_PLL_CHANNEL_DISABLE BIT(8)
256#define A2W_PLL_DIV_BITS 8
257#define A2W_PLL_DIV_SHIFT 0
258
259#define A2W_PLLA_DSI0 0x1300
260#define A2W_PLLA_CORE 0x1400
261#define A2W_PLLA_PER 0x1500
262#define A2W_PLLA_CCP2 0x1600
263
264#define A2W_PLLC_CORE2 0x1320
265#define A2W_PLLC_CORE1 0x1420
266#define A2W_PLLC_PER 0x1520
267#define A2W_PLLC_CORE0 0x1620
268
269#define A2W_PLLD_DSI0 0x1340
270#define A2W_PLLD_CORE 0x1440
271#define A2W_PLLD_PER 0x1540
272#define A2W_PLLD_DSI1 0x1640
273
274#define A2W_PLLH_AUX 0x1360
275#define A2W_PLLH_RCAL 0x1460
276#define A2W_PLLH_PIX 0x1560
277#define A2W_PLLH_STS 0x1660
278
279#define A2W_PLLH_CTRLR 0x1960
280#define A2W_PLLH_FRACR 0x1a60
281#define A2W_PLLH_AUXR 0x1b60
282#define A2W_PLLH_RCALR 0x1c60
283#define A2W_PLLH_PIXR 0x1d60
284#define A2W_PLLH_STSR 0x1e60
285
286#define A2W_PLLB_ARM 0x13e0
287#define A2W_PLLB_SP0 0x14e0
288#define A2W_PLLB_SP1 0x15e0
289#define A2W_PLLB_SP2 0x16e0
290
291#define LOCK_TIMEOUT_NS 100000000
292#define BCM2835_MAX_FB_RATE 1750000000u
293
294#define SOC_BCM2835 BIT(0)
295#define SOC_BCM2711 BIT(1)
296#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
297
298
299
300
301
302
303static const char *const cprman_parent_names[] = {
304 "xosc",
305 "dsi0_byte",
306 "dsi0_ddr2",
307 "dsi0_ddr",
308 "dsi1_byte",
309 "dsi1_ddr2",
310 "dsi1_ddr",
311};
312
313struct bcm2835_cprman {
314 struct device *dev;
315 void __iomem *regs;
316 spinlock_t regs_lock;
317 unsigned int soc;
318
319
320
321
322
323
324 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
325
326
327 struct clk_hw_onecell_data onecell;
328};
329
330struct cprman_plat_data {
331 unsigned int soc;
332};
333
334static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
335{
336 writel(CM_PASSWORD | val, cprman->regs + reg);
337}
338
339static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
340{
341 return readl(cprman->regs + reg);
342}
343
344
345
346
347static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
348 u32 tcnt_mux)
349{
350 u32 osccount = 19200;
351 u32 count;
352 ktime_t timeout;
353
354 spin_lock(&cprman->regs_lock);
355
356 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
357
358 cprman_write(cprman, CM_TCNTCTL,
359 (tcnt_mux & CM_SRC_MASK) |
360 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
361
362 cprman_write(cprman, CM_OSCCOUNT, osccount);
363
364
365 mdelay(1);
366
367
368 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
369 while (cprman_read(cprman, CM_OSCCOUNT)) {
370 if (ktime_after(ktime_get(), timeout)) {
371 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
372 count = 0;
373 goto out;
374 }
375 cpu_relax();
376 }
377
378
379 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
380 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
381 if (ktime_after(ktime_get(), timeout)) {
382 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
383 count = 0;
384 goto out;
385 }
386 cpu_relax();
387 }
388
389 count = cprman_read(cprman, CM_TCNTCNT);
390
391 cprman_write(cprman, CM_TCNTCTL, 0);
392
393out:
394 spin_unlock(&cprman->regs_lock);
395
396 return count * 1000;
397}
398
399static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
400 const struct debugfs_reg32 *regs,
401 size_t nregs, struct dentry *dentry)
402{
403 struct debugfs_regset32 *regset;
404
405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
406 if (!regset)
407 return;
408
409 regset->regs = regs;
410 regset->nregs = nregs;
411 regset->base = cprman->regs + base;
412
413 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
414}
415
416struct bcm2835_pll_data {
417 const char *name;
418 u32 cm_ctrl_reg;
419 u32 a2w_ctrl_reg;
420 u32 frac_reg;
421 u32 ana_reg_base;
422 u32 reference_enable_mask;
423
424 u32 lock_mask;
425 u32 flags;
426
427 const struct bcm2835_pll_ana_bits *ana;
428
429 unsigned long min_rate;
430 unsigned long max_rate;
431
432
433
434
435 unsigned long max_fb_rate;
436};
437
438struct bcm2835_pll_ana_bits {
439 u32 mask0;
440 u32 set0;
441 u32 mask1;
442 u32 set1;
443 u32 mask3;
444 u32 set3;
445 u32 fb_prediv_mask;
446};
447
448static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
449 .mask0 = 0,
450 .set0 = 0,
451 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
452 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
453 .mask3 = A2W_PLL_KA_MASK,
454 .set3 = (2 << A2W_PLL_KA_SHIFT),
455 .fb_prediv_mask = BIT(14),
456};
457
458static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
459 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
460 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
461 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
462 .set1 = (6 << A2W_PLLH_KP_SHIFT),
463 .mask3 = 0,
464 .set3 = 0,
465 .fb_prediv_mask = BIT(11),
466};
467
468struct bcm2835_pll_divider_data {
469 const char *name;
470 const char *source_pll;
471
472 u32 cm_reg;
473 u32 a2w_reg;
474
475 u32 load_mask;
476 u32 hold_mask;
477 u32 fixed_divider;
478 u32 flags;
479};
480
481struct bcm2835_clock_data {
482 const char *name;
483
484 const char *const *parents;
485 int num_mux_parents;
486
487
488 unsigned int set_rate_parent;
489
490 u32 ctl_reg;
491 u32 div_reg;
492
493
494 u32 int_bits;
495
496 u32 frac_bits;
497
498 u32 flags;
499
500 bool is_vpu_clock;
501 bool is_mash_clock;
502 bool low_jitter;
503
504 u32 tcnt_mux;
505};
506
507struct bcm2835_gate_data {
508 const char *name;
509 const char *parent;
510
511 u32 ctl_reg;
512};
513
514struct bcm2835_pll {
515 struct clk_hw hw;
516 struct bcm2835_cprman *cprman;
517 const struct bcm2835_pll_data *data;
518};
519
520static int bcm2835_pll_is_on(struct clk_hw *hw)
521{
522 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
523 struct bcm2835_cprman *cprman = pll->cprman;
524 const struct bcm2835_pll_data *data = pll->data;
525
526 return cprman_read(cprman, data->a2w_ctrl_reg) &
527 A2W_PLL_CTRL_PRST_DISABLE;
528}
529
530static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,
531 const struct bcm2835_pll_data *data)
532{
533
534
535
536
537
538 if (cprman->soc & SOC_BCM2711)
539 return 0;
540
541 return data->ana->fb_prediv_mask;
542}
543
544static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
545 unsigned long parent_rate,
546 u32 *ndiv, u32 *fdiv)
547{
548 u64 div;
549
550 div = (u64)rate << A2W_PLL_FRAC_BITS;
551 do_div(div, parent_rate);
552
553 *ndiv = div >> A2W_PLL_FRAC_BITS;
554 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
555}
556
557static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
558 u32 ndiv, u32 fdiv, u32 pdiv)
559{
560 u64 rate;
561
562 if (pdiv == 0)
563 return 0;
564
565 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
566 do_div(rate, pdiv);
567 return rate >> A2W_PLL_FRAC_BITS;
568}
569
570static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
571 unsigned long *parent_rate)
572{
573 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
574 const struct bcm2835_pll_data *data = pll->data;
575 u32 ndiv, fdiv;
576
577 rate = clamp(rate, data->min_rate, data->max_rate);
578
579 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
580
581 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
582}
583
584static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
585 unsigned long parent_rate)
586{
587 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
588 struct bcm2835_cprman *cprman = pll->cprman;
589 const struct bcm2835_pll_data *data = pll->data;
590 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
591 u32 ndiv, pdiv, fdiv;
592 bool using_prediv;
593
594 if (parent_rate == 0)
595 return 0;
596
597 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
598 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
599 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
600 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
601 bcm2835_pll_get_prediv_mask(cprman, data);
602
603 if (using_prediv) {
604 ndiv *= 2;
605 fdiv *= 2;
606 }
607
608 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
609}
610
611static void bcm2835_pll_off(struct clk_hw *hw)
612{
613 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
614 struct bcm2835_cprman *cprman = pll->cprman;
615 const struct bcm2835_pll_data *data = pll->data;
616
617 spin_lock(&cprman->regs_lock);
618 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
619 cprman_write(cprman, data->a2w_ctrl_reg,
620 cprman_read(cprman, data->a2w_ctrl_reg) |
621 A2W_PLL_CTRL_PWRDN);
622 spin_unlock(&cprman->regs_lock);
623}
624
625static int bcm2835_pll_on(struct clk_hw *hw)
626{
627 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
628 struct bcm2835_cprman *cprman = pll->cprman;
629 const struct bcm2835_pll_data *data = pll->data;
630 ktime_t timeout;
631
632 cprman_write(cprman, data->a2w_ctrl_reg,
633 cprman_read(cprman, data->a2w_ctrl_reg) &
634 ~A2W_PLL_CTRL_PWRDN);
635
636
637 spin_lock(&cprman->regs_lock);
638 cprman_write(cprman, data->cm_ctrl_reg,
639 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
640 spin_unlock(&cprman->regs_lock);
641
642
643 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
644 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
645 if (ktime_after(ktime_get(), timeout)) {
646 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
647 clk_hw_get_name(hw));
648 return -ETIMEDOUT;
649 }
650
651 cpu_relax();
652 }
653
654 cprman_write(cprman, data->a2w_ctrl_reg,
655 cprman_read(cprman, data->a2w_ctrl_reg) |
656 A2W_PLL_CTRL_PRST_DISABLE);
657
658 return 0;
659}
660
661static void
662bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
663{
664 int i;
665
666
667
668
669
670
671
672
673
674 for (i = 3; i >= 0; i--)
675 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
676}
677
678static int bcm2835_pll_set_rate(struct clk_hw *hw,
679 unsigned long rate, unsigned long parent_rate)
680{
681 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
682 struct bcm2835_cprman *cprman = pll->cprman;
683 const struct bcm2835_pll_data *data = pll->data;
684 u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);
685 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
686 u32 ndiv, fdiv, a2w_ctl;
687 u32 ana[4];
688 int i;
689
690 if (rate > data->max_fb_rate) {
691 use_fb_prediv = true;
692 rate /= 2;
693 } else {
694 use_fb_prediv = false;
695 }
696
697 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
698
699 for (i = 3; i >= 0; i--)
700 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
701
702 was_using_prediv = ana[1] & prediv_mask;
703
704 ana[0] &= ~data->ana->mask0;
705 ana[0] |= data->ana->set0;
706 ana[1] &= ~data->ana->mask1;
707 ana[1] |= data->ana->set1;
708 ana[3] &= ~data->ana->mask3;
709 ana[3] |= data->ana->set3;
710
711 if (was_using_prediv && !use_fb_prediv) {
712 ana[1] &= ~prediv_mask;
713 do_ana_setup_first = true;
714 } else if (!was_using_prediv && use_fb_prediv) {
715 ana[1] |= prediv_mask;
716 do_ana_setup_first = false;
717 } else {
718 do_ana_setup_first = true;
719 }
720
721
722 spin_lock(&cprman->regs_lock);
723 cprman_write(cprman, A2W_XOSC_CTRL,
724 cprman_read(cprman, A2W_XOSC_CTRL) |
725 data->reference_enable_mask);
726 spin_unlock(&cprman->regs_lock);
727
728 if (do_ana_setup_first)
729 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
730
731
732 cprman_write(cprman, data->frac_reg, fdiv);
733
734 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
735 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
736 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
737 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
738 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
739 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
740
741 if (!do_ana_setup_first)
742 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
743
744 return 0;
745}
746
747static void bcm2835_pll_debug_init(struct clk_hw *hw,
748 struct dentry *dentry)
749{
750 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
751 struct bcm2835_cprman *cprman = pll->cprman;
752 const struct bcm2835_pll_data *data = pll->data;
753 struct debugfs_reg32 *regs;
754
755 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
756 if (!regs)
757 return;
758
759 regs[0].name = "cm_ctrl";
760 regs[0].offset = data->cm_ctrl_reg;
761 regs[1].name = "a2w_ctrl";
762 regs[1].offset = data->a2w_ctrl_reg;
763 regs[2].name = "frac";
764 regs[2].offset = data->frac_reg;
765 regs[3].name = "ana0";
766 regs[3].offset = data->ana_reg_base + 0 * 4;
767 regs[4].name = "ana1";
768 regs[4].offset = data->ana_reg_base + 1 * 4;
769 regs[5].name = "ana2";
770 regs[5].offset = data->ana_reg_base + 2 * 4;
771 regs[6].name = "ana3";
772 regs[6].offset = data->ana_reg_base + 3 * 4;
773
774 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
775}
776
777static const struct clk_ops bcm2835_pll_clk_ops = {
778 .is_prepared = bcm2835_pll_is_on,
779 .prepare = bcm2835_pll_on,
780 .unprepare = bcm2835_pll_off,
781 .recalc_rate = bcm2835_pll_get_rate,
782 .set_rate = bcm2835_pll_set_rate,
783 .round_rate = bcm2835_pll_round_rate,
784 .debug_init = bcm2835_pll_debug_init,
785};
786
787struct bcm2835_pll_divider {
788 struct clk_divider div;
789 struct bcm2835_cprman *cprman;
790 const struct bcm2835_pll_divider_data *data;
791};
792
793static struct bcm2835_pll_divider *
794bcm2835_pll_divider_from_hw(struct clk_hw *hw)
795{
796 return container_of(hw, struct bcm2835_pll_divider, div.hw);
797}
798
799static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
800{
801 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
802 struct bcm2835_cprman *cprman = divider->cprman;
803 const struct bcm2835_pll_divider_data *data = divider->data;
804
805 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
806}
807
808static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,
809 struct clk_rate_request *req)
810{
811 return clk_divider_ops.determine_rate(hw, req);
812}
813
814static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
815 unsigned long parent_rate)
816{
817 return clk_divider_ops.recalc_rate(hw, parent_rate);
818}
819
820static void bcm2835_pll_divider_off(struct clk_hw *hw)
821{
822 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
823 struct bcm2835_cprman *cprman = divider->cprman;
824 const struct bcm2835_pll_divider_data *data = divider->data;
825
826 spin_lock(&cprman->regs_lock);
827 cprman_write(cprman, data->cm_reg,
828 (cprman_read(cprman, data->cm_reg) &
829 ~data->load_mask) | data->hold_mask);
830 cprman_write(cprman, data->a2w_reg,
831 cprman_read(cprman, data->a2w_reg) |
832 A2W_PLL_CHANNEL_DISABLE);
833 spin_unlock(&cprman->regs_lock);
834}
835
836static int bcm2835_pll_divider_on(struct clk_hw *hw)
837{
838 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
839 struct bcm2835_cprman *cprman = divider->cprman;
840 const struct bcm2835_pll_divider_data *data = divider->data;
841
842 spin_lock(&cprman->regs_lock);
843 cprman_write(cprman, data->a2w_reg,
844 cprman_read(cprman, data->a2w_reg) &
845 ~A2W_PLL_CHANNEL_DISABLE);
846
847 cprman_write(cprman, data->cm_reg,
848 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
849 spin_unlock(&cprman->regs_lock);
850
851 return 0;
852}
853
854static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
855 unsigned long rate,
856 unsigned long parent_rate)
857{
858 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
859 struct bcm2835_cprman *cprman = divider->cprman;
860 const struct bcm2835_pll_divider_data *data = divider->data;
861 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
862
863 div = DIV_ROUND_UP_ULL(parent_rate, rate);
864
865 div = min(div, max_div);
866 if (div == max_div)
867 div = 0;
868
869 cprman_write(cprman, data->a2w_reg, div);
870 cm = cprman_read(cprman, data->cm_reg);
871 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
872 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
873
874 return 0;
875}
876
877static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
878 struct dentry *dentry)
879{
880 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
881 struct bcm2835_cprman *cprman = divider->cprman;
882 const struct bcm2835_pll_divider_data *data = divider->data;
883 struct debugfs_reg32 *regs;
884
885 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
886 if (!regs)
887 return;
888
889 regs[0].name = "cm";
890 regs[0].offset = data->cm_reg;
891 regs[1].name = "a2w";
892 regs[1].offset = data->a2w_reg;
893
894 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
895}
896
897static const struct clk_ops bcm2835_pll_divider_clk_ops = {
898 .is_prepared = bcm2835_pll_divider_is_on,
899 .prepare = bcm2835_pll_divider_on,
900 .unprepare = bcm2835_pll_divider_off,
901 .recalc_rate = bcm2835_pll_divider_get_rate,
902 .set_rate = bcm2835_pll_divider_set_rate,
903 .determine_rate = bcm2835_pll_divider_determine_rate,
904 .debug_init = bcm2835_pll_divider_debug_init,
905};
906
907
908
909
910
911
912
913struct bcm2835_clock {
914 struct clk_hw hw;
915 struct bcm2835_cprman *cprman;
916 const struct bcm2835_clock_data *data;
917};
918
919static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
920{
921 return container_of(hw, struct bcm2835_clock, hw);
922}
923
924static int bcm2835_clock_is_on(struct clk_hw *hw)
925{
926 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
927 struct bcm2835_cprman *cprman = clock->cprman;
928 const struct bcm2835_clock_data *data = clock->data;
929
930 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
931}
932
933static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
934 unsigned long rate,
935 unsigned long parent_rate,
936 bool round_up)
937{
938 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
939 const struct bcm2835_clock_data *data = clock->data;
940 u32 unused_frac_mask =
941 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
942 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
943 u64 rem;
944 u32 div, mindiv, maxdiv;
945
946 rem = do_div(temp, rate);
947 div = temp;
948
949
950 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
951 div += unused_frac_mask + 1;
952 div &= ~unused_frac_mask;
953
954
955 if (data->is_mash_clock) {
956
957 mindiv = 2 << CM_DIV_FRAC_BITS;
958
959 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
960 } else {
961
962 mindiv = 1 << CM_DIV_FRAC_BITS;
963
964 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
965 CM_DIV_FRAC_BITS - data->frac_bits);
966 }
967
968
969 div = max_t(u32, div, mindiv);
970 div = min_t(u32, div, maxdiv);
971
972 return div;
973}
974
975static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
976 unsigned long parent_rate,
977 u32 div)
978{
979 const struct bcm2835_clock_data *data = clock->data;
980 u64 temp;
981
982 if (data->int_bits == 0 && data->frac_bits == 0)
983 return parent_rate;
984
985
986
987
988
989 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
990 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
991
992 if (div == 0)
993 return 0;
994
995 temp = (u64)parent_rate << data->frac_bits;
996
997 do_div(temp, div);
998
999 return temp;
1000}
1001
1002static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1003 unsigned long parent_rate)
1004{
1005 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1006 struct bcm2835_cprman *cprman = clock->cprman;
1007 const struct bcm2835_clock_data *data = clock->data;
1008 u32 div;
1009
1010 if (data->int_bits == 0 && data->frac_bits == 0)
1011 return parent_rate;
1012
1013 div = cprman_read(cprman, data->div_reg);
1014
1015 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1016}
1017
1018static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1019{
1020 struct bcm2835_cprman *cprman = clock->cprman;
1021 const struct bcm2835_clock_data *data = clock->data;
1022 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1023
1024 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1025 if (ktime_after(ktime_get(), timeout)) {
1026 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1027 clk_hw_get_name(&clock->hw));
1028 return;
1029 }
1030 cpu_relax();
1031 }
1032}
1033
1034static void bcm2835_clock_off(struct clk_hw *hw)
1035{
1036 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1037 struct bcm2835_cprman *cprman = clock->cprman;
1038 const struct bcm2835_clock_data *data = clock->data;
1039
1040 spin_lock(&cprman->regs_lock);
1041 cprman_write(cprman, data->ctl_reg,
1042 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1043 spin_unlock(&cprman->regs_lock);
1044
1045
1046 bcm2835_clock_wait_busy(clock);
1047}
1048
1049static int bcm2835_clock_on(struct clk_hw *hw)
1050{
1051 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1052 struct bcm2835_cprman *cprman = clock->cprman;
1053 const struct bcm2835_clock_data *data = clock->data;
1054
1055 spin_lock(&cprman->regs_lock);
1056 cprman_write(cprman, data->ctl_reg,
1057 cprman_read(cprman, data->ctl_reg) |
1058 CM_ENABLE |
1059 CM_GATE);
1060 spin_unlock(&cprman->regs_lock);
1061
1062
1063
1064
1065 if (data->tcnt_mux && false) {
1066 dev_info(cprman->dev,
1067 "clk %s: rate %ld, measure %ld\n",
1068 data->name,
1069 clk_hw_get_rate(hw),
1070 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1071 }
1072
1073 return 0;
1074}
1075
1076static int bcm2835_clock_set_rate(struct clk_hw *hw,
1077 unsigned long rate, unsigned long parent_rate)
1078{
1079 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1080 struct bcm2835_cprman *cprman = clock->cprman;
1081 const struct bcm2835_clock_data *data = clock->data;
1082 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
1083 u32 ctl;
1084
1085 spin_lock(&cprman->regs_lock);
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1096 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1097 cprman_write(cprman, data->ctl_reg, ctl);
1098
1099 cprman_write(cprman, data->div_reg, div);
1100
1101 spin_unlock(&cprman->regs_lock);
1102
1103 return 0;
1104}
1105
1106static bool
1107bcm2835_clk_is_pllc(struct clk_hw *hw)
1108{
1109 if (!hw)
1110 return false;
1111
1112 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1113}
1114
1115static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1116 int parent_idx,
1117 unsigned long rate,
1118 u32 *div,
1119 unsigned long *prate,
1120 unsigned long *avgrate)
1121{
1122 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1123 struct bcm2835_cprman *cprman = clock->cprman;
1124 const struct bcm2835_clock_data *data = clock->data;
1125 unsigned long best_rate = 0;
1126 u32 curdiv, mindiv, maxdiv;
1127 struct clk_hw *parent;
1128
1129 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1130
1131 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1132 *prate = clk_hw_get_rate(parent);
1133 *div = bcm2835_clock_choose_div(hw, rate, *prate, true);
1134
1135 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1136
1137 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1138 unsigned long high, low;
1139 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1140
1141 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1142 int_div);
1143 int_div += CM_DIV_FRAC_MASK + 1;
1144 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1145 int_div);
1146
1147
1148
1149
1150
1151 return *avgrate - max(*avgrate - low, high - *avgrate);
1152 }
1153 return *avgrate;
1154 }
1155
1156 if (data->frac_bits)
1157 dev_warn(cprman->dev,
1158 "frac bits are not used when propagating rate change");
1159
1160
1161 mindiv = data->is_mash_clock ? 2 : 1;
1162 maxdiv = BIT(data->int_bits) - 1;
1163
1164
1165 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1166 unsigned long tmp_rate;
1167
1168 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1169 tmp_rate /= curdiv;
1170 if (curdiv == mindiv ||
1171 (tmp_rate > best_rate && tmp_rate <= rate))
1172 best_rate = tmp_rate;
1173
1174 if (best_rate == rate)
1175 break;
1176 }
1177
1178 *div = curdiv << CM_DIV_FRAC_BITS;
1179 *prate = curdiv * best_rate;
1180 *avgrate = best_rate;
1181
1182 return best_rate;
1183}
1184
1185static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1186 struct clk_rate_request *req)
1187{
1188 struct clk_hw *parent, *best_parent = NULL;
1189 bool current_parent_is_pllc;
1190 unsigned long rate, best_rate = 0;
1191 unsigned long prate, best_prate = 0;
1192 unsigned long avgrate, best_avgrate = 0;
1193 size_t i;
1194 u32 div;
1195
1196 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1197
1198
1199
1200
1201 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1202 parent = clk_hw_get_parent_by_index(hw, i);
1203 if (!parent)
1204 continue;
1205
1206
1207
1208
1209
1210
1211
1212
1213 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1214 continue;
1215
1216 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1217 &div, &prate,
1218 &avgrate);
1219 if (rate > best_rate && rate <= req->rate) {
1220 best_parent = parent;
1221 best_prate = prate;
1222 best_rate = rate;
1223 best_avgrate = avgrate;
1224 }
1225 }
1226
1227 if (!best_parent)
1228 return -EINVAL;
1229
1230 req->best_parent_hw = best_parent;
1231 req->best_parent_rate = best_prate;
1232
1233 req->rate = best_avgrate;
1234
1235 return 0;
1236}
1237
1238static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1239{
1240 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1241 struct bcm2835_cprman *cprman = clock->cprman;
1242 const struct bcm2835_clock_data *data = clock->data;
1243 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1244
1245 cprman_write(cprman, data->ctl_reg, src);
1246 return 0;
1247}
1248
1249static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1250{
1251 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1252 struct bcm2835_cprman *cprman = clock->cprman;
1253 const struct bcm2835_clock_data *data = clock->data;
1254 u32 src = cprman_read(cprman, data->ctl_reg);
1255
1256 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1257}
1258
1259static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1260 {
1261 .name = "ctl",
1262 .offset = 0,
1263 },
1264 {
1265 .name = "div",
1266 .offset = 4,
1267 },
1268};
1269
1270static void bcm2835_clock_debug_init(struct clk_hw *hw,
1271 struct dentry *dentry)
1272{
1273 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1274 struct bcm2835_cprman *cprman = clock->cprman;
1275 const struct bcm2835_clock_data *data = clock->data;
1276
1277 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1278 bcm2835_debugfs_clock_reg32,
1279 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1280 dentry);
1281}
1282
1283static const struct clk_ops bcm2835_clock_clk_ops = {
1284 .is_prepared = bcm2835_clock_is_on,
1285 .prepare = bcm2835_clock_on,
1286 .unprepare = bcm2835_clock_off,
1287 .recalc_rate = bcm2835_clock_get_rate,
1288 .set_rate = bcm2835_clock_set_rate,
1289 .determine_rate = bcm2835_clock_determine_rate,
1290 .set_parent = bcm2835_clock_set_parent,
1291 .get_parent = bcm2835_clock_get_parent,
1292 .debug_init = bcm2835_clock_debug_init,
1293};
1294
1295static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1296{
1297 return true;
1298}
1299
1300
1301
1302
1303
1304static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1305 .is_prepared = bcm2835_vpu_clock_is_on,
1306 .recalc_rate = bcm2835_clock_get_rate,
1307 .set_rate = bcm2835_clock_set_rate,
1308 .determine_rate = bcm2835_clock_determine_rate,
1309 .set_parent = bcm2835_clock_set_parent,
1310 .get_parent = bcm2835_clock_get_parent,
1311 .debug_init = bcm2835_clock_debug_init,
1312};
1313
1314static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1315 const void *data)
1316{
1317 const struct bcm2835_pll_data *pll_data = data;
1318 struct bcm2835_pll *pll;
1319 struct clk_init_data init;
1320 int ret;
1321
1322 memset(&init, 0, sizeof(init));
1323
1324
1325 init.parent_names = &cprman->real_parent_names[0];
1326 init.num_parents = 1;
1327 init.name = pll_data->name;
1328 init.ops = &bcm2835_pll_clk_ops;
1329 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1330
1331 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1332 if (!pll)
1333 return NULL;
1334
1335 pll->cprman = cprman;
1336 pll->data = pll_data;
1337 pll->hw.init = &init;
1338
1339 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1340 if (ret) {
1341 kfree(pll);
1342 return NULL;
1343 }
1344 return &pll->hw;
1345}
1346
1347static struct clk_hw *
1348bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1349 const void *data)
1350{
1351 const struct bcm2835_pll_divider_data *divider_data = data;
1352 struct bcm2835_pll_divider *divider;
1353 struct clk_init_data init;
1354 const char *divider_name;
1355 int ret;
1356
1357 if (divider_data->fixed_divider != 1) {
1358 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1359 "%s_prediv", divider_data->name);
1360 if (!divider_name)
1361 return NULL;
1362 } else {
1363 divider_name = divider_data->name;
1364 }
1365
1366 memset(&init, 0, sizeof(init));
1367
1368 init.parent_names = ÷r_data->source_pll;
1369 init.num_parents = 1;
1370 init.name = divider_name;
1371 init.ops = &bcm2835_pll_divider_clk_ops;
1372 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1373
1374 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1375 if (!divider)
1376 return NULL;
1377
1378 divider->div.reg = cprman->regs + divider_data->a2w_reg;
1379 divider->div.shift = A2W_PLL_DIV_SHIFT;
1380 divider->div.width = A2W_PLL_DIV_BITS;
1381 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1382 divider->div.lock = &cprman->regs_lock;
1383 divider->div.hw.init = &init;
1384 divider->div.table = NULL;
1385
1386 divider->cprman = cprman;
1387 divider->data = divider_data;
1388
1389 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
1390 if (ret)
1391 return ERR_PTR(ret);
1392
1393
1394
1395
1396
1397 if (divider_data->fixed_divider != 1) {
1398 return clk_hw_register_fixed_factor(cprman->dev,
1399 divider_data->name,
1400 divider_name,
1401 CLK_SET_RATE_PARENT,
1402 1,
1403 divider_data->fixed_divider);
1404 }
1405
1406 return ÷r->div.hw;
1407}
1408
1409static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1410 const void *data)
1411{
1412 const struct bcm2835_clock_data *clock_data = data;
1413 struct bcm2835_clock *clock;
1414 struct clk_init_data init;
1415 const char *parents[1 << CM_SRC_BITS];
1416 size_t i;
1417 int ret;
1418
1419
1420
1421
1422
1423 for (i = 0; i < clock_data->num_mux_parents; i++) {
1424 parents[i] = clock_data->parents[i];
1425
1426 ret = match_string(cprman_parent_names,
1427 ARRAY_SIZE(cprman_parent_names),
1428 parents[i]);
1429 if (ret >= 0)
1430 parents[i] = cprman->real_parent_names[ret];
1431 }
1432
1433 memset(&init, 0, sizeof(init));
1434 init.parent_names = parents;
1435 init.num_parents = clock_data->num_mux_parents;
1436 init.name = clock_data->name;
1437 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1438
1439
1440
1441
1442
1443 if (clock_data->set_rate_parent)
1444 init.flags |= CLK_SET_RATE_PARENT;
1445
1446 if (clock_data->is_vpu_clock) {
1447 init.ops = &bcm2835_vpu_clock_clk_ops;
1448 } else {
1449 init.ops = &bcm2835_clock_clk_ops;
1450 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1451
1452
1453
1454
1455 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
1456 init.flags &= ~CLK_IS_CRITICAL;
1457 }
1458
1459 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1460 if (!clock)
1461 return NULL;
1462
1463 clock->cprman = cprman;
1464 clock->data = clock_data;
1465 clock->hw.init = &init;
1466
1467 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1468 if (ret)
1469 return ERR_PTR(ret);
1470 return &clock->hw;
1471}
1472
1473static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1474 const void *data)
1475{
1476 const struct bcm2835_gate_data *gate_data = data;
1477
1478 return clk_hw_register_gate(cprman->dev, gate_data->name,
1479 gate_data->parent,
1480 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1481 cprman->regs + gate_data->ctl_reg,
1482 CM_GATE_BIT, 0, &cprman->regs_lock);
1483}
1484
1485struct bcm2835_clk_desc {
1486 struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
1487 const void *data);
1488 unsigned int supported;
1489 const void *data;
1490};
1491
1492
1493#define _REGISTER(f, s, ...) { .clk_register = f, \
1494 .supported = s, \
1495 .data = __VA_ARGS__ }
1496#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
1497 s, \
1498 &(struct bcm2835_pll_data) \
1499 {__VA_ARGS__})
1500#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1501 s, \
1502 &(struct bcm2835_pll_divider_data) \
1503 {__VA_ARGS__})
1504#define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
1505 s, \
1506 &(struct bcm2835_clock_data) \
1507 {__VA_ARGS__})
1508#define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
1509 s, \
1510 &(struct bcm2835_gate_data) \
1511 {__VA_ARGS__})
1512
1513
1514
1515
1516static const char *const bcm2835_clock_osc_parents[] = {
1517 "gnd",
1518 "xosc",
1519 "testdebug0",
1520 "testdebug1"
1521};
1522
1523#define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
1524 s, \
1525 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1526 .parents = bcm2835_clock_osc_parents, \
1527 __VA_ARGS__)
1528
1529
1530static const char *const bcm2835_clock_per_parents[] = {
1531 "gnd",
1532 "xosc",
1533 "testdebug0",
1534 "testdebug1",
1535 "plla_per",
1536 "pllc_per",
1537 "plld_per",
1538 "pllh_aux",
1539};
1540
1541#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
1542 s, \
1543 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1544 .parents = bcm2835_clock_per_parents, \
1545 __VA_ARGS__)
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556static const char *const bcm2835_pcm_per_parents[] = {
1557 "-",
1558 "xosc",
1559 "-",
1560 "-",
1561 "-",
1562 "-",
1563 "plld_per",
1564 "-",
1565};
1566
1567#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
1568 s, \
1569 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1570 .parents = bcm2835_pcm_per_parents, \
1571 __VA_ARGS__)
1572
1573
1574static const char *const bcm2835_clock_vpu_parents[] = {
1575 "gnd",
1576 "xosc",
1577 "testdebug0",
1578 "testdebug1",
1579 "plla_core",
1580 "pllc_core0",
1581 "plld_core",
1582 "pllh_aux",
1583 "pllc_core1",
1584 "pllc_core2",
1585};
1586
1587#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
1588 s, \
1589 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1590 .parents = bcm2835_clock_vpu_parents, \
1591 __VA_ARGS__)
1592
1593
1594
1595
1596
1597
1598static const char *const bcm2835_clock_dsi0_parents[] = {
1599 "gnd",
1600 "xosc",
1601 "testdebug0",
1602 "testdebug1",
1603 "dsi0_ddr",
1604 "dsi0_ddr_inv",
1605 "dsi0_ddr2",
1606 "dsi0_ddr2_inv",
1607 "dsi0_byte",
1608 "dsi0_byte_inv",
1609};
1610
1611static const char *const bcm2835_clock_dsi1_parents[] = {
1612 "gnd",
1613 "xosc",
1614 "testdebug0",
1615 "testdebug1",
1616 "dsi1_ddr",
1617 "dsi1_ddr_inv",
1618 "dsi1_ddr2",
1619 "dsi1_ddr2_inv",
1620 "dsi1_byte",
1621 "dsi1_byte_inv",
1622};
1623
1624#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
1625 s, \
1626 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1627 .parents = bcm2835_clock_dsi0_parents, \
1628 __VA_ARGS__)
1629
1630#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
1631 s, \
1632 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1633 .parents = bcm2835_clock_dsi1_parents, \
1634 __VA_ARGS__)
1635
1636
1637
1638
1639
1640static const struct bcm2835_clk_desc clk_desc_array[] = {
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650 [BCM2835_PLLA] = REGISTER_PLL(
1651 SOC_ALL,
1652 .name = "plla",
1653 .cm_ctrl_reg = CM_PLLA,
1654 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1655 .frac_reg = A2W_PLLA_FRAC,
1656 .ana_reg_base = A2W_PLLA_ANA0,
1657 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1658 .lock_mask = CM_LOCK_FLOCKA,
1659
1660 .ana = &bcm2835_ana_default,
1661
1662 .min_rate = 600000000u,
1663 .max_rate = 2400000000u,
1664 .max_fb_rate = BCM2835_MAX_FB_RATE),
1665 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1666 SOC_ALL,
1667 .name = "plla_core",
1668 .source_pll = "plla",
1669 .cm_reg = CM_PLLA,
1670 .a2w_reg = A2W_PLLA_CORE,
1671 .load_mask = CM_PLLA_LOADCORE,
1672 .hold_mask = CM_PLLA_HOLDCORE,
1673 .fixed_divider = 1,
1674 .flags = CLK_SET_RATE_PARENT),
1675 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1676 SOC_ALL,
1677 .name = "plla_per",
1678 .source_pll = "plla",
1679 .cm_reg = CM_PLLA,
1680 .a2w_reg = A2W_PLLA_PER,
1681 .load_mask = CM_PLLA_LOADPER,
1682 .hold_mask = CM_PLLA_HOLDPER,
1683 .fixed_divider = 1,
1684 .flags = CLK_SET_RATE_PARENT),
1685 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1686 SOC_ALL,
1687 .name = "plla_dsi0",
1688 .source_pll = "plla",
1689 .cm_reg = CM_PLLA,
1690 .a2w_reg = A2W_PLLA_DSI0,
1691 .load_mask = CM_PLLA_LOADDSI0,
1692 .hold_mask = CM_PLLA_HOLDDSI0,
1693 .fixed_divider = 1),
1694 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1695 SOC_ALL,
1696 .name = "plla_ccp2",
1697 .source_pll = "plla",
1698 .cm_reg = CM_PLLA,
1699 .a2w_reg = A2W_PLLA_CCP2,
1700 .load_mask = CM_PLLA_LOADCCP2,
1701 .hold_mask = CM_PLLA_HOLDCCP2,
1702 .fixed_divider = 1,
1703 .flags = CLK_SET_RATE_PARENT),
1704
1705
1706 [BCM2835_PLLB] = REGISTER_PLL(
1707 SOC_ALL,
1708 .name = "pllb",
1709 .cm_ctrl_reg = CM_PLLB,
1710 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1711 .frac_reg = A2W_PLLB_FRAC,
1712 .ana_reg_base = A2W_PLLB_ANA0,
1713 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1714 .lock_mask = CM_LOCK_FLOCKB,
1715
1716 .ana = &bcm2835_ana_default,
1717
1718 .min_rate = 600000000u,
1719 .max_rate = 3000000000u,
1720 .max_fb_rate = BCM2835_MAX_FB_RATE,
1721 .flags = CLK_GET_RATE_NOCACHE),
1722 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1723 SOC_ALL,
1724 .name = "pllb_arm",
1725 .source_pll = "pllb",
1726 .cm_reg = CM_PLLB,
1727 .a2w_reg = A2W_PLLB_ARM,
1728 .load_mask = CM_PLLB_LOADARM,
1729 .hold_mask = CM_PLLB_HOLDARM,
1730 .fixed_divider = 1,
1731 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
1732
1733
1734
1735
1736
1737
1738
1739 [BCM2835_PLLC] = REGISTER_PLL(
1740 SOC_ALL,
1741 .name = "pllc",
1742 .cm_ctrl_reg = CM_PLLC,
1743 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1744 .frac_reg = A2W_PLLC_FRAC,
1745 .ana_reg_base = A2W_PLLC_ANA0,
1746 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1747 .lock_mask = CM_LOCK_FLOCKC,
1748
1749 .ana = &bcm2835_ana_default,
1750
1751 .min_rate = 600000000u,
1752 .max_rate = 3000000000u,
1753 .max_fb_rate = BCM2835_MAX_FB_RATE),
1754 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1755 SOC_ALL,
1756 .name = "pllc_core0",
1757 .source_pll = "pllc",
1758 .cm_reg = CM_PLLC,
1759 .a2w_reg = A2W_PLLC_CORE0,
1760 .load_mask = CM_PLLC_LOADCORE0,
1761 .hold_mask = CM_PLLC_HOLDCORE0,
1762 .fixed_divider = 1,
1763 .flags = CLK_SET_RATE_PARENT),
1764 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1765 SOC_ALL,
1766 .name = "pllc_core1",
1767 .source_pll = "pllc",
1768 .cm_reg = CM_PLLC,
1769 .a2w_reg = A2W_PLLC_CORE1,
1770 .load_mask = CM_PLLC_LOADCORE1,
1771 .hold_mask = CM_PLLC_HOLDCORE1,
1772 .fixed_divider = 1,
1773 .flags = CLK_SET_RATE_PARENT),
1774 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1775 SOC_ALL,
1776 .name = "pllc_core2",
1777 .source_pll = "pllc",
1778 .cm_reg = CM_PLLC,
1779 .a2w_reg = A2W_PLLC_CORE2,
1780 .load_mask = CM_PLLC_LOADCORE2,
1781 .hold_mask = CM_PLLC_HOLDCORE2,
1782 .fixed_divider = 1,
1783 .flags = CLK_SET_RATE_PARENT),
1784 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1785 SOC_ALL,
1786 .name = "pllc_per",
1787 .source_pll = "pllc",
1788 .cm_reg = CM_PLLC,
1789 .a2w_reg = A2W_PLLC_PER,
1790 .load_mask = CM_PLLC_LOADPER,
1791 .hold_mask = CM_PLLC_HOLDPER,
1792 .fixed_divider = 1,
1793 .flags = CLK_SET_RATE_PARENT),
1794
1795
1796
1797
1798
1799
1800
1801 [BCM2835_PLLD] = REGISTER_PLL(
1802 SOC_ALL,
1803 .name = "plld",
1804 .cm_ctrl_reg = CM_PLLD,
1805 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1806 .frac_reg = A2W_PLLD_FRAC,
1807 .ana_reg_base = A2W_PLLD_ANA0,
1808 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1809 .lock_mask = CM_LOCK_FLOCKD,
1810
1811 .ana = &bcm2835_ana_default,
1812
1813 .min_rate = 600000000u,
1814 .max_rate = 2400000000u,
1815 .max_fb_rate = BCM2835_MAX_FB_RATE),
1816 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1817 SOC_ALL,
1818 .name = "plld_core",
1819 .source_pll = "plld",
1820 .cm_reg = CM_PLLD,
1821 .a2w_reg = A2W_PLLD_CORE,
1822 .load_mask = CM_PLLD_LOADCORE,
1823 .hold_mask = CM_PLLD_HOLDCORE,
1824 .fixed_divider = 1,
1825 .flags = CLK_SET_RATE_PARENT),
1826
1827
1828
1829
1830
1831 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1832 SOC_ALL,
1833 .name = "plld_per",
1834 .source_pll = "plld",
1835 .cm_reg = CM_PLLD,
1836 .a2w_reg = A2W_PLLD_PER,
1837 .load_mask = CM_PLLD_LOADPER,
1838 .hold_mask = CM_PLLD_HOLDPER,
1839 .fixed_divider = 1,
1840 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1841 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1842 SOC_ALL,
1843 .name = "plld_dsi0",
1844 .source_pll = "plld",
1845 .cm_reg = CM_PLLD,
1846 .a2w_reg = A2W_PLLD_DSI0,
1847 .load_mask = CM_PLLD_LOADDSI0,
1848 .hold_mask = CM_PLLD_HOLDDSI0,
1849 .fixed_divider = 1),
1850 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1851 SOC_ALL,
1852 .name = "plld_dsi1",
1853 .source_pll = "plld",
1854 .cm_reg = CM_PLLD,
1855 .a2w_reg = A2W_PLLD_DSI1,
1856 .load_mask = CM_PLLD_LOADDSI1,
1857 .hold_mask = CM_PLLD_HOLDDSI1,
1858 .fixed_divider = 1),
1859
1860
1861
1862
1863
1864
1865
1866 [BCM2835_PLLH] = REGISTER_PLL(
1867 SOC_BCM2835,
1868 "pllh",
1869 .cm_ctrl_reg = CM_PLLH,
1870 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1871 .frac_reg = A2W_PLLH_FRAC,
1872 .ana_reg_base = A2W_PLLH_ANA0,
1873 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1874 .lock_mask = CM_LOCK_FLOCKH,
1875
1876 .ana = &bcm2835_ana_pllh,
1877
1878 .min_rate = 600000000u,
1879 .max_rate = 3000000000u,
1880 .max_fb_rate = BCM2835_MAX_FB_RATE),
1881 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1882 SOC_BCM2835,
1883 .name = "pllh_rcal",
1884 .source_pll = "pllh",
1885 .cm_reg = CM_PLLH,
1886 .a2w_reg = A2W_PLLH_RCAL,
1887 .load_mask = CM_PLLH_LOADRCAL,
1888 .hold_mask = 0,
1889 .fixed_divider = 10,
1890 .flags = CLK_SET_RATE_PARENT),
1891 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1892 SOC_BCM2835,
1893 .name = "pllh_aux",
1894 .source_pll = "pllh",
1895 .cm_reg = CM_PLLH,
1896 .a2w_reg = A2W_PLLH_AUX,
1897 .load_mask = CM_PLLH_LOADAUX,
1898 .hold_mask = 0,
1899 .fixed_divider = 1,
1900 .flags = CLK_SET_RATE_PARENT),
1901 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1902 SOC_BCM2835,
1903 .name = "pllh_pix",
1904 .source_pll = "pllh",
1905 .cm_reg = CM_PLLH,
1906 .a2w_reg = A2W_PLLH_PIX,
1907 .load_mask = CM_PLLH_LOADPIX,
1908 .hold_mask = 0,
1909 .fixed_divider = 10,
1910 .flags = CLK_SET_RATE_PARENT),
1911
1912
1913
1914
1915
1916
1917 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1918 SOC_ALL,
1919 .name = "otp",
1920 .ctl_reg = CM_OTPCTL,
1921 .div_reg = CM_OTPDIV,
1922 .int_bits = 4,
1923 .frac_bits = 0,
1924 .tcnt_mux = 6),
1925
1926
1927
1928
1929 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1930 SOC_ALL,
1931 .name = "timer",
1932 .ctl_reg = CM_TIMERCTL,
1933 .div_reg = CM_TIMERDIV,
1934 .int_bits = 6,
1935 .frac_bits = 12),
1936
1937
1938
1939
1940 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1941 SOC_ALL,
1942 .name = "tsens",
1943 .ctl_reg = CM_TSENSCTL,
1944 .div_reg = CM_TSENSDIV,
1945 .int_bits = 5,
1946 .frac_bits = 0),
1947 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1948 SOC_ALL,
1949 .name = "tec",
1950 .ctl_reg = CM_TECCTL,
1951 .div_reg = CM_TECDIV,
1952 .int_bits = 6,
1953 .frac_bits = 0),
1954
1955
1956 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1957 SOC_ALL,
1958 .name = "h264",
1959 .ctl_reg = CM_H264CTL,
1960 .div_reg = CM_H264DIV,
1961 .int_bits = 4,
1962 .frac_bits = 8,
1963 .tcnt_mux = 1),
1964 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1965 SOC_ALL,
1966 .name = "isp",
1967 .ctl_reg = CM_ISPCTL,
1968 .div_reg = CM_ISPDIV,
1969 .int_bits = 4,
1970 .frac_bits = 8,
1971 .tcnt_mux = 2),
1972
1973
1974
1975
1976
1977 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1978 SOC_ALL,
1979 .name = "sdram",
1980 .ctl_reg = CM_SDCCTL,
1981 .div_reg = CM_SDCDIV,
1982 .int_bits = 6,
1983 .frac_bits = 0,
1984 .tcnt_mux = 3),
1985 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1986 SOC_ALL,
1987 .name = "v3d",
1988 .ctl_reg = CM_V3DCTL,
1989 .div_reg = CM_V3DDIV,
1990 .int_bits = 4,
1991 .frac_bits = 8,
1992 .tcnt_mux = 4),
1993
1994
1995
1996
1997
1998
1999 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
2000 SOC_ALL,
2001 .name = "vpu",
2002 .ctl_reg = CM_VPUCTL,
2003 .div_reg = CM_VPUDIV,
2004 .int_bits = 12,
2005 .frac_bits = 8,
2006 .flags = CLK_IS_CRITICAL,
2007 .is_vpu_clock = true,
2008 .tcnt_mux = 5),
2009
2010
2011 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
2012 SOC_ALL,
2013 .name = "aveo",
2014 .ctl_reg = CM_AVEOCTL,
2015 .div_reg = CM_AVEODIV,
2016 .int_bits = 4,
2017 .frac_bits = 0,
2018 .tcnt_mux = 38),
2019 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
2020 SOC_ALL,
2021 .name = "cam0",
2022 .ctl_reg = CM_CAM0CTL,
2023 .div_reg = CM_CAM0DIV,
2024 .int_bits = 4,
2025 .frac_bits = 8,
2026 .tcnt_mux = 14),
2027 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
2028 SOC_ALL,
2029 .name = "cam1",
2030 .ctl_reg = CM_CAM1CTL,
2031 .div_reg = CM_CAM1DIV,
2032 .int_bits = 4,
2033 .frac_bits = 8,
2034 .tcnt_mux = 15),
2035 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
2036 SOC_ALL,
2037 .name = "dft",
2038 .ctl_reg = CM_DFTCTL,
2039 .div_reg = CM_DFTDIV,
2040 .int_bits = 5,
2041 .frac_bits = 0),
2042 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
2043 SOC_ALL,
2044 .name = "dpi",
2045 .ctl_reg = CM_DPICTL,
2046 .div_reg = CM_DPIDIV,
2047 .int_bits = 4,
2048 .frac_bits = 8,
2049 .tcnt_mux = 17),
2050
2051
2052 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2053 SOC_ALL,
2054 .name = "emmc",
2055 .ctl_reg = CM_EMMCCTL,
2056 .div_reg = CM_EMMCDIV,
2057 .int_bits = 4,
2058 .frac_bits = 8,
2059 .tcnt_mux = 39),
2060
2061
2062 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
2063 SOC_BCM2711,
2064 .name = "emmc2",
2065 .ctl_reg = CM_EMMC2CTL,
2066 .div_reg = CM_EMMC2DIV,
2067 .int_bits = 4,
2068 .frac_bits = 8,
2069 .tcnt_mux = 42),
2070
2071
2072 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2073 SOC_ALL,
2074 .name = "gp0",
2075 .ctl_reg = CM_GP0CTL,
2076 .div_reg = CM_GP0DIV,
2077 .int_bits = 12,
2078 .frac_bits = 12,
2079 .is_mash_clock = true,
2080 .tcnt_mux = 20),
2081 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2082 SOC_ALL,
2083 .name = "gp1",
2084 .ctl_reg = CM_GP1CTL,
2085 .div_reg = CM_GP1DIV,
2086 .int_bits = 12,
2087 .frac_bits = 12,
2088 .flags = CLK_IS_CRITICAL,
2089 .is_mash_clock = true,
2090 .tcnt_mux = 21),
2091 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2092 SOC_ALL,
2093 .name = "gp2",
2094 .ctl_reg = CM_GP2CTL,
2095 .div_reg = CM_GP2DIV,
2096 .int_bits = 12,
2097 .frac_bits = 12,
2098 .flags = CLK_IS_CRITICAL),
2099
2100
2101 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2102 SOC_ALL,
2103 .name = "hsm",
2104 .ctl_reg = CM_HSMCTL,
2105 .div_reg = CM_HSMDIV,
2106 .int_bits = 4,
2107 .frac_bits = 8,
2108 .tcnt_mux = 22),
2109 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2110 SOC_ALL,
2111 .name = "pcm",
2112 .ctl_reg = CM_PCMCTL,
2113 .div_reg = CM_PCMDIV,
2114 .int_bits = 12,
2115 .frac_bits = 12,
2116 .is_mash_clock = true,
2117 .low_jitter = true,
2118 .tcnt_mux = 23),
2119 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2120 SOC_ALL,
2121 .name = "pwm",
2122 .ctl_reg = CM_PWMCTL,
2123 .div_reg = CM_PWMDIV,
2124 .int_bits = 12,
2125 .frac_bits = 12,
2126 .is_mash_clock = true,
2127 .tcnt_mux = 24),
2128 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2129 SOC_ALL,
2130 .name = "slim",
2131 .ctl_reg = CM_SLIMCTL,
2132 .div_reg = CM_SLIMDIV,
2133 .int_bits = 12,
2134 .frac_bits = 12,
2135 .is_mash_clock = true,
2136 .tcnt_mux = 25),
2137 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2138 SOC_ALL,
2139 .name = "smi",
2140 .ctl_reg = CM_SMICTL,
2141 .div_reg = CM_SMIDIV,
2142 .int_bits = 4,
2143 .frac_bits = 8,
2144 .tcnt_mux = 27),
2145 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2146 SOC_ALL,
2147 .name = "uart",
2148 .ctl_reg = CM_UARTCTL,
2149 .div_reg = CM_UARTDIV,
2150 .int_bits = 10,
2151 .frac_bits = 12,
2152 .tcnt_mux = 28),
2153
2154
2155 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2156 SOC_ALL,
2157 .name = "vec",
2158 .ctl_reg = CM_VECCTL,
2159 .div_reg = CM_VECDIV,
2160 .int_bits = 4,
2161 .frac_bits = 0,
2162
2163
2164
2165
2166 .set_rate_parent = BIT(7),
2167 .tcnt_mux = 29),
2168
2169
2170 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2171 SOC_ALL,
2172 .name = "dsi0e",
2173 .ctl_reg = CM_DSI0ECTL,
2174 .div_reg = CM_DSI0EDIV,
2175 .int_bits = 4,
2176 .frac_bits = 8,
2177 .tcnt_mux = 18),
2178 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2179 SOC_ALL,
2180 .name = "dsi1e",
2181 .ctl_reg = CM_DSI1ECTL,
2182 .div_reg = CM_DSI1EDIV,
2183 .int_bits = 4,
2184 .frac_bits = 8,
2185 .tcnt_mux = 19),
2186 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2187 SOC_ALL,
2188 .name = "dsi0p",
2189 .ctl_reg = CM_DSI0PCTL,
2190 .div_reg = CM_DSI0PDIV,
2191 .int_bits = 0,
2192 .frac_bits = 0,
2193 .tcnt_mux = 12),
2194 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2195 SOC_ALL,
2196 .name = "dsi1p",
2197 .ctl_reg = CM_DSI1PCTL,
2198 .div_reg = CM_DSI1PDIV,
2199 .int_bits = 0,
2200 .frac_bits = 0,
2201 .tcnt_mux = 13),
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2212 SOC_ALL,
2213 .name = "peri_image",
2214 .parent = "vpu",
2215 .ctl_reg = CM_PERIICTL),
2216};
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2228{
2229 struct clk *parent = clk_get_parent(sdc);
2230
2231 if (IS_ERR(parent))
2232 return PTR_ERR(parent);
2233
2234 return clk_prepare_enable(parent);
2235}
2236
2237static int bcm2835_clk_probe(struct platform_device *pdev)
2238{
2239 struct device *dev = &pdev->dev;
2240 struct clk_hw **hws;
2241 struct bcm2835_cprman *cprman;
2242 const struct bcm2835_clk_desc *desc;
2243 const size_t asize = ARRAY_SIZE(clk_desc_array);
2244 const struct cprman_plat_data *pdata;
2245 size_t i;
2246 int ret;
2247
2248 pdata = of_device_get_match_data(&pdev->dev);
2249 if (!pdata)
2250 return -ENODEV;
2251
2252 cprman = devm_kzalloc(dev,
2253 struct_size(cprman, onecell.hws, asize),
2254 GFP_KERNEL);
2255 if (!cprman)
2256 return -ENOMEM;
2257
2258 spin_lock_init(&cprman->regs_lock);
2259 cprman->dev = dev;
2260 cprman->regs = devm_platform_ioremap_resource(pdev, 0);
2261 if (IS_ERR(cprman->regs))
2262 return PTR_ERR(cprman->regs);
2263
2264 memcpy(cprman->real_parent_names, cprman_parent_names,
2265 sizeof(cprman_parent_names));
2266 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2267 ARRAY_SIZE(cprman_parent_names));
2268
2269
2270
2271
2272
2273
2274
2275
2276 if (!cprman->real_parent_names[0])
2277 return -ENODEV;
2278
2279 platform_set_drvdata(pdev, cprman);
2280
2281 cprman->onecell.num = asize;
2282 cprman->soc = pdata->soc;
2283 hws = cprman->onecell.hws;
2284
2285 for (i = 0; i < asize; i++) {
2286 desc = &clk_desc_array[i];
2287 if (desc->clk_register && desc->data &&
2288 (desc->supported & pdata->soc)) {
2289 hws[i] = desc->clk_register(cprman, desc->data);
2290 }
2291 }
2292
2293 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2294 if (ret)
2295 return ret;
2296
2297 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2298 &cprman->onecell);
2299}
2300
2301static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2302 .soc = SOC_BCM2835,
2303};
2304
2305static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2306 .soc = SOC_BCM2711,
2307};
2308
2309static const struct of_device_id bcm2835_clk_of_match[] = {
2310 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2311 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2312 {}
2313};
2314MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2315
2316static struct platform_driver bcm2835_clk_driver = {
2317 .driver = {
2318 .name = "bcm2835-clk",
2319 .of_match_table = bcm2835_clk_of_match,
2320 },
2321 .probe = bcm2835_clk_probe,
2322};
2323
2324builtin_platform_driver(bcm2835_clk_driver);
2325
2326MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2327MODULE_DESCRIPTION("BCM2835 clock driver");
2328MODULE_LICENSE("GPL");
2329