LXR linux/drivers/clk/davinci/pll-dm646x.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * PLL clock descriptions for TI DM646X
   4 *
   5 * Copyright (C) 2018 David Lechner <david@lechnology.com>
   6 */
   7
   8#include <linux/clk-provider.h>
   9#include <linux/clk/davinci.h>
  10#include <linux/clkdev.h>
  11#include <linux/init.h>
  12#include <linux/types.h>
  13
  14#include "pll.h"
  15
  16static const struct davinci_pll_clk_info dm646x_pll1_info = {
  17        .name = "pll1",
  18        .pllm_mask = GENMASK(4, 0),
  19        .pllm_min = 14,
  20        .pllm_max = 32,
  21        .flags = PLL_HAS_CLKMODE,
  22};
  23
  24SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
  25SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
  26SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
  27SYSCLK(4, pll1_sysclk4, pll1_pllen, 4, 0);
  28SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, 0);
  29SYSCLK(6, pll1_sysclk6, pll1_pllen, 4, 0);
  30SYSCLK(8, pll1_sysclk8, pll1_pllen, 4, 0);
  31SYSCLK(9, pll1_sysclk9, pll1_pllen, 4, 0);
  32
  33int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  34{
  35        struct clk *clk;
  36
  37        davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base, cfgchip);
  38
  39        clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
  40        clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc");
  41
  42        clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
  43        clk_register_clkdev(clk, "pll1_sysclk2", "dm646x-psc");
  44
  45        clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
  46        clk_register_clkdev(clk, "pll1_sysclk3", "dm646x-psc");
  47        clk_register_clkdev(clk, NULL, "davinci-wdt");
  48
  49        clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
  50        clk_register_clkdev(clk, "pll1_sysclk4", "dm646x-psc");
  51
  52        clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
  53        clk_register_clkdev(clk, "pll1_sysclk5", "dm646x-psc");
  54
  55        davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
  56
  57        davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
  58
  59        davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
  60
  61        davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
  62
  63        davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
  64
  65        return 0;
  66}
  67
  68static const struct davinci_pll_clk_info dm646x_pll2_info = {
  69        .name = "pll2",
  70        .pllm_mask = GENMASK(4, 0),
  71        .pllm_min = 14,
  72        .pllm_max = 32,
  73        .flags = 0,
  74};
  75
  76SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
  77
  78int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  79{
  80        davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base, cfgchip);
  81
  82        davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
  83
  84        return 0;
  85}
  86