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7#include <linux/clk-provider.h>
8#include <linux/of.h>
9#include <linux/of_address.h>
10#include <linux/slab.h>
11#include <linux/mfd/syscon.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14
15#include "clk-mtk.h"
16#include "clk-gate.h"
17#include "clk-mux.h"
18
19#include <dt-bindings/clock/mt6765-clk.h>
20
21
22#define _DIV4_ 1
23
24static DEFINE_SPINLOCK(mt6765_clk_lock);
25
26
27static void __iomem *cksys_base;
28static void __iomem *apmixed_base;
29
30
31#define CLK_SCP_CFG_0 (cksys_base + 0x200)
32#define CLK_SCP_CFG_1 (cksys_base + 0x204)
33
34
35#define AP_PLL_CON3 (apmixed_base + 0x0C)
36#define PLLON_CON0 (apmixed_base + 0x44)
37#define PLLON_CON1 (apmixed_base + 0x48)
38
39
40#define CLK_CFG_0 0x40
41#define CLK_CFG_0_SET 0x44
42#define CLK_CFG_0_CLR 0x48
43#define CLK_CFG_1 0x50
44#define CLK_CFG_1_SET 0x54
45#define CLK_CFG_1_CLR 0x58
46#define CLK_CFG_2 0x60
47#define CLK_CFG_2_SET 0x64
48#define CLK_CFG_2_CLR 0x68
49#define CLK_CFG_3 0x70
50#define CLK_CFG_3_SET 0x74
51#define CLK_CFG_3_CLR 0x78
52#define CLK_CFG_4 0x80
53#define CLK_CFG_4_SET 0x84
54#define CLK_CFG_4_CLR 0x88
55#define CLK_CFG_5 0x90
56#define CLK_CFG_5_SET 0x94
57#define CLK_CFG_5_CLR 0x98
58#define CLK_CFG_6 0xa0
59#define CLK_CFG_6_SET 0xa4
60#define CLK_CFG_6_CLR 0xa8
61#define CLK_CFG_7 0xb0
62#define CLK_CFG_7_SET 0xb4
63#define CLK_CFG_7_CLR 0xb8
64#define CLK_CFG_8 0xc0
65#define CLK_CFG_8_SET 0xc4
66#define CLK_CFG_8_CLR 0xc8
67#define CLK_CFG_9 0xd0
68#define CLK_CFG_9_SET 0xd4
69#define CLK_CFG_9_CLR 0xd8
70#define CLK_CFG_10 0xe0
71#define CLK_CFG_10_SET 0xe4
72#define CLK_CFG_10_CLR 0xe8
73#define CLK_CFG_UPDATE 0x004
74
75static const struct mtk_fixed_clk fixed_clks[] = {
76 FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768),
77 FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000),
78 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000),
79};
80
81static const struct mtk_fixed_factor top_divs[] = {
82 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
83 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
84 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
85 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
86 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
87 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
88 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
89 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
90 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
91 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
92 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
93 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
94 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
95 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
96 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
97 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
98 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
99 FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13),
100 FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
101 FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
102 FACTOR(CLK_TOP_USB20_192M_D16,
103 "usb20_192m_d16", "usb20_192m_ck", 1, 16),
104 FACTOR(CLK_TOP_USB20_192M_D32,
105 "usb20_192m_d32", "usb20_192m_ck", 1, 32),
106 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
107 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
108 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
109 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
110 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
111 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
112 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
113 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
114 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
115 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
116 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
117 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
118 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2),
119 FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1),
120 FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2),
121 FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4),
122 FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
123 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
124 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
125 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
126 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
127 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
128 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
129 FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1),
130 FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2),
131 FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4),
132 FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8),
133 FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16),
134 FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32),
135 FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1),
136 FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1),
137 FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1),
138 FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1),
139 FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1),
140 FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
141 FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1),
142 FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
143 FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1),
144 FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1),
145 FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),
146 FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1),
147 FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1),
148 FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1),
149 FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1),
150 FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1),
151 FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1),
152 FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1),
153 FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1),
154 FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1),
155 FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1),
156 FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1),
157 FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1),
158 FACTOR(CLK_TOP_DA_USB20_48M_DIV,
159 "usb20_48m_div", "usb20_192m_d4", 1, 1),
160 FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1),
161};
162
163static const char * const axi_parents[] = {
164 "clk26m",
165 "syspll_d7",
166 "syspll1_d4",
167 "syspll3_d2"
168};
169
170static const char * const mem_parents[] = {
171 "clk26m",
172 "dmpll_ck",
173 "apll1_ck"
174};
175
176static const char * const mm_parents[] = {
177 "clk26m",
178 "mmpll_ck",
179 "syspll1_d2",
180 "syspll_d5",
181 "syspll1_d4",
182 "univpll_d5",
183 "univpll1_d2",
184 "mmpll_d2"
185};
186
187static const char * const scp_parents[] = {
188 "clk26m",
189 "syspll4_d2",
190 "univpll2_d2",
191 "syspll1_d2",
192 "univpll1_d2",
193 "syspll_d3",
194 "univpll_d3"
195};
196
197static const char * const mfg_parents[] = {
198 "clk26m",
199 "mfgpll_ck",
200 "syspll_d3",
201 "univpll_d3"
202};
203
204static const char * const atb_parents[] = {
205 "clk26m",
206 "syspll1_d4",
207 "syspll1_d2"
208};
209
210static const char * const camtg_parents[] = {
211 "clk26m",
212 "usb20_192m_d8",
213 "univpll2_d8",
214 "usb20_192m_d4",
215 "univpll2_d32",
216 "usb20_192m_d16",
217 "usb20_192m_d32"
218};
219
220static const char * const uart_parents[] = {
221 "clk26m",
222 "univpll2_d8"
223};
224
225static const char * const spi_parents[] = {
226 "clk26m",
227 "syspll3_d2",
228 "syspll4_d2",
229 "syspll2_d4"
230};
231
232static const char * const msdc5hclk_parents[] = {
233 "clk26m",
234 "syspll1_d2",
235 "univpll1_d4",
236 "syspll2_d2"
237};
238
239static const char * const msdc50_0_parents[] = {
240 "clk26m",
241 "msdcpll_ck",
242 "syspll2_d2",
243 "syspll4_d2",
244 "univpll1_d2",
245 "syspll1_d2",
246 "univpll_d5",
247 "univpll1_d4"
248};
249
250static const char * const msdc30_1_parents[] = {
251 "clk26m",
252 "msdcpll_d2",
253 "univpll2_d2",
254 "syspll2_d2",
255 "syspll1_d4",
256 "univpll1_d4",
257 "usb20_192m_d4",
258 "syspll2_d4"
259};
260
261static const char * const audio_parents[] = {
262 "clk26m",
263 "syspll3_d4",
264 "syspll4_d4",
265 "syspll1_d16"
266};
267
268static const char * const aud_intbus_parents[] = {
269 "clk26m",
270 "syspll1_d4",
271 "syspll4_d2"
272};
273
274static const char * const aud_1_parents[] = {
275 "clk26m",
276 "apll1_ck"
277};
278
279static const char * const aud_engen1_parents[] = {
280 "clk26m",
281 "apll1_d2",
282 "apll1_d4",
283 "apll1_d8"
284};
285
286static const char * const disp_pwm_parents[] = {
287 "clk26m",
288 "univpll2_d4",
289 "ulposc1_d2",
290 "ulposc1_d8"
291};
292
293static const char * const sspm_parents[] = {
294 "clk26m",
295 "syspll1_d2",
296 "syspll_d3"
297};
298
299static const char * const dxcc_parents[] = {
300 "clk26m",
301 "syspll1_d2",
302 "syspll1_d4",
303 "syspll1_d8"
304};
305
306static const char * const usb_top_parents[] = {
307 "clk26m",
308 "univpll3_d4"
309};
310
311static const char * const spm_parents[] = {
312 "clk26m",
313 "syspll1_d8"
314};
315
316static const char * const i2c_parents[] = {
317 "clk26m",
318 "univpll3_d4",
319 "univpll3_d2",
320 "syspll1_d8",
321 "syspll2_d8"
322};
323
324static const char * const pwm_parents[] = {
325 "clk26m",
326 "univpll3_d4",
327 "syspll1_d8"
328};
329
330static const char * const seninf_parents[] = {
331 "clk26m",
332 "univpll1_d4",
333 "univpll1_d2",
334 "univpll2_d2"
335};
336
337static const char * const aes_fde_parents[] = {
338 "clk26m",
339 "msdcpll_ck",
340 "univpll_d3",
341 "univpll2_d2",
342 "univpll1_d2",
343 "syspll1_d2"
344};
345
346static const char * const ulposc_parents[] = {
347 "clk26m",
348 "ulposc1_d4",
349 "ulposc1_d8",
350 "ulposc1_d16",
351 "ulposc1_d32"
352};
353
354static const char * const camtm_parents[] = {
355 "clk26m",
356 "univpll1_d4",
357 "univpll1_d2",
358 "univpll2_d2"
359};
360
361#define INVALID_UPDATE_REG 0xFFFFFFFF
362#define INVALID_UPDATE_SHIFT -1
363#define INVALID_MUX_GATE -1
364
365static const struct mtk_mux top_muxes[] = {
366
367 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
368 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
369 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
370 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
371 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
372 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
373 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
374 CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
375 CLK_CFG_UPDATE, 2),
376 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
377 CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
378 CLK_CFG_UPDATE, 3),
379
380 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
381 CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
382 CLK_CFG_UPDATE, 4),
383 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
384 CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
385 CLK_CFG_UPDATE, 5),
386 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
387 camtg_parents, CLK_CFG_1, CLK_CFG_1_SET,
388 CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
389 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
390 CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,
391 24, 3, 31, CLK_CFG_UPDATE, 7),
392
393 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
394 camtg_parents, CLK_CFG_2, CLK_CFG_2_SET,
395 CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8),
396 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
397 CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR,
398 8, 3, 15, CLK_CFG_UPDATE, 9),
399 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
400 CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23,
401 CLK_CFG_UPDATE, 10),
402 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
403 CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
404 CLK_CFG_UPDATE, 11),
405
406 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
407 msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
408 CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
409 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
410 msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
411 CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
412 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
413 msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
414 CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
415 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
416 CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
417 24, 2, 31, CLK_CFG_UPDATE, 15),
418
419 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
420 aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET,
421 CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16),
422 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
423 CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR,
424 8, 1, 15, CLK_CFG_UPDATE, 17),
425 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
426 aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET,
427 CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18),
428 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
429 disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET,
430 CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19),
431
432 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents,
433 CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7,
434 CLK_CFG_UPDATE, 20),
435 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
436 CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15,
437 CLK_CFG_UPDATE, 21),
438 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
439 usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET,
440 CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22),
441 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5,
442 CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31,
443 CLK_CFG_UPDATE, 23),
444
445 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6,
446 CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE,
447 24),
448 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
449 CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE,
450 25),
451 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,
452 CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23,
453 CLK_CFG_UPDATE, 26),
454 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
455 aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET,
456 CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27),
457
458 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
459 ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
460 CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
461 CLK_IS_CRITICAL),
462 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
463 CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
464 CLK_CFG_UPDATE, 29),
465};
466
467static const struct mtk_gate_regs top0_cg_regs = {
468 .set_ofs = 0x0,
469 .clr_ofs = 0x0,
470 .sta_ofs = 0x0,
471};
472
473static const struct mtk_gate_regs top1_cg_regs = {
474 .set_ofs = 0x104,
475 .clr_ofs = 0x104,
476 .sta_ofs = 0x104,
477};
478
479static const struct mtk_gate_regs top2_cg_regs = {
480 .set_ofs = 0x320,
481 .clr_ofs = 0x320,
482 .sta_ofs = 0x320,
483};
484
485#define GATE_TOP0(_id, _name, _parent, _shift) { \
486 .id = _id, \
487 .name = _name, \
488 .parent_name = _parent, \
489 .regs = &top0_cg_regs, \
490 .shift = _shift, \
491 .ops = &mtk_clk_gate_ops_no_setclr, \
492 }
493
494#define GATE_TOP1(_id, _name, _parent, _shift) { \
495 .id = _id, \
496 .name = _name, \
497 .parent_name = _parent, \
498 .regs = &top1_cg_regs, \
499 .shift = _shift, \
500 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
501 }
502
503#define GATE_TOP2(_id, _name, _parent, _shift) { \
504 .id = _id, \
505 .name = _name, \
506 .parent_name = _parent, \
507 .regs = &top2_cg_regs, \
508 .shift = _shift, \
509 .ops = &mtk_clk_gate_ops_no_setclr, \
510 }
511
512static const struct mtk_gate top_clks[] = {
513
514 GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8),
515 GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9),
516 GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10),
517 GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11),
518
519 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN,
520 "arm_div_pll0_en", "arm_div_pll0", 3),
521 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
522 "arm_div_pll1_en", "arm_div_pll1", 4),
523 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
524 "arm_div_pll2_en", "arm_div_pll2", 5),
525 GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6),
526 GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8),
527 GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9),
528 GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12),
529 GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16),
530
531 GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
532 GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
533 GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
534 GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
535};
536
537static const struct mtk_gate_regs ifr2_cg_regs = {
538 .set_ofs = 0x80,
539 .clr_ofs = 0x84,
540 .sta_ofs = 0x90,
541};
542
543static const struct mtk_gate_regs ifr3_cg_regs = {
544 .set_ofs = 0x88,
545 .clr_ofs = 0x8c,
546 .sta_ofs = 0x94,
547};
548
549static const struct mtk_gate_regs ifr4_cg_regs = {
550 .set_ofs = 0xa4,
551 .clr_ofs = 0xa8,
552 .sta_ofs = 0xac,
553};
554
555static const struct mtk_gate_regs ifr5_cg_regs = {
556 .set_ofs = 0xc0,
557 .clr_ofs = 0xc4,
558 .sta_ofs = 0xc8,
559};
560
561#define GATE_IFR2(_id, _name, _parent, _shift) { \
562 .id = _id, \
563 .name = _name, \
564 .parent_name = _parent, \
565 .regs = &ifr2_cg_regs, \
566 .shift = _shift, \
567 .ops = &mtk_clk_gate_ops_setclr, \
568 }
569
570#define GATE_IFR3(_id, _name, _parent, _shift) { \
571 .id = _id, \
572 .name = _name, \
573 .parent_name = _parent, \
574 .regs = &ifr3_cg_regs, \
575 .shift = _shift, \
576 .ops = &mtk_clk_gate_ops_setclr, \
577 }
578
579#define GATE_IFR4(_id, _name, _parent, _shift) { \
580 .id = _id, \
581 .name = _name, \
582 .parent_name = _parent, \
583 .regs = &ifr4_cg_regs, \
584 .shift = _shift, \
585 .ops = &mtk_clk_gate_ops_setclr, \
586 }
587
588#define GATE_IFR5(_id, _name, _parent, _shift) { \
589 .id = _id, \
590 .name = _name, \
591 .parent_name = _parent, \
592 .regs = &ifr5_cg_regs, \
593 .shift = _shift, \
594 .ops = &mtk_clk_gate_ops_setclr, \
595 }
596
597static const struct mtk_gate ifr_clks[] = {
598
599
600
601 GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8),
602 GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9),
603 GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10),
604 GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11),
605 GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12),
606 GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13),
607 GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14),
608 GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15),
609 GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16),
610 GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17),
611 GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18),
612 GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19),
613 GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20),
614 GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21),
615 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22),
616 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23),
617 GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27),
618 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28),
619 GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31),
620
621 GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1),
622 GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2),
623 GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4),
624 GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9),
625 GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10),
626 GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12),
627 GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13),
628 GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14),
629 GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18),
630 GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20),
631 GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23),
632 GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25),
633 GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26),
634
635 GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0),
636 GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2),
637 GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3),
638 GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4),
639 GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6),
640 GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7),
641 GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9),
642 GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10),
643 GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18),
644 GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19),
645 GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20),
646 GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21),
647 GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22),
648 GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23),
649 GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24),
650 GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25),
651 GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26),
652 GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27),
653 GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29),
654
655 GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0),
656 GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1),
657 GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6),
658 GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7),
659 GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8),
660 GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9),
661 GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10),
662 GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17),
663 GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18),
664 GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19),
665 GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20),
666 GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21),
667};
668
669
670static const struct mtk_gate_regs apmixed_cg_regs = {
671 .set_ofs = 0x14,
672 .clr_ofs = 0x14,
673 .sta_ofs = 0x14,
674};
675
676#define GATE_APMIXED(_id, _name, _parent, _shift) { \
677 .id = _id, \
678 .name = _name, \
679 .parent_name = _parent, \
680 .regs = &apmixed_cg_regs, \
681 .shift = _shift, \
682 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
683 }
684
685static const struct mtk_gate apmixed_clks[] = {
686
687 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck",
688 4),
689 GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck",
690 5),
691 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck",
692 6),
693 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck",
694 7),
695 GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck",
696 8),
697 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck",
698 9),
699 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck",
700 11),
701 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck",
702 13),
703 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
704 "f_f26m_ck", 14),
705 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck",
706 16),
707};
708
709#define MT6765_PLL_FMAX (3800UL * MHZ)
710#define MT6765_PLL_FMIN (1500UL * MHZ)
711
712#define CON0_MT6765_RST_BAR BIT(23)
713
714#define PLL_INFO_NULL (0xFF)
715
716#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
717 _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\
718 _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\
719 .id = _id, \
720 .name = _name, \
721 .reg = _reg, \
722 .pwr_reg = _pwr_reg, \
723 .en_mask = _en_mask, \
724 .flags = _flags, \
725 .rst_bar_mask = CON0_MT6765_RST_BAR, \
726 .fmax = MT6765_PLL_FMAX, \
727 .fmin = MT6765_PLL_FMIN, \
728 .pcwbits = _pcwbits, \
729 .pcwibits = _pcwibits, \
730 .pd_reg = _pd_reg, \
731 .pd_shift = _pd_shift, \
732 .tuner_reg = _tuner_reg, \
733 .tuner_en_reg = _tuner_en_reg, \
734 .tuner_en_bit = _tuner_en_bit, \
735 .pcw_reg = _pcw_reg, \
736 .pcw_shift = _pcw_shift, \
737 .div_table = _div_table, \
738 }
739
740#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
741 _pcwibits, _pd_reg, _pd_shift, _tuner_reg, \
742 _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
743 _pcw_shift) \
744 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
745 _pcwbits, _pcwibits, _pd_reg, _pd_shift, \
746 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
747 _pcw_reg, _pcw_shift, NULL) \
748
749static const struct mtk_pll_data plls[] = {
750 PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
751 PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
752 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
753 PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
754 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
755 PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
756 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
757 (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
758 0),
759 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
760 0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
761 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
762 0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
763 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
764 HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
765 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
766 0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
767 PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
768 0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
769 PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
770 PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
771};
772
773static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
774{
775 struct clk_onecell_data *clk_data;
776 int r;
777 struct device_node *node = pdev->dev.of_node;
778 void __iomem *base;
779 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
780
781 base = devm_ioremap_resource(&pdev->dev, res);
782 if (IS_ERR(base)) {
783 pr_err("%s(): ioremap failed\n", __func__);
784 return PTR_ERR(base);
785 }
786
787 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
788
789 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
790
791 mtk_clk_register_gates(node, apmixed_clks,
792 ARRAY_SIZE(apmixed_clks), clk_data);
793 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
794
795 if (r)
796 pr_err("%s(): could not register clock provider: %d\n",
797 __func__, r);
798
799 apmixed_base = base;
800
801 writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3);
802 writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0);
803 writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1);
804
805 return r;
806}
807
808static int clk_mt6765_top_probe(struct platform_device *pdev)
809{
810 int r;
811 struct device_node *node = pdev->dev.of_node;
812 void __iomem *base;
813 struct clk_onecell_data *clk_data;
814 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815
816 base = devm_ioremap_resource(&pdev->dev, res);
817 if (IS_ERR(base)) {
818 pr_err("%s(): ioremap failed\n", __func__);
819 return PTR_ERR(base);
820 }
821
822 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
823
824 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
825 clk_data);
826 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
827 clk_data);
828 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
829 &mt6765_clk_lock, clk_data);
830 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
831 clk_data);
832
833 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
834
835 if (r)
836 pr_err("%s(): could not register clock provider: %d\n",
837 __func__, r);
838
839 cksys_base = base;
840
841 writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0);
842
843 writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1);
844
845 return r;
846}
847
848static int clk_mt6765_ifr_probe(struct platform_device *pdev)
849{
850 struct clk_onecell_data *clk_data;
851 int r;
852 struct device_node *node = pdev->dev.of_node;
853 void __iomem *base;
854 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
855
856 base = devm_ioremap_resource(&pdev->dev, res);
857 if (IS_ERR(base)) {
858 pr_err("%s(): ioremap failed\n", __func__);
859 return PTR_ERR(base);
860 }
861
862 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
863
864 mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
865 clk_data);
866 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
867
868 if (r)
869 pr_err("%s(): could not register clock provider: %d\n",
870 __func__, r);
871
872 return r;
873}
874
875static const struct of_device_id of_match_clk_mt6765[] = {
876 {
877 .compatible = "mediatek,mt6765-apmixedsys",
878 .data = clk_mt6765_apmixed_probe,
879 }, {
880 .compatible = "mediatek,mt6765-topckgen",
881 .data = clk_mt6765_top_probe,
882 }, {
883 .compatible = "mediatek,mt6765-infracfg",
884 .data = clk_mt6765_ifr_probe,
885 }, {
886
887 }
888};
889
890static int clk_mt6765_probe(struct platform_device *pdev)
891{
892 int (*clk_probe)(struct platform_device *d);
893 int r;
894
895 clk_probe = of_device_get_match_data(&pdev->dev);
896 if (!clk_probe)
897 return -EINVAL;
898
899 r = clk_probe(pdev);
900 if (r)
901 dev_err(&pdev->dev,
902 "could not register clock provider: %s: %d\n",
903 pdev->name, r);
904
905 return r;
906}
907
908static struct platform_driver clk_mt6765_drv = {
909 .probe = clk_mt6765_probe,
910 .driver = {
911 .name = "clk-mt6765",
912 .of_match_table = of_match_clk_mt6765,
913 },
914};
915
916static int __init clk_mt6765_init(void)
917{
918 return platform_driver_register(&clk_mt6765_drv);
919}
920
921arch_initcall(clk_mt6765_init);
922
