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7#include <linux/clk.h>
8#include <linux/of.h>
9#include <linux/of_address.h>
10#include <linux/slab.h>
11#include <linux/mfd/syscon.h>
12#include <dt-bindings/clock/mt8135-clk.h>
13
14#include "clk-mtk.h"
15#include "clk-gate.h"
16
17static DEFINE_SPINLOCK(mt8135_clk_lock);
18
19static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
20 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
21 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
22 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
23 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
24};
25
26static const struct mtk_fixed_factor top_divs[] __initconst = {
27 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
28 FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
29 FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
30 FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
31
32 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
33 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
34 FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
35 FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
36 FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
37
38 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
39 FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
40 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
41 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
42 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
43 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
44
45 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
46 FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
47 FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
48 FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
49 FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
50 FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
51 FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
52 FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
53
54 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
55
56 FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
57 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
58
59 FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
60
61 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
62 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
63 FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
64 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
65 FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
66
67 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
68 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
69 FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
70 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
71
72 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
73 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
74 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
75 FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
76 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
77
78 FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
79 FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
80 FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
81 FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
82 FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
83
84 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
85 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
86 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
87
88 FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
89 FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
90
91 FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
92
93 FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
94 FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
95
96 FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
97 FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
98
99 FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
100};
101
102static const char * const axi_parents[] __initconst = {
103 "clk26m",
104 "syspll_d3",
105 "syspll_d4",
106 "syspll_d6",
107 "univpll_d5",
108 "univpll2_d2",
109 "syspll_d3p5"
110};
111
112static const char * const smi_parents[] __initconst = {
113 "clk26m",
114 "clkph_mck",
115 "syspll_d2p5",
116 "syspll_d3",
117 "syspll_d8",
118 "univpll_d5",
119 "univpll1_d2",
120 "univpll1_d6",
121 "mmpll_d3",
122 "mmpll_d4",
123 "mmpll_d5",
124 "mmpll_d6",
125 "mmpll_d7",
126 "vdecpll",
127 "lvdspll"
128};
129
130static const char * const mfg_parents[] __initconst = {
131 "clk26m",
132 "univpll1_d4",
133 "syspll_d2",
134 "syspll_d2p5",
135 "syspll_d3",
136 "univpll_d5",
137 "univpll1_d2",
138 "mmpll_d2",
139 "mmpll_d3",
140 "mmpll_d4",
141 "mmpll_d5",
142 "mmpll_d6",
143 "mmpll_d7"
144};
145
146static const char * const irda_parents[] __initconst = {
147 "clk26m",
148 "univpll2_d8",
149 "univpll1_d6"
150};
151
152static const char * const cam_parents[] __initconst = {
153 "clk26m",
154 "syspll_d3",
155 "syspll_d3p5",
156 "syspll_d4",
157 "univpll_d5",
158 "univpll2_d2",
159 "univpll_d7",
160 "univpll1_d4"
161};
162
163static const char * const aud_intbus_parents[] __initconst = {
164 "clk26m",
165 "syspll_d6",
166 "univpll_d10"
167};
168
169static const char * const jpg_parents[] __initconst = {
170 "clk26m",
171 "syspll_d5",
172 "syspll_d4",
173 "syspll_d3",
174 "univpll_d7",
175 "univpll2_d2",
176 "univpll_d5"
177};
178
179static const char * const disp_parents[] __initconst = {
180 "clk26m",
181 "syspll_d3p5",
182 "syspll_d3",
183 "univpll2_d2",
184 "univpll_d5",
185 "univpll1_d2",
186 "lvdspll",
187 "vdecpll"
188};
189
190static const char * const msdc30_parents[] __initconst = {
191 "clk26m",
192 "syspll_d6",
193 "syspll_d5",
194 "univpll1_d4",
195 "univpll2_d4",
196 "msdcpll"
197};
198
199static const char * const usb20_parents[] __initconst = {
200 "clk26m",
201 "univpll2_d6",
202 "univpll1_d10"
203};
204
205static const char * const venc_parents[] __initconst = {
206 "clk26m",
207 "syspll_d3",
208 "syspll_d8",
209 "univpll_d5",
210 "univpll1_d6",
211 "mmpll_d4",
212 "mmpll_d5",
213 "mmpll_d6"
214};
215
216static const char * const spi_parents[] __initconst = {
217 "clk26m",
218 "syspll_d6",
219 "syspll_d8",
220 "syspll_d10",
221 "univpll1_d6",
222 "univpll1_d8"
223};
224
225static const char * const uart_parents[] __initconst = {
226 "clk26m",
227 "univpll2_d8"
228};
229
230static const char * const mem_parents[] __initconst = {
231 "clk26m",
232 "clkph_mck"
233};
234
235static const char * const camtg_parents[] __initconst = {
236 "clk26m",
237 "univpll_d26",
238 "univpll1_d6",
239 "syspll_d16",
240 "syspll_d8"
241};
242
243static const char * const audio_parents[] __initconst = {
244 "clk26m",
245 "syspll_d24"
246};
247
248static const char * const fix_parents[] __initconst = {
249 "rtc32k",
250 "clk26m",
251 "univpll_d5",
252 "univpll_d7",
253 "univpll1_d2",
254 "univpll1_d4",
255 "univpll1_d6",
256 "univpll1_d8"
257};
258
259static const char * const vdec_parents[] __initconst = {
260 "clk26m",
261 "vdecpll",
262 "clkph_mck",
263 "syspll_d2p5",
264 "syspll_d3",
265 "syspll_d3p5",
266 "syspll_d4",
267 "syspll_d5",
268 "syspll_d6",
269 "syspll_d8",
270 "univpll1_d2",
271 "univpll2_d2",
272 "univpll_d7",
273 "univpll_d10",
274 "univpll2_d4",
275 "lvdspll"
276};
277
278static const char * const ddrphycfg_parents[] __initconst = {
279 "clk26m",
280 "axi_sel",
281 "syspll_d12"
282};
283
284static const char * const dpilvds_parents[] __initconst = {
285 "clk26m",
286 "lvdspll",
287 "lvdspll_d2",
288 "lvdspll_d4",
289 "lvdspll_d8"
290};
291
292static const char * const pmicspi_parents[] __initconst = {
293 "clk26m",
294 "univpll2_d6",
295 "syspll_d8",
296 "syspll_d10",
297 "univpll1_d10",
298 "mempll_mck_d4",
299 "univpll_d26",
300 "syspll_d24"
301};
302
303static const char * const smi_mfg_as_parents[] __initconst = {
304 "clk26m",
305 "smi_sel",
306 "mfg_sel",
307 "mem_sel"
308};
309
310static const char * const gcpu_parents[] __initconst = {
311 "clk26m",
312 "syspll_d4",
313 "univpll_d7",
314 "syspll_d5",
315 "syspll_d6"
316};
317
318static const char * const dpi1_parents[] __initconst = {
319 "clk26m",
320 "tvhdmi_h_ck",
321 "tvhdmi_d2",
322 "tvhdmi_d4"
323};
324
325static const char * const cci_parents[] __initconst = {
326 "clk26m",
327 "mainpll_537p3m",
328 "univpll_d3",
329 "syspll_d2p5",
330 "syspll_d3",
331 "syspll_d5"
332};
333
334static const char * const apll_parents[] __initconst = {
335 "clk26m",
336 "apll_ck",
337 "apll_d4",
338 "apll_d8",
339 "apll_d16",
340 "apll_d24"
341};
342
343static const char * const hdmipll_parents[] __initconst = {
344 "clk26m",
345 "hdmitx_clkdig_cts",
346 "hdmitx_clkdig_d2",
347 "hdmitx_clkdig_d3"
348};
349
350static const struct mtk_composite top_muxes[] __initconst = {
351
352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
353 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
354 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
355 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
356 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
357
358 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
359 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
360 0x0144, 8, 2, 15),
361 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
362 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
363
364 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
365 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
366 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
367 MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
368
369 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
370
371 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
372 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
373 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
374
375 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
376 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
377 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
378
379 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
380 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
381 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
382 0x015c, 16, 2, 23),
383 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
384
385 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
386 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
387 MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
388 0x0164, 16, 2, 23),
389 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
390
391 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
392 MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
393 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
394 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
395};
396
397static const struct mtk_gate_regs infra_cg_regs = {
398 .set_ofs = 0x0040,
399 .clr_ofs = 0x0044,
400 .sta_ofs = 0x0048,
401};
402
403#define GATE_ICG(_id, _name, _parent, _shift) { \
404 .id = _id, \
405 .name = _name, \
406 .parent_name = _parent, \
407 .regs = &infra_cg_regs, \
408 .shift = _shift, \
409 .ops = &mtk_clk_gate_ops_setclr, \
410 }
411
412static const struct mtk_gate infra_clks[] __initconst = {
413 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
414 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
415 GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
416 GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
417 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
418 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
419 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
420 GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
421 GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
422 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
423 GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
424 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
425 GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
426};
427
428static const struct mtk_gate_regs peri0_cg_regs = {
429 .set_ofs = 0x0008,
430 .clr_ofs = 0x0010,
431 .sta_ofs = 0x0018,
432};
433
434static const struct mtk_gate_regs peri1_cg_regs = {
435 .set_ofs = 0x000c,
436 .clr_ofs = 0x0014,
437 .sta_ofs = 0x001c,
438};
439
440#define GATE_PERI0(_id, _name, _parent, _shift) { \
441 .id = _id, \
442 .name = _name, \
443 .parent_name = _parent, \
444 .regs = &peri0_cg_regs, \
445 .shift = _shift, \
446 .ops = &mtk_clk_gate_ops_setclr, \
447 }
448
449#define GATE_PERI1(_id, _name, _parent, _shift) { \
450 .id = _id, \
451 .name = _name, \
452 .parent_name = _parent, \
453 .regs = &peri1_cg_regs, \
454 .shift = _shift, \
455 .ops = &mtk_clk_gate_ops_setclr, \
456 }
457
458static const struct mtk_gate peri_gates[] __initconst = {
459
460 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
461 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
462 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
463 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
464 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
465 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
466 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
467 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
468 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
469 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
470 GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
471 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
472 GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
473 GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
474 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
475 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
476 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
477 GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
478 GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
479 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
480 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
481 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
482 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
483 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
484 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
485 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
486 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
487 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
488 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
489 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
490 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
491 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
492
493 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
494 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
495 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
496 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
497 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
498 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
499 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
500 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
501 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
502};
503
504static const char * const uart_ck_sel_parents[] __initconst = {
505 "clk26m",
506 "uart_sel",
507};
508
509static const struct mtk_composite peri_clks[] __initconst = {
510 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
511 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
512 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
513 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
514};
515
516static void __init mtk_topckgen_init(struct device_node *node)
517{
518 struct clk_onecell_data *clk_data;
519 void __iomem *base;
520 int r;
521
522 base = of_iomap(node, 0);
523 if (!base) {
524 pr_err("%s(): ioremap failed\n", __func__);
525 return;
526 }
527
528 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
529
530 mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
531 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
532 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
533 &mt8135_clk_lock, clk_data);
534
535 clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
536
537 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
538 if (r)
539 pr_err("%s(): could not register clock provider: %d\n",
540 __func__, r);
541}
542CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
543
544static void __init mtk_infrasys_init(struct device_node *node)
545{
546 struct clk_onecell_data *clk_data;
547 int r;
548
549 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
550
551 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
552 clk_data);
553
554 clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
555
556 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
557 if (r)
558 pr_err("%s(): could not register clock provider: %d\n",
559 __func__, r);
560
561 mtk_register_reset_controller(node, 2, 0x30);
562}
563CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
564
565static void __init mtk_pericfg_init(struct device_node *node)
566{
567 struct clk_onecell_data *clk_data;
568 int r;
569 void __iomem *base;
570
571 base = of_iomap(node, 0);
572 if (!base) {
573 pr_err("%s(): ioremap failed\n", __func__);
574 return;
575 }
576
577 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
578
579 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
580 clk_data);
581 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
582 &mt8135_clk_lock, clk_data);
583
584 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
585 if (r)
586 pr_err("%s(): could not register clock provider: %d\n",
587 __func__, r);
588
589 mtk_register_reset_controller(node, 2, 0);
590}
591CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
592
593#define MT8135_PLL_FMAX (2000 * MHZ)
594#define CON0_MT8135_RST_BAR BIT(27)
595
596#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
597 .id = _id, \
598 .name = _name, \
599 .reg = _reg, \
600 .pwr_reg = _pwr_reg, \
601 .en_mask = _en_mask, \
602 .flags = _flags, \
603 .rst_bar_mask = CON0_MT8135_RST_BAR, \
604 .fmax = MT8135_PLL_FMAX, \
605 .pcwbits = _pcwbits, \
606 .pd_reg = _pd_reg, \
607 .pd_shift = _pd_shift, \
608 .tuner_reg = _tuner_reg, \
609 .pcw_reg = _pcw_reg, \
610 .pcw_shift = _pcw_shift, \
611 }
612
613static const struct mtk_pll_data plls[] = {
614 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
615 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
616 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
617 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
618 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
619 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
620 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
621 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
622 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
623 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
624};
625
626static void __init mtk_apmixedsys_init(struct device_node *node)
627{
628 struct clk_onecell_data *clk_data;
629
630 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
631 if (!clk_data)
632 return;
633
634 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
635}
636CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
637 mtk_apmixedsys_init);
638
