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6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/mfd/syscon.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14
15#include "clk-mtk.h"
16#include "clk-mux.h"
17#include "clk-gate.h"
18
19#include <dt-bindings/clock/mt8192-clk.h>
20
21static DEFINE_SPINLOCK(mt8192_clk_lock);
22
23static const struct mtk_fixed_clk top_fixed_clks[] = {
24 FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
25};
26
27static const struct mtk_fixed_factor top_early_divs[] = {
28 FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
29};
30
31static const struct mtk_fixed_factor top_divs[] = {
32 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
33 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
34 FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
35 FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
36 FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
37 FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16),
38 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
39 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
40 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
41 FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
42 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
43 FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
44 FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
45 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
46 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
47 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
48 FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
49 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
50 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
51 FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
52 FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
53 FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
54 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
55 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
56 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
57 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
58 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
59 FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
60 FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
61 FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
62 FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
63 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
64 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
65 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
66 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
67 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
68 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
69 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
70 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
71 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
72 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
73 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
74 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
75 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
76 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
77 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
78 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
79 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
80 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2),
81 FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1),
82 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
83 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
84 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
85 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
86 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
87 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
88 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
89 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
90 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
91 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
92 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
93 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
94 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
95 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
96 FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
97 FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
98 FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2),
99 FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
100 FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
101 FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
102 FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
103};
104
105static const char * const axi_parents[] = {
106 "clk26m",
107 "mainpll_d4_d4",
108 "mainpll_d7_d2",
109 "mainpll_d4_d2",
110 "mainpll_d5_d2",
111 "mainpll_d6_d2",
112 "osc_d4"
113};
114
115static const char * const spm_parents[] = {
116 "clk26m",
117 "osc_d10",
118 "mainpll_d7_d4",
119 "clk32k"
120};
121
122static const char * const scp_parents[] = {
123 "clk26m",
124 "univpll_d5",
125 "mainpll_d6_d2",
126 "mainpll_d6",
127 "univpll_d6",
128 "mainpll_d4_d2",
129 "mainpll_d5_d2",
130 "univpll_d4_d2"
131};
132
133static const char * const bus_aximem_parents[] = {
134 "clk26m",
135 "mainpll_d7_d2",
136 "mainpll_d4_d2",
137 "mainpll_d5_d2",
138 "mainpll_d6"
139};
140
141static const char * const disp_parents[] = {
142 "clk26m",
143 "univpll_d6_d2",
144 "mainpll_d5_d2",
145 "mmpll_d6_d2",
146 "univpll_d5_d2",
147 "univpll_d4_d2",
148 "mmpll_d7",
149 "univpll_d6",
150 "mainpll_d4",
151 "mmpll_d5_d2"
152};
153
154static const char * const mdp_parents[] = {
155 "clk26m",
156 "mainpll_d5_d2",
157 "mmpll_d6_d2",
158 "mainpll_d4_d2",
159 "mmpll_d4_d2",
160 "mainpll_d6",
161 "univpll_d6",
162 "mainpll_d4",
163 "tvdpll_ck",
164 "univpll_d4",
165 "mmpll_d5_d2"
166};
167
168static const char * const img1_parents[] = {
169 "clk26m",
170 "univpll_d4",
171 "tvdpll_ck",
172 "mainpll_d4",
173 "univpll_d5",
174 "mmpll_d6",
175 "univpll_d6",
176 "mainpll_d6",
177 "mmpll_d4_d2",
178 "mainpll_d4_d2",
179 "mmpll_d6_d2",
180 "mmpll_d5_d2"
181};
182
183static const char * const img2_parents[] = {
184 "clk26m",
185 "univpll_d4",
186 "tvdpll_ck",
187 "mainpll_d4",
188 "univpll_d5",
189 "mmpll_d6",
190 "univpll_d6",
191 "mainpll_d6",
192 "mmpll_d4_d2",
193 "mainpll_d4_d2",
194 "mmpll_d6_d2",
195 "mmpll_d5_d2"
196};
197
198static const char * const ipe_parents[] = {
199 "clk26m",
200 "mainpll_d4",
201 "mmpll_d6",
202 "univpll_d6",
203 "mainpll_d6",
204 "univpll_d4_d2",
205 "mainpll_d4_d2",
206 "mmpll_d6_d2",
207 "mmpll_d5_d2"
208};
209
210static const char * const dpe_parents[] = {
211 "clk26m",
212 "mainpll_d4",
213 "mmpll_d6",
214 "univpll_d6",
215 "mainpll_d6",
216 "univpll_d4_d2",
217 "univpll_d5_d2",
218 "mmpll_d6_d2"
219};
220
221static const char * const cam_parents[] = {
222 "clk26m",
223 "mainpll_d4",
224 "mmpll_d6",
225 "univpll_d4",
226 "univpll_d5",
227 "univpll_d6",
228 "mmpll_d7",
229 "univpll_d4_d2",
230 "mainpll_d4_d2",
231 "univpll_d6_d2"
232};
233
234static const char * const ccu_parents[] = {
235 "clk26m",
236 "mainpll_d4",
237 "mmpll_d6",
238 "mainpll_d6",
239 "mmpll_d7",
240 "univpll_d4_d2",
241 "mmpll_d6_d2",
242 "mmpll_d5_d2",
243 "univpll_d5",
244 "univpll_d6_d2"
245};
246
247static const char * const dsp7_parents[] = {
248 "clk26m",
249 "mainpll_d4_d2",
250 "mainpll_d6",
251 "mmpll_d6",
252 "univpll_d5",
253 "mmpll_d5",
254 "univpll_d4",
255 "mmpll_d4"
256};
257
258static const char * const mfg_ref_parents[] = {
259 "clk26m",
260 "clk26m",
261 "univpll_d6",
262 "mainpll_d5_d2"
263};
264
265static const char * const mfg_pll_parents[] = {
266 "mfg_ref_sel",
267 "mfgpll"
268};
269
270static const char * const camtg_parents[] = {
271 "clk26m",
272 "univpll_192m_d8",
273 "univpll_d6_d8",
274 "univpll_192m_d4",
275 "univpll_d6_d16",
276 "csw_f26m_d2",
277 "univpll_192m_d16",
278 "univpll_192m_d32"
279};
280
281static const char * const camtg2_parents[] = {
282 "clk26m",
283 "univpll_192m_d8",
284 "univpll_d6_d8",
285 "univpll_192m_d4",
286 "univpll_d6_d16",
287 "csw_f26m_d2",
288 "univpll_192m_d16",
289 "univpll_192m_d32"
290};
291
292static const char * const camtg3_parents[] = {
293 "clk26m",
294 "univpll_192m_d8",
295 "univpll_d6_d8",
296 "univpll_192m_d4",
297 "univpll_d6_d16",
298 "csw_f26m_d2",
299 "univpll_192m_d16",
300 "univpll_192m_d32"
301};
302
303static const char * const camtg4_parents[] = {
304 "clk26m",
305 "univpll_192m_d8",
306 "univpll_d6_d8",
307 "univpll_192m_d4",
308 "univpll_d6_d16",
309 "csw_f26m_d2",
310 "univpll_192m_d16",
311 "univpll_192m_d32"
312};
313
314static const char * const camtg5_parents[] = {
315 "clk26m",
316 "univpll_192m_d8",
317 "univpll_d6_d8",
318 "univpll_192m_d4",
319 "univpll_d6_d16",
320 "csw_f26m_d2",
321 "univpll_192m_d16",
322 "univpll_192m_d32"
323};
324
325static const char * const camtg6_parents[] = {
326 "clk26m",
327 "univpll_192m_d8",
328 "univpll_d6_d8",
329 "univpll_192m_d4",
330 "univpll_d6_d16",
331 "csw_f26m_d2",
332 "univpll_192m_d16",
333 "univpll_192m_d32"
334};
335
336static const char * const uart_parents[] = {
337 "clk26m",
338 "univpll_d6_d8"
339};
340
341static const char * const spi_parents[] = {
342 "clk26m",
343 "mainpll_d5_d4",
344 "mainpll_d6_d4",
345 "msdcpll_d4"
346};
347
348static const char * const msdc50_0_h_parents[] = {
349 "clk26m",
350 "mainpll_d4_d2",
351 "mainpll_d6_d2"
352};
353
354static const char * const msdc50_0_parents[] = {
355 "clk26m",
356 "msdcpll_ck",
357 "msdcpll_d2",
358 "univpll_d4_d4",
359 "mainpll_d6_d2",
360 "univpll_d4_d2"
361};
362
363static const char * const msdc30_1_parents[] = {
364 "clk26m",
365 "univpll_d6_d2",
366 "mainpll_d6_d2",
367 "mainpll_d7_d2",
368 "msdcpll_d2"
369};
370
371static const char * const msdc30_2_parents[] = {
372 "clk26m",
373 "univpll_d6_d2",
374 "mainpll_d6_d2",
375 "mainpll_d7_d2",
376 "msdcpll_d2"
377};
378
379static const char * const audio_parents[] = {
380 "clk26m",
381 "mainpll_d5_d8",
382 "mainpll_d7_d8",
383 "mainpll_d4_d16"
384};
385
386static const char * const aud_intbus_parents[] = {
387 "clk26m",
388 "mainpll_d4_d4",
389 "mainpll_d7_d4"
390};
391
392static const char * const pwrap_ulposc_parents[] = {
393 "osc_d10",
394 "clk26m",
395 "osc_d4",
396 "osc_d8",
397 "osc_d16"
398};
399
400static const char * const atb_parents[] = {
401 "clk26m",
402 "mainpll_d4_d2",
403 "mainpll_d5_d2"
404};
405
406static const char * const dpi_parents[] = {
407 "clk26m",
408 "tvdpll_d2",
409 "tvdpll_d4",
410 "tvdpll_d8",
411 "tvdpll_d16"
412};
413
414static const char * const scam_parents[] = {
415 "clk26m",
416 "mainpll_d5_d4"
417};
418
419static const char * const disp_pwm_parents[] = {
420 "clk26m",
421 "univpll_d6_d4",
422 "osc_d2",
423 "osc_d4",
424 "osc_d16"
425};
426
427static const char * const usb_top_parents[] = {
428 "clk26m",
429 "univpll_d5_d4",
430 "univpll_d6_d4",
431 "univpll_d5_d2"
432};
433
434static const char * const ssusb_xhci_parents[] = {
435 "clk26m",
436 "univpll_d5_d4",
437 "univpll_d6_d4",
438 "univpll_d5_d2"
439};
440
441static const char * const i2c_parents[] = {
442 "clk26m",
443 "mainpll_d4_d8",
444 "univpll_d5_d4"
445};
446
447static const char * const seninf_parents[] = {
448 "clk26m",
449 "univpll_d4_d4",
450 "univpll_d6_d2",
451 "univpll_d4_d2",
452 "univpll_d7",
453 "univpll_d6",
454 "mmpll_d6",
455 "univpll_d5"
456};
457
458static const char * const seninf1_parents[] = {
459 "clk26m",
460 "univpll_d4_d4",
461 "univpll_d6_d2",
462 "univpll_d4_d2",
463 "univpll_d7",
464 "univpll_d6",
465 "mmpll_d6",
466 "univpll_d5"
467};
468
469static const char * const seninf2_parents[] = {
470 "clk26m",
471 "univpll_d4_d4",
472 "univpll_d6_d2",
473 "univpll_d4_d2",
474 "univpll_d7",
475 "univpll_d6",
476 "mmpll_d6",
477 "univpll_d5"
478};
479
480static const char * const seninf3_parents[] = {
481 "clk26m",
482 "univpll_d4_d4",
483 "univpll_d6_d2",
484 "univpll_d4_d2",
485 "univpll_d7",
486 "univpll_d6",
487 "mmpll_d6",
488 "univpll_d5"
489};
490
491static const char * const tl_parents[] = {
492 "clk26m",
493 "univpll_192m_d2",
494 "mainpll_d6_d4"
495};
496
497static const char * const dxcc_parents[] = {
498 "clk26m",
499 "mainpll_d4_d2",
500 "mainpll_d4_d4",
501 "mainpll_d4_d8"
502};
503
504static const char * const aud_engen1_parents[] = {
505 "clk26m",
506 "apll1_d2",
507 "apll1_d4",
508 "apll1_d8"
509};
510
511static const char * const aud_engen2_parents[] = {
512 "clk26m",
513 "apll2_d2",
514 "apll2_d4",
515 "apll2_d8"
516};
517
518static const char * const aes_ufsfde_parents[] = {
519 "clk26m",
520 "mainpll_d4",
521 "mainpll_d4_d2",
522 "mainpll_d6",
523 "mainpll_d4_d4",
524 "univpll_d4_d2",
525 "univpll_d6"
526};
527
528static const char * const ufs_parents[] = {
529 "clk26m",
530 "mainpll_d4_d4",
531 "mainpll_d4_d8",
532 "univpll_d4_d4",
533 "mainpll_d6_d2",
534 "mainpll_d5_d2",
535 "msdcpll_d2"
536};
537
538static const char * const aud_1_parents[] = {
539 "clk26m",
540 "apll1_ck"
541};
542
543static const char * const aud_2_parents[] = {
544 "clk26m",
545 "apll2_ck"
546};
547
548static const char * const adsp_parents[] = {
549 "clk26m",
550 "mainpll_d6",
551 "mainpll_d5_d2",
552 "univpll_d4_d4",
553 "univpll_d4",
554 "univpll_d6",
555 "ulposc",
556 "adsppll_ck"
557};
558
559static const char * const dpmaif_main_parents[] = {
560 "clk26m",
561 "univpll_d4_d4",
562 "mainpll_d6",
563 "mainpll_d4_d2",
564 "univpll_d4_d2"
565};
566
567static const char * const venc_parents[] = {
568 "clk26m",
569 "mmpll_d7",
570 "mainpll_d6",
571 "univpll_d4_d2",
572 "mainpll_d4_d2",
573 "univpll_d6",
574 "mmpll_d6",
575 "mainpll_d5_d2",
576 "mainpll_d6_d2",
577 "mmpll_d9",
578 "univpll_d4_d4",
579 "mainpll_d4",
580 "univpll_d4",
581 "univpll_d5",
582 "univpll_d5_d2",
583 "mainpll_d5"
584};
585
586static const char * const vdec_parents[] = {
587 "clk26m",
588 "univpll_192m_d2",
589 "univpll_d5_d4",
590 "mainpll_d5",
591 "mainpll_d5_d2",
592 "mmpll_d6_d2",
593 "univpll_d5_d2",
594 "mainpll_d4_d2",
595 "univpll_d4_d2",
596 "univpll_d7",
597 "mmpll_d7",
598 "mmpll_d6",
599 "univpll_d5",
600 "mainpll_d4",
601 "univpll_d4",
602 "univpll_d6"
603};
604
605static const char * const camtm_parents[] = {
606 "clk26m",
607 "univpll_d7",
608 "univpll_d6_d2",
609 "univpll_d4_d2"
610};
611
612static const char * const pwm_parents[] = {
613 "clk26m",
614 "univpll_d4_d8"
615};
616
617static const char * const audio_h_parents[] = {
618 "clk26m",
619 "univpll_d7",
620 "apll1_ck",
621 "apll2_ck"
622};
623
624static const char * const spmi_mst_parents[] = {
625 "clk26m",
626 "csw_f26m_d2",
627 "osc_d8",
628 "osc_d10",
629 "osc_d16",
630 "osc_d20",
631 "clk32k"
632};
633
634static const char * const aes_msdcfde_parents[] = {
635 "clk26m",
636 "mainpll_d4_d2",
637 "mainpll_d6",
638 "mainpll_d4_d4",
639 "univpll_d4_d2",
640 "univpll_d6"
641};
642
643static const char * const sflash_parents[] = {
644 "clk26m",
645 "mainpll_d7_d8",
646 "univpll_d6_d8",
647 "univpll_d5_d8"
648};
649
650static const char * const apll_i2s0_m_parents[] = {
651 "aud_1_sel",
652 "aud_2_sel"
653};
654
655static const char * const apll_i2s1_m_parents[] = {
656 "aud_1_sel",
657 "aud_2_sel"
658};
659
660static const char * const apll_i2s2_m_parents[] = {
661 "aud_1_sel",
662 "aud_2_sel"
663};
664
665static const char * const apll_i2s3_m_parents[] = {
666 "aud_1_sel",
667 "aud_2_sel"
668};
669
670static const char * const apll_i2s4_m_parents[] = {
671 "aud_1_sel",
672 "aud_2_sel"
673};
674
675static const char * const apll_i2s5_m_parents[] = {
676 "aud_1_sel",
677 "aud_2_sel"
678};
679
680static const char * const apll_i2s6_m_parents[] = {
681 "aud_1_sel",
682 "aud_2_sel"
683};
684
685static const char * const apll_i2s7_m_parents[] = {
686 "aud_1_sel",
687 "aud_2_sel"
688};
689
690static const char * const apll_i2s8_m_parents[] = {
691 "aud_1_sel",
692 "aud_2_sel"
693};
694
695static const char * const apll_i2s9_m_parents[] = {
696 "aud_1_sel",
697 "aud_2_sel"
698};
699
700
701
702
703
704
705
706static const struct mtk_mux top_mtk_muxes[] = {
707
708 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
709 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
710 CLK_IS_CRITICAL),
711 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
712 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
713 CLK_IS_CRITICAL),
714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
715 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
716 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
717 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
718 CLK_IS_CRITICAL),
719
720 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
721 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
722 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
723 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
724 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
725 img1_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
726 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
727 img2_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
728
729 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
730 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
731 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
732 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9),
733 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
734 cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
735 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
736 ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
737
738 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
739 dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
740 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
741 mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
742 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
743 mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
744 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
745 camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
746
747 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
748 camtg2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
749 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
750 camtg3_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
751 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
752 camtg4_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
753 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
754 camtg5_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
755
756 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel",
757 camtg6_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
758 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
759 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
760 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
761 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
762 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
763 msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27),
764
765 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
766 msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28),
767 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
768 msdc30_1_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29),
769 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
770 msdc30_2_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30),
771 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
772 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
773
774 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
775 aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1),
776 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
777 pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2),
778 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
779 atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3),
780
781 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
782 dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5),
783 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel",
784 scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6),
785 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
786 disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7),
787 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
788 usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8),
789
790 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
791 ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9),
792 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
793 i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10),
794 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
795 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11),
796 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
797 seninf1_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
798
799 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
800 seninf2_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
801 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
802 seninf3_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
803 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
804 tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15),
805 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
806 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16),
807
808 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
809 aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17),
810 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
811 aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18),
812 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
813 aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19),
814 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
815 ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20),
816
817 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
818 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21),
819 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
820 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22),
821 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
822 adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23),
823 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel",
824 dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24),
825
826 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
827 venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25),
828 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
829 vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26),
830 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
831 camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27),
832 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
833 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
834
835 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
836 audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29),
837 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel",
838 spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30),
839 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
840 aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
841
842 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
843 sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
844};
845
846static struct mtk_composite top_muxes[] = {
847
848 MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s0_m_parents, 0x320, 16, 1),
849 MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s1_m_parents, 0x320, 17, 1),
850 MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s2_m_parents, 0x320, 18, 1),
851 MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s3_m_parents, 0x320, 19, 1),
852 MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s4_m_parents, 0x320, 20, 1),
853 MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s5_m_parents, 0x320, 21, 1),
854 MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s6_m_parents, 0x320, 22, 1),
855 MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s7_m_parents, 0x320, 23, 1),
856 MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s8_m_parents, 0x320, 24, 1),
857 MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s9_m_parents, 0x320, 25, 1),
858};
859
860static const struct mtk_composite top_adj_divs[] = {
861 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
862 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8),
863 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16),
864 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24),
865 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
866 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8),
867 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
868 DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24),
869 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0),
870 DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8),
871 DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16),
872};
873
874static const struct mtk_gate_regs apmixed_cg_regs = {
875 .set_ofs = 0x14,
876 .clr_ofs = 0x14,
877 .sta_ofs = 0x14,
878};
879
880#define GATE_APMIXED(_id, _name, _parent, _shift) \
881 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
882
883static const struct mtk_gate apmixed_clks[] = {
884 GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16),
885};
886
887static const struct mtk_gate_regs infra0_cg_regs = {
888 .set_ofs = 0x80,
889 .clr_ofs = 0x84,
890 .sta_ofs = 0x90,
891};
892
893static const struct mtk_gate_regs infra1_cg_regs = {
894 .set_ofs = 0x88,
895 .clr_ofs = 0x8c,
896 .sta_ofs = 0x94,
897};
898
899static const struct mtk_gate_regs infra2_cg_regs = {
900 .set_ofs = 0xa4,
901 .clr_ofs = 0xa8,
902 .sta_ofs = 0xac,
903};
904
905static const struct mtk_gate_regs infra3_cg_regs = {
906 .set_ofs = 0xc0,
907 .clr_ofs = 0xc4,
908 .sta_ofs = 0xc8,
909};
910
911static const struct mtk_gate_regs infra4_cg_regs = {
912 .set_ofs = 0xd0,
913 .clr_ofs = 0xd4,
914 .sta_ofs = 0xd8,
915};
916
917static const struct mtk_gate_regs infra5_cg_regs = {
918 .set_ofs = 0xe0,
919 .clr_ofs = 0xe4,
920 .sta_ofs = 0xe8,
921};
922
923#define GATE_INFRA0(_id, _name, _parent, _shift) \
924 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
925
926#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \
927 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
928 &mtk_clk_gate_ops_setclr, _flag)
929
930#define GATE_INFRA1(_id, _name, _parent, _shift) \
931 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
932
933#define GATE_INFRA2(_id, _name, _parent, _shift) \
934 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
935
936#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \
937 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \
938 &mtk_clk_gate_ops_setclr, _flag)
939
940#define GATE_INFRA3(_id, _name, _parent, _shift) \
941 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
942
943#define GATE_INFRA4(_id, _name, _parent, _shift) \
944 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
945
946#define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \
947 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \
948 &mtk_clk_gate_ops_setclr, _flag)
949
950#define GATE_INFRA5(_id, _name, _parent, _shift) \
951 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
952
953
954
955
956
957
958static const struct mtk_gate infra_clks[] = {
959
960 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0),
961 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1),
962 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2),
963 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3),
964 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
965 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
966 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
967 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
968 GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
969 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
970 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
971 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12),
972 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
973 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
974 GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15),
975 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16),
976 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17),
977 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18),
978 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19),
979 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21),
980 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
981 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
982 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
983 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
984 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
985 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28),
986 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
987
988 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1),
989 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2),
990 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4),
991 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5),
992 GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6),
993 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
994 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
995 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
996 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
997 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12),
998 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13),
999 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14),
1000 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15),
1001 GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16),
1002 GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17),
1003 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18),
1004 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19),
1005 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL),
1006 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
1007 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24),
1008 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
1009 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
1010 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27),
1011 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28),
1012 GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29),
1013 GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30),
1014 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
1015
1016 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0),
1017 GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1),
1018 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2),
1019 GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3),
1020 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4),
1021 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5),
1022 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6),
1023 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7),
1024 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9),
1025 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10),
1026 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11),
1027 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12),
1028 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13),
1029 GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14),
1030 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
1031 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
1032 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
1033 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
1034 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21),
1035 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22),
1036 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23),
1037 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24),
1038 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25),
1039 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26),
1040 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27),
1041 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28),
1042 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29),
1043 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30),
1044 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31),
1045
1046 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
1047 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
1048 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
1049 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
1050 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
1051 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7),
1052 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8),
1053 GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9),
1054 GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10),
1055 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11),
1056 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14),
1057 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15),
1058 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16),
1059 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17),
1060 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18),
1061 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19),
1062 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20),
1063 GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21),
1064 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22),
1065 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23),
1066 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24),
1067 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25,
1068 CLK_IS_CRITICAL),
1069 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26),
1070 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27),
1071 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28),
1072 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29),
1073 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30),
1074 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31),
1075
1076 GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31),
1077
1078 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL),
1079 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL),
1080 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2),
1081 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3),
1082 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4),
1083 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5),
1084 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6),
1085 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30),
1086 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31),
1087};
1088
1089static const struct mtk_gate_regs peri_cg_regs = {
1090 .set_ofs = 0x20c,
1091 .clr_ofs = 0x20c,
1092 .sta_ofs = 0x20c,
1093};
1094
1095#define GATE_PERI(_id, _name, _parent, _shift) \
1096 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1097
1098static const struct mtk_gate peri_clks[] = {
1099 GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31),
1100};
1101
1102static const struct mtk_gate_regs top_cg_regs = {
1103 .set_ofs = 0x150,
1104 .clr_ofs = 0x150,
1105 .sta_ofs = 0x150,
1106};
1107
1108#define GATE_TOP(_id, _name, _parent, _shift) \
1109 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1110
1111static const struct mtk_gate top_clks[] = {
1112 GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24),
1113 GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
1114};
1115
1116#define MT8192_PLL_FMAX (3800UL * MHZ)
1117#define MT8192_PLL_FMIN (1500UL * MHZ)
1118#define MT8192_INTEGER_BITS 8
1119
1120#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1121 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1122 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1123 _pcw_reg, _pcw_shift, _pcw_chg_reg, \
1124 _en_reg, _pll_en_bit) { \
1125 .id = _id, \
1126 .name = _name, \
1127 .reg = _reg, \
1128 .pwr_reg = _pwr_reg, \
1129 .en_mask = _en_mask, \
1130 .flags = _flags, \
1131 .rst_bar_mask = _rst_bar_mask, \
1132 .fmax = MT8192_PLL_FMAX, \
1133 .fmin = MT8192_PLL_FMIN, \
1134 .pcwbits = _pcwbits, \
1135 .pcwibits = MT8192_INTEGER_BITS, \
1136 .pd_reg = _pd_reg, \
1137 .pd_shift = _pd_shift, \
1138 .tuner_reg = _tuner_reg, \
1139 .tuner_en_reg = _tuner_en_reg, \
1140 .tuner_en_bit = _tuner_en_bit, \
1141 .pcw_reg = _pcw_reg, \
1142 .pcw_shift = _pcw_shift, \
1143 .pcw_chg_reg = _pcw_chg_reg, \
1144 .en_reg = _en_reg, \
1145 .pll_en_bit = _pll_en_bit, \
1146 }
1147
1148#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1149 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1150 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1151 _pcw_reg, _pcw_shift) \
1152 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1153 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1154 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1155 _pcw_reg, _pcw_shift, 0, 0, 0)
1156
1157static const struct mtk_pll_data plls[] = {
1158 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000,
1159 HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0),
1160 PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000,
1161 HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0),
1162 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000,
1163 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2),
1164 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000,
1165 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0),
1166 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000,
1167 HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0),
1168 PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000,
1169 HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0),
1170 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000,
1171 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0),
1172 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000,
1173 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0),
1174 PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000,
1175 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
1176 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000,
1177 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
1178};
1179
1180static struct clk_onecell_data *top_clk_data;
1181
1182static void clk_mt8192_top_init_early(struct device_node *node)
1183{
1184 int i;
1185
1186 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1187 if (!top_clk_data)
1188 return;
1189
1190 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1191 top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
1192
1193 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
1194
1195 of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1196}
1197
1198CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen",
1199 clk_mt8192_top_init_early);
1200
1201static int clk_mt8192_top_probe(struct platform_device *pdev)
1202{
1203 struct device_node *node = pdev->dev.of_node;
1204 int r;
1205 void __iomem *base;
1206
1207 base = devm_platform_ioremap_resource(pdev, 0);
1208 if (IS_ERR(base))
1209 return PTR_ERR(base);
1210
1211 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1212 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
1213 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1214 mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, &mt8192_clk_lock,
1215 top_clk_data);
1216 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8192_clk_lock,
1217 top_clk_data);
1218 mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8192_clk_lock,
1219 top_clk_data);
1220 r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1221 if (r)
1222 return r;
1223
1224 return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1225}
1226
1227static int clk_mt8192_infra_probe(struct platform_device *pdev)
1228{
1229 struct clk_onecell_data *clk_data;
1230 struct device_node *node = pdev->dev.of_node;
1231 int r;
1232
1233 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1234 if (!clk_data)
1235 return -ENOMEM;
1236
1237 r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data);
1238 if (r)
1239 return r;
1240
1241 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1242}
1243
1244static int clk_mt8192_peri_probe(struct platform_device *pdev)
1245{
1246 struct clk_onecell_data *clk_data;
1247 struct device_node *node = pdev->dev.of_node;
1248 int r;
1249
1250 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1251 if (!clk_data)
1252 return -ENOMEM;
1253
1254 r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data);
1255 if (r)
1256 return r;
1257
1258 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1259}
1260
1261static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
1262{
1263 struct clk_onecell_data *clk_data;
1264 struct device_node *node = pdev->dev.of_node;
1265 int r;
1266
1267 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1268 if (!clk_data)
1269 return -ENOMEM;
1270
1271 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1272 r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
1273 if (r)
1274 return r;
1275
1276 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1277}
1278
1279static const struct of_device_id of_match_clk_mt8192[] = {
1280 {
1281 .compatible = "mediatek,mt8192-apmixedsys",
1282 .data = clk_mt8192_apmixed_probe,
1283 }, {
1284 .compatible = "mediatek,mt8192-topckgen",
1285 .data = clk_mt8192_top_probe,
1286 }, {
1287 .compatible = "mediatek,mt8192-infracfg",
1288 .data = clk_mt8192_infra_probe,
1289 }, {
1290 .compatible = "mediatek,mt8192-pericfg",
1291 .data = clk_mt8192_peri_probe,
1292 }, {
1293
1294 }
1295};
1296
1297static int clk_mt8192_probe(struct platform_device *pdev)
1298{
1299 int (*clk_probe)(struct platform_device *pdev);
1300 int r;
1301
1302 clk_probe = of_device_get_match_data(&pdev->dev);
1303 if (!clk_probe)
1304 return -EINVAL;
1305
1306 r = clk_probe(pdev);
1307 if (r)
1308 dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r);
1309
1310 return r;
1311}
1312
1313static struct platform_driver clk_mt8192_drv = {
1314 .probe = clk_mt8192_probe,
1315 .driver = {
1316 .name = "clk-mt8192",
1317 .of_match_table = of_match_clk_mt8192,
1318 },
1319};
1320
1321static int __init clk_mt8192_init(void)
1322{
1323 return platform_driver_register(&clk_mt8192_drv);
1324}
1325
1326arch_initcall(clk_mt8192_init);
1327
