LXR linux/drivers/clk/mediatek/clk-mt8516-aud.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2019 MediaTek Inc.
   4 * Author: James Liao <jamesjj.liao@mediatek.com>
   5 *         Fabien Parent <fparent@baylibre.com>
   6 */
   7
   8#include <linux/clk-provider.h>
   9#include <linux/of.h>
  10#include <linux/of_address.h>
  11#include <linux/of_device.h>
  12#include <linux/platform_device.h>
  13
  14#include "clk-mtk.h"
  15#include "clk-gate.h"
  16
  17#include <dt-bindings/clock/mt8516-clk.h>
  18
  19static const struct mtk_gate_regs aud_cg_regs = {
  20        .set_ofs = 0x0,
  21        .clr_ofs = 0x0,
  22        .sta_ofs = 0x0,
  23};
  24
  25#define GATE_AUD(_id, _name, _parent, _shift) { \
  26                .id = _id,                      \
  27                .name = _name,                  \
  28                .parent_name = _parent,         \
  29                .regs = &aud_cg_regs,           \
  30                .shift = _shift,                \
  31                .ops = &mtk_clk_gate_ops_no_setclr,             \
  32        }
  33
  34static const struct mtk_gate aud_clks[] __initconst = {
  35        GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
  36        GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
  37        GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
  38        GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
  39        GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
  40        GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
  41        GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
  42        GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
  43        GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
  44        GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
  45        GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
  46        GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
  47        GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
  48};
  49
  50static void __init mtk_audsys_init(struct device_node *node)
  51{
  52        struct clk_onecell_data *clk_data;
  53        int r;
  54
  55        clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
  56
  57        mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
  58
  59        r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  60        if (r)
  61                pr_err("%s(): could not register clock provider: %d\n",
  62                        __func__, r);
  63
  64}
  65CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);
  66