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8#include <linux/delay.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/slab.h>
12#include <linux/mfd/syscon.h>
13
14#include "clk-mtk.h"
15#include "clk-gate.h"
16
17#include <dt-bindings/clock/mt8516-clk.h>
18
19static DEFINE_SPINLOCK(mt8516_clk_lock);
20
21static const struct mtk_fixed_clk fixed_clks[] __initconst = {
22 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
23 FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
24 FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
25};
26
27static const struct mtk_fixed_factor top_divs[] __initconst = {
28 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
29 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
30 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
31 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
32 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
33 FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
34 FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
35 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
36 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
37 FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
38 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
39 FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
40 FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
41 FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
42 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
43 FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
44 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
45 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
46 FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
47 FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
48 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
49 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
50 FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
51 FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
52 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
53 FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
54 FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
55 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
56 FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
57 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
58 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
59 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
60 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
61 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
62 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
63 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
64 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
65 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
66 FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
67 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
68 FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
69 FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
70 FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
71};
72
73static const char * const uart0_parents[] __initconst = {
74 "clk26m_ck",
75 "univpll_d24"
76};
77
78static const char * const ahb_infra_parents[] __initconst = {
79 "clk_null",
80 "clk26m_ck",
81 "mainpll_d11",
82 "clk_null",
83 "mainpll_d12",
84 "clk_null",
85 "clk_null",
86 "clk_null",
87 "clk_null",
88 "clk_null",
89 "clk_null",
90 "clk_null",
91 "mainpll_d10"
92};
93
94static const char * const msdc0_parents[] __initconst = {
95 "clk26m_ck",
96 "univpll_d6",
97 "mainpll_d8",
98 "univpll_d8",
99 "mainpll_d16",
100 "mmpll_200m",
101 "mainpll_d12",
102 "mmpll_d2"
103};
104
105static const char * const uart1_parents[] __initconst = {
106 "clk26m_ck",
107 "univpll_d24"
108};
109
110static const char * const msdc1_parents[] __initconst = {
111 "clk26m_ck",
112 "univpll_d6",
113 "mainpll_d8",
114 "univpll_d8",
115 "mainpll_d16",
116 "mmpll_200m",
117 "mainpll_d12",
118 "mmpll_d2"
119};
120
121static const char * const pmicspi_parents[] __initconst = {
122 "univpll_d20",
123 "usb_phy48m_ck",
124 "univpll_d16",
125 "clk26m_ck"
126};
127
128static const char * const qaxi_aud26m_parents[] __initconst = {
129 "clk26m_ck",
130 "ahb_infra_sel"
131};
132
133static const char * const aud_intbus_parents[] __initconst = {
134 "clk_null",
135 "clk26m_ck",
136 "mainpll_d22",
137 "clk_null",
138 "mainpll_d11"
139};
140
141static const char * const nfi2x_pad_parents[] __initconst = {
142 "clk_null",
143 "clk_null",
144 "clk_null",
145 "clk_null",
146 "clk_null",
147 "clk_null",
148 "clk_null",
149 "clk_null",
150 "clk26m_ck",
151 "clk_null",
152 "clk_null",
153 "clk_null",
154 "clk_null",
155 "clk_null",
156 "clk_null",
157 "clk_null",
158 "clk_null",
159 "mainpll_d12",
160 "mainpll_d8",
161 "clk_null",
162 "mainpll_d6",
163 "clk_null",
164 "clk_null",
165 "clk_null",
166 "clk_null",
167 "clk_null",
168 "clk_null",
169 "clk_null",
170 "clk_null",
171 "clk_null",
172 "clk_null",
173 "clk_null",
174 "mainpll_d4",
175 "clk_null",
176 "clk_null",
177 "clk_null",
178 "clk_null",
179 "clk_null",
180 "clk_null",
181 "clk_null",
182 "clk_null",
183 "clk_null",
184 "clk_null",
185 "clk_null",
186 "clk_null",
187 "clk_null",
188 "clk_null",
189 "clk_null",
190 "clk_null",
191 "clk_null",
192 "clk_null",
193 "clk_null",
194 "clk_null",
195 "clk_null",
196 "clk_null",
197 "clk_null",
198 "clk_null",
199 "clk_null",
200 "clk_null",
201 "clk_null",
202 "clk_null",
203 "clk_null",
204 "clk_null",
205 "clk_null",
206 "clk_null",
207 "clk_null",
208 "clk_null",
209 "clk_null",
210 "clk_null",
211 "clk_null",
212 "clk_null",
213 "clk_null",
214 "clk_null",
215 "clk_null",
216 "clk_null",
217 "clk_null",
218 "clk_null",
219 "clk_null",
220 "clk_null",
221 "clk_null",
222 "clk_null",
223 "mainpll_d10",
224 "mainpll_d7",
225 "clk_null",
226 "mainpll_d5"
227};
228
229static const char * const nfi1x_pad_parents[] __initconst = {
230 "ahb_infra_sel",
231 "nfi1x_ck"
232};
233
234static const char * const usb_78m_parents[] __initconst = {
235 "clk_null",
236 "clk26m_ck",
237 "univpll_d16",
238 "clk_null",
239 "mainpll_d20"
240};
241
242static const char * const spinor_parents[] __initconst = {
243 "clk26m_d2",
244 "clk26m_ck",
245 "mainpll_d40",
246 "univpll_d24",
247 "univpll_d20",
248 "mainpll_d20",
249 "mainpll_d16",
250 "univpll_d12"
251};
252
253static const char * const msdc2_parents[] __initconst = {
254 "clk26m_ck",
255 "univpll_d6",
256 "mainpll_d8",
257 "univpll_d8",
258 "mainpll_d16",
259 "mmpll_200m",
260 "mainpll_d12",
261 "mmpll_d2"
262};
263
264static const char * const eth_parents[] __initconst = {
265 "clk26m_ck",
266 "mainpll_d40",
267 "univpll_d24",
268 "univpll_d20",
269 "mainpll_d20"
270};
271
272static const char * const aud1_parents[] __initconst = {
273 "clk26m_ck",
274 "apll1_ck"
275};
276
277static const char * const aud2_parents[] __initconst = {
278 "clk26m_ck",
279 "apll2_ck"
280};
281
282static const char * const aud_engen1_parents[] __initconst = {
283 "clk26m_ck",
284 "rg_apll1_d2_en",
285 "rg_apll1_d4_en",
286 "rg_apll1_d8_en"
287};
288
289static const char * const aud_engen2_parents[] __initconst = {
290 "clk26m_ck",
291 "rg_apll2_d2_en",
292 "rg_apll2_d4_en",
293 "rg_apll2_d8_en"
294};
295
296static const char * const i2c_parents[] __initconst = {
297 "clk26m_ck",
298 "univpll_d20",
299 "univpll_d16",
300 "univpll_d12"
301};
302
303static const char * const aud_i2s0_m_parents[] __initconst = {
304 "rg_aud1",
305 "rg_aud2"
306};
307
308static const char * const pwm_parents[] __initconst = {
309 "clk26m_ck",
310 "univpll_d12"
311};
312
313static const char * const spi_parents[] __initconst = {
314 "clk26m_ck",
315 "univpll_d12",
316 "univpll_d8",
317 "univpll_d6"
318};
319
320static const char * const aud_spdifin_parents[] __initconst = {
321 "clk26m_ck",
322 "univpll_d2"
323};
324
325static const char * const uart2_parents[] __initconst = {
326 "clk26m_ck",
327 "univpll_d24"
328};
329
330static const char * const bsi_parents[] __initconst = {
331 "clk26m_ck",
332 "mainpll_d10",
333 "mainpll_d12",
334 "mainpll_d20"
335};
336
337static const char * const dbg_atclk_parents[] __initconst = {
338 "clk_null",
339 "clk26m_ck",
340 "mainpll_d5",
341 "clk_null",
342 "univpll_d5"
343};
344
345static const char * const csw_nfiecc_parents[] __initconst = {
346 "clk_null",
347 "mainpll_d7",
348 "mainpll_d6",
349 "clk_null",
350 "mainpll_d5"
351};
352
353static const char * const nfiecc_parents[] __initconst = {
354 "clk_null",
355 "nfi2x_pad_sel",
356 "mainpll_d4",
357 "clk_null",
358 "csw_nfiecc_sel"
359};
360
361static struct mtk_composite top_muxes[] __initdata = {
362
363 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
364 0x000, 0, 1),
365 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
366 0x000, 4, 4),
367 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
368 0x000, 11, 3),
369 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
370 0x000, 19, 1),
371 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
372 0x000, 20, 3),
373 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
374 0x000, 24, 2),
375 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
376 0x000, 26, 1),
377 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
378 0x000, 27, 3),
379
380 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
381 0x004, 0, 7),
382 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
383 0x004, 7, 1),
384 MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
385 0x004, 20, 3),
386
387 MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
388 0x040, 0, 3),
389 MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
390 0x040, 3, 3),
391 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
392 0x040, 6, 3),
393 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
394 0x040, 22, 1),
395 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
396 0x040, 23, 1),
397 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
398 0x040, 24, 2),
399 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
400 0x040, 26, 2),
401 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
402 0x040, 28, 2),
403
404 MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
405 0x044, 12, 1),
406 MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
407 0x044, 13, 1),
408 MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
409 0x044, 14, 1),
410 MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
411 0x044, 15, 1),
412 MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
413 0x044, 16, 1),
414 MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
415 0x044, 17, 1),
416 MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
417 0x044, 18, 1),
418
419 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
420 0x07c, 0, 1),
421 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
422 0x07c, 1, 2),
423 MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
424 0x07c, 3, 1),
425 MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
426 0x07c, 4, 1),
427 MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
428 0x07c, 5, 2),
429 MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
430 0x07c, 7, 3),
431 MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
432 0x07c, 10, 3),
433 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
434 0x07c, 13, 3),
435};
436
437static const char * const ifr_mux1_parents[] __initconst = {
438 "clk26m_ck",
439 "armpll",
440 "univpll",
441 "mainpll_d2"
442};
443
444static const char * const ifr_eth_25m_parents[] __initconst = {
445 "eth_d2_ck",
446 "rg_eth"
447};
448
449static const char * const ifr_i2c0_parents[] __initconst = {
450 "ahb_infra_d2",
451 "rg_i2c"
452};
453
454static const struct mtk_composite ifr_muxes[] __initconst = {
455 MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
456 2, 2),
457 MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
458 0, 1),
459 MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
460 1, 1),
461 MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
462 2, 1),
463 MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
464 3, 1),
465};
466
467#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
468 .id = _id, \
469 .name = _name, \
470 .parent_name = _parent, \
471 .div_reg = _reg, \
472 .div_shift = _shift, \
473 .div_width = _width, \
474}
475
476static const struct mtk_clk_divider top_adj_divs[] = {
477 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
478 0x0048, 0, 8),
479 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
480 0x0048, 8, 8),
481 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
482 0x0048, 16, 8),
483 DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
484 0x0048, 24, 8),
485 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
486 0x004c, 0, 8),
487 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
488 0x004c, 8, 8),
489 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
490 0x004c, 16, 8),
491 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
492 0x004c, 24, 8),
493 DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
494 0x0078, 0, 8),
495};
496
497static const struct mtk_gate_regs top1_cg_regs = {
498 .set_ofs = 0x54,
499 .clr_ofs = 0x84,
500 .sta_ofs = 0x24,
501};
502
503static const struct mtk_gate_regs top2_cg_regs = {
504 .set_ofs = 0x6c,
505 .clr_ofs = 0x9c,
506 .sta_ofs = 0x3c,
507};
508
509static const struct mtk_gate_regs top3_cg_regs = {
510 .set_ofs = 0xa0,
511 .clr_ofs = 0xb0,
512 .sta_ofs = 0x70,
513};
514
515static const struct mtk_gate_regs top4_cg_regs = {
516 .set_ofs = 0xa4,
517 .clr_ofs = 0xb4,
518 .sta_ofs = 0x74,
519};
520
521static const struct mtk_gate_regs top5_cg_regs = {
522 .set_ofs = 0x44,
523 .clr_ofs = 0x44,
524 .sta_ofs = 0x44,
525};
526
527#define GATE_TOP1(_id, _name, _parent, _shift) { \
528 .id = _id, \
529 .name = _name, \
530 .parent_name = _parent, \
531 .regs = &top1_cg_regs, \
532 .shift = _shift, \
533 .ops = &mtk_clk_gate_ops_setclr, \
534 }
535
536#define GATE_TOP2(_id, _name, _parent, _shift) { \
537 .id = _id, \
538 .name = _name, \
539 .parent_name = _parent, \
540 .regs = &top2_cg_regs, \
541 .shift = _shift, \
542 .ops = &mtk_clk_gate_ops_setclr, \
543 }
544
545#define GATE_TOP2_I(_id, _name, _parent, _shift) { \
546 .id = _id, \
547 .name = _name, \
548 .parent_name = _parent, \
549 .regs = &top2_cg_regs, \
550 .shift = _shift, \
551 .ops = &mtk_clk_gate_ops_setclr_inv, \
552 }
553
554#define GATE_TOP3(_id, _name, _parent, _shift) { \
555 .id = _id, \
556 .name = _name, \
557 .parent_name = _parent, \
558 .regs = &top3_cg_regs, \
559 .shift = _shift, \
560 .ops = &mtk_clk_gate_ops_setclr, \
561 }
562
563#define GATE_TOP4_I(_id, _name, _parent, _shift) { \
564 .id = _id, \
565 .name = _name, \
566 .parent_name = _parent, \
567 .regs = &top4_cg_regs, \
568 .shift = _shift, \
569 .ops = &mtk_clk_gate_ops_setclr_inv, \
570 }
571
572#define GATE_TOP5(_id, _name, _parent, _shift) { \
573 .id = _id, \
574 .name = _name, \
575 .parent_name = _parent, \
576 .regs = &top5_cg_regs, \
577 .shift = _shift, \
578 .ops = &mtk_clk_gate_ops_no_setclr, \
579 }
580
581static const struct mtk_gate top_clks[] __initconst = {
582
583 GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
584 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
585 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
586 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
587 GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
588 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
589 GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
590 GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
591 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
592 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
593 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
594 GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
595 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
596 GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
597 GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
598 GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
599 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
600 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
601 GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
602 GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
603 GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
604 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
605 GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
606 GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
607 GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
608 GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
609 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
610 GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
611 GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
612 GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
613
614 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
615 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
616 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
617 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
618 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
619 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
620 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
621 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
622 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
623 GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
624 GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
625 GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
626 GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
627 GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
628 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
629 15),
630 GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
631 GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
632 GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
633 GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
634 GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
635 GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
636 GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
637 GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
638 GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
639 GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
640 GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
641 GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
642
643 GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
644 GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
645 GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
646 GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
647 GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
648 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
649 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
650 GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
651 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
652 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
653 14),
654 GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
655 GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
656 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
657 GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
658
659 GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
660 GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
661 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
662 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
663 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
664 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
665
666 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
667 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
668 GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
669 GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
670 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
671 GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
672 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
673 GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
674 GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
675};
676
677static void __init mtk_topckgen_init(struct device_node *node)
678{
679 struct clk_onecell_data *clk_data;
680 int r;
681 void __iomem *base;
682
683 base = of_iomap(node, 0);
684 if (!base) {
685 pr_err("%s(): ioremap failed\n", __func__);
686 return;
687 }
688
689 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
690
691 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
692 clk_data);
693 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
694
695 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
696 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
697 &mt8516_clk_lock, clk_data);
698 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
699 base, &mt8516_clk_lock, clk_data);
700
701 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
702 if (r)
703 pr_err("%s(): could not register clock provider: %d\n",
704 __func__, r);
705}
706CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
707
708static void __init mtk_infracfg_init(struct device_node *node)
709{
710 struct clk_onecell_data *clk_data;
711 int r;
712 void __iomem *base;
713
714 base = of_iomap(node, 0);
715 if (!base) {
716 pr_err("%s(): ioremap failed\n", __func__);
717 return;
718 }
719
720 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
721
722 mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
723 &mt8516_clk_lock, clk_data);
724
725 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
726 if (r)
727 pr_err("%s(): could not register clock provider: %d\n",
728 __func__, r);
729}
730CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init);
731
732#define MT8516_PLL_FMAX (1502UL * MHZ)
733
734#define CON0_MT8516_RST_BAR BIT(27)
735
736#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
737 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
738 _pcw_shift, _div_table) { \
739 .id = _id, \
740 .name = _name, \
741 .reg = _reg, \
742 .pwr_reg = _pwr_reg, \
743 .en_mask = _en_mask, \
744 .flags = _flags, \
745 .rst_bar_mask = CON0_MT8516_RST_BAR, \
746 .fmax = MT8516_PLL_FMAX, \
747 .pcwbits = _pcwbits, \
748 .pd_reg = _pd_reg, \
749 .pd_shift = _pd_shift, \
750 .tuner_reg = _tuner_reg, \
751 .pcw_reg = _pcw_reg, \
752 .pcw_shift = _pcw_shift, \
753 .div_table = _div_table, \
754 }
755
756#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
757 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
758 _pcw_shift) \
759 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
760 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
761 NULL)
762
763static const struct mtk_pll_div_table mmpll_div_table[] = {
764 { .div = 0, .freq = MT8516_PLL_FMAX },
765 { .div = 1, .freq = 1000000000 },
766 { .div = 2, .freq = 604500000 },
767 { .div = 3, .freq = 253500000 },
768 { .div = 4, .freq = 126750000 },
769 { }
770};
771
772static const struct mtk_pll_data plls[] = {
773 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
774 21, 0x0104, 24, 0, 0x0104, 0),
775 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
776 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
777 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
778 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
779 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
780 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
781 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
782 31, 0x0180, 1, 0x0194, 0x0184, 0),
783 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
784 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
785};
786
787static void __init mtk_apmixedsys_init(struct device_node *node)
788{
789 struct clk_onecell_data *clk_data;
790 void __iomem *base;
791 int r;
792
793 base = of_iomap(node, 0);
794 if (!base) {
795 pr_err("%s(): ioremap failed\n", __func__);
796 return;
797 }
798
799 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
800
801 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
802
803 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
804 if (r)
805 pr_err("%s(): could not register clock provider: %d\n",
806 __func__, r);
807
808}
809CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys",
810 mtk_apmixedsys_init);
811
