LXR linux/drivers/clk/meson/vid-pll-div.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2018 BayLibre, SAS.
   4 * Author: Neil Armstrong <narmstrong@baylibre.com>
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/module.h>
   9
  10#include "clk-regmap.h"
  11#include "vid-pll-div.h"
  12
  13static inline struct meson_vid_pll_div_data *
  14meson_vid_pll_div_data(struct clk_regmap *clk)
  15{
  16        return (struct meson_vid_pll_div_data *)clk->data;
  17}
  18
  19/*
  20 * This vid_pll divided is a fully programmable fractionnal divider to
  21 * achieve complex video clock rates.
  22 *
  23 * Here are provided the commonly used fraction values provided by Amlogic.
  24 */
  25
  26struct vid_pll_div {
  27        unsigned int shift_val;
  28        unsigned int shift_sel;
  29        unsigned int divider;
  30        unsigned int multiplier;
  31};
  32
  33#define VID_PLL_DIV(_val, _sel, _ft, _fb)                               \
  34        {                                                               \
  35                .shift_val = (_val),                                    \
  36                .shift_sel = (_sel),                                    \
  37                .divider = (_ft),                                       \
  38                .multiplier = (_fb),                                    \
  39        }
  40
  41static const struct vid_pll_div vid_pll_div_table[] = {
  42        VID_PLL_DIV(0x0aaa, 0, 2, 1),   /* 2/1  => /2 */
  43        VID_PLL_DIV(0x5294, 2, 5, 2),   /* 5/2  => /2.5 */
  44        VID_PLL_DIV(0x0db6, 0, 3, 1),   /* 3/1  => /3 */
  45        VID_PLL_DIV(0x36cc, 1, 7, 2),   /* 7/2  => /3.5 */
  46        VID_PLL_DIV(0x6666, 2, 15, 4),  /* 15/4 => /3.75 */
  47        VID_PLL_DIV(0x0ccc, 0, 4, 1),   /* 4/1  => /4 */
  48        VID_PLL_DIV(0x739c, 2, 5, 1),   /* 5/1  => /5 */
  49        VID_PLL_DIV(0x0e38, 0, 6, 1),   /* 6/1  => /6 */
  50        VID_PLL_DIV(0x0000, 3, 25, 4),  /* 25/4 => /6.25 */
  51        VID_PLL_DIV(0x3c78, 1, 7, 1),   /* 7/1  => /7 */
  52        VID_PLL_DIV(0x78f0, 2, 15, 2),  /* 15/2 => /7.5 */
  53        VID_PLL_DIV(0x0fc0, 0, 12, 1),  /* 12/1 => /12 */
  54        VID_PLL_DIV(0x3f80, 1, 14, 1),  /* 14/1 => /14 */
  55        VID_PLL_DIV(0x7f80, 2, 15, 1),  /* 15/1 => /15 */
  56};
  57
  58#define to_meson_vid_pll_div(_hw) \
  59        container_of(_hw, struct meson_vid_pll_div, hw)
  60
  61static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
  62                                                unsigned int shift_sel)
  63{
  64        int i;
  65
  66        for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) {
  67                if (vid_pll_div_table[i].shift_val == shift_val &&
  68                    vid_pll_div_table[i].shift_sel == shift_sel)
  69                        return &vid_pll_div_table[i];
  70        }
  71
  72        return NULL;
  73}
  74
  75static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw,
  76                                                   unsigned long parent_rate)
  77{
  78        struct clk_regmap *clk = to_clk_regmap(hw);
  79        struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk);
  80        const struct vid_pll_div *div;
  81
  82        div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
  83                             meson_parm_read(clk->map, &pll_div->sel));
  84        if (!div || !div->divider) {
  85                pr_debug("%s: Invalid config value for vid_pll_div\n", __func__);
  86                return 0;
  87        }
  88
  89        return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
  90}
  91
  92const struct clk_ops meson_vid_pll_div_ro_ops = {
  93        .recalc_rate    = meson_vid_pll_div_recalc_rate,
  94};
  95EXPORT_SYMBOL_GPL(meson_vid_pll_div_ro_ops);
  96
  97MODULE_DESCRIPTION("Amlogic video pll divider driver");
  98MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
  99MODULE_LICENSE("GPL v2");
 100