1
2
3
4
5
6
7
8
9
10
11
12#include <linux/clk.h>
13#include <linux/clk/mmp.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/spinlock.h>
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20
21#include "clk.h"
22
23#define APBC_RTC 0x28
24#define APBC_TWSI0 0x2c
25#define APBC_KPC 0x30
26#define APBC_UART0 0x0
27#define APBC_UART1 0x4
28#define APBC_GPIO 0x8
29#define APBC_PWM0 0xc
30#define APBC_PWM1 0x10
31#define APBC_PWM2 0x14
32#define APBC_PWM3 0x18
33#define APBC_SSP0 0x81c
34#define APBC_SSP1 0x820
35#define APBC_SSP2 0x84c
36#define APBC_SSP3 0x858
37#define APBC_SSP4 0x85c
38#define APBC_TWSI1 0x6c
39#define APBC_UART2 0x70
40#define APMU_SDH0 0x54
41#define APMU_SDH1 0x58
42#define APMU_USB 0x5c
43#define APMU_DISP0 0x4c
44#define APMU_CCIC0 0x50
45#define APMU_DFC 0x60
46#define MPMU_UART_PLL 0x14
47
48static DEFINE_SPINLOCK(clk_lock);
49
50static struct mmp_clk_factor_masks uart_factor_masks = {
51 .factor = 2,
52 .num_mask = 0x1fff,
53 .den_mask = 0x1fff,
54 .num_shift = 16,
55 .den_shift = 0,
56};
57
58static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
59 {.num = 8125, .den = 1536},
60};
61
62static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
63static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
64static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
65static const char *disp_parent[] = {"pll1_2", "pll1_12"};
66static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
67static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
68
69void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
70 phys_addr_t apbc_phys)
71{
72 struct clk *clk;
73 struct clk *uart_pll;
74 void __iomem *mpmu_base;
75 void __iomem *apmu_base;
76 void __iomem *apbc_base;
77
78 mpmu_base = ioremap(mpmu_phys, SZ_4K);
79 if (!mpmu_base) {
80 pr_err("error to ioremap MPMU base\n");
81 return;
82 }
83
84 apmu_base = ioremap(apmu_phys, SZ_4K);
85 if (!apmu_base) {
86 pr_err("error to ioremap APMU base\n");
87 return;
88 }
89
90 apbc_base = ioremap(apbc_phys, SZ_4K);
91 if (!apbc_base) {
92 pr_err("error to ioremap APBC base\n");
93 return;
94 }
95
96 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
97 clk_register_clkdev(clk, "clk32", NULL);
98
99 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
100 clk_register_clkdev(clk, "vctcxo", NULL);
101
102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
103 clk_register_clkdev(clk, "pll1", NULL);
104
105 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
106 CLK_SET_RATE_PARENT, 1, 2);
107 clk_register_clkdev(clk, "pll1_2", NULL);
108
109 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
110 CLK_SET_RATE_PARENT, 1, 2);
111 clk_register_clkdev(clk, "pll1_4", NULL);
112
113 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
114 CLK_SET_RATE_PARENT, 1, 2);
115 clk_register_clkdev(clk, "pll1_8", NULL);
116
117 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
118 CLK_SET_RATE_PARENT, 1, 2);
119 clk_register_clkdev(clk, "pll1_16", NULL);
120
121 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
122 CLK_SET_RATE_PARENT, 1, 3);
123 clk_register_clkdev(clk, "pll1_6", NULL);
124
125 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
126 CLK_SET_RATE_PARENT, 1, 2);
127 clk_register_clkdev(clk, "pll1_12", NULL);
128
129 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
130 CLK_SET_RATE_PARENT, 1, 2);
131 clk_register_clkdev(clk, "pll1_24", NULL);
132
133 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
134 CLK_SET_RATE_PARENT, 1, 2);
135 clk_register_clkdev(clk, "pll1_48", NULL);
136
137 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
138 CLK_SET_RATE_PARENT, 1, 2);
139 clk_register_clkdev(clk, "pll1_96", NULL);
140
141 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
142 CLK_SET_RATE_PARENT, 1, 13);
143 clk_register_clkdev(clk, "pll1_13", NULL);
144
145 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
146 CLK_SET_RATE_PARENT, 2, 3);
147 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
148
149 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
150 CLK_SET_RATE_PARENT, 2, 3);
151 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
152
153 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
154 CLK_SET_RATE_PARENT, 3, 16);
155 clk_register_clkdev(clk, "pll1_3_16", NULL);
156
157 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
158 mpmu_base + MPMU_UART_PLL,
159 &uart_factor_masks, uart_factor_tbl,
160 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
161 clk_set_rate(uart_pll, 14745600);
162 clk_register_clkdev(uart_pll, "uart_pll", NULL);
163
164 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
165 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
166 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
167
168 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
169 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
170 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
171
172 clk = mmp_clk_register_apbc("gpio", "vctcxo",
173 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
174 clk_register_clkdev(clk, NULL, "mmp-gpio");
175
176 clk = mmp_clk_register_apbc("kpc", "clk32",
177 apbc_base + APBC_KPC, 10, 0, &clk_lock);
178 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
179
180 clk = mmp_clk_register_apbc("rtc", "clk32",
181 apbc_base + APBC_RTC, 10, 0, &clk_lock);
182 clk_register_clkdev(clk, NULL, "sa1100-rtc");
183
184 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
185 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
186 clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
187
188 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
189 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
190 clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
191
192 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
193 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
194 clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
195
196 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
197 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
198 clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
199
200 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
201 ARRAY_SIZE(uart_parent),
202 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
203 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
204 clk_set_parent(clk, uart_pll);
205 clk_register_clkdev(clk, "uart_mux.0", NULL);
206
207 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
208 apbc_base + APBC_UART0, 10, 0, &clk_lock);
209 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
210
211 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
212 ARRAY_SIZE(uart_parent),
213 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
214 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
215 clk_set_parent(clk, uart_pll);
216 clk_register_clkdev(clk, "uart_mux.1", NULL);
217
218 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
219 apbc_base + APBC_UART1, 10, 0, &clk_lock);
220 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
221
222 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
223 ARRAY_SIZE(uart_parent),
224 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
225 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
226 clk_set_parent(clk, uart_pll);
227 clk_register_clkdev(clk, "uart_mux.2", NULL);
228
229 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
230 apbc_base + APBC_UART2, 10, 0, &clk_lock);
231 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
232
233 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
234 ARRAY_SIZE(ssp_parent),
235 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
236 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
237 clk_register_clkdev(clk, "uart_mux.0", NULL);
238
239 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
240 10, 0, &clk_lock);
241 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
242
243 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
244 ARRAY_SIZE(ssp_parent),
245 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
246 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
247 clk_register_clkdev(clk, "ssp_mux.1", NULL);
248
249 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
250 10, 0, &clk_lock);
251 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
252
253 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
254 ARRAY_SIZE(ssp_parent),
255 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
256 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
257 clk_register_clkdev(clk, "ssp_mux.2", NULL);
258
259 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
260 10, 0, &clk_lock);
261 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
262
263 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
264 ARRAY_SIZE(ssp_parent),
265 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
266 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
267 clk_register_clkdev(clk, "ssp_mux.3", NULL);
268
269 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
270 10, 0, &clk_lock);
271 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
272
273 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
274 ARRAY_SIZE(ssp_parent),
275 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
276 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
277 clk_register_clkdev(clk, "ssp_mux.4", NULL);
278
279 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
280 10, 0, &clk_lock);
281 clk_register_clkdev(clk, NULL, "mmp-ssp.4");
282
283 clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
284 0x19b, &clk_lock);
285 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
286
287 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
288 ARRAY_SIZE(sdh_parent),
289 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
290 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
291 clk_register_clkdev(clk, "sdh0_mux", NULL);
292
293 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
294 0x1b, &clk_lock);
295 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
296
297 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
298 ARRAY_SIZE(sdh_parent),
299 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
300 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
301 clk_register_clkdev(clk, "sdh1_mux", NULL);
302
303 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
304 0x1b, &clk_lock);
305 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
306
307 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
308 0x9, &clk_lock);
309 clk_register_clkdev(clk, "usb_clk", NULL);
310
311 clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
312 0x12, &clk_lock);
313 clk_register_clkdev(clk, "sph_clk", NULL);
314
315 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
316 ARRAY_SIZE(disp_parent),
317 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
318 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
319 clk_register_clkdev(clk, "disp_mux.0", NULL);
320
321 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
322 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
323 clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
324
325 clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
326 apmu_base + APMU_DISP0, 0x24, &clk_lock);
327 clk_register_clkdev(clk, "hclk", "mmp-disp.0");
328
329 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
330 ARRAY_SIZE(ccic_parent),
331 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
332 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
333 clk_register_clkdev(clk, "ccic_mux.0", NULL);
334
335 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
336 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
337 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
338
339 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
340 ARRAY_SIZE(ccic_phy_parent),
341 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
342 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
343 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
344
345 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
346 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
347 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
348
349 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
350 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
351 10, 5, 0, &clk_lock);
352 clk_register_clkdev(clk, "sphyclk_div", NULL);
353
354 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
355 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
356 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
357}
358
