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6#include <linux/err.h>
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/clk-provider.h>
11#include <linux/regmap.h>
12#include <linux/reset-controller.h>
13
14#include <dt-bindings/clock/qcom,gcc-sm6115.h>
15
16#include "clk-alpha-pll.h"
17#include "clk-branch.h"
18#include "clk-pll.h"
19#include "clk-rcg.h"
20#include "clk-regmap.h"
21#include "clk-regmap-divider.h"
22#include "common.h"
23#include "gdsc.h"
24#include "reset.h"
25
26enum {
27 P_BI_TCXO,
28 P_GPLL0_OUT_AUX2,
29 P_GPLL0_OUT_EARLY,
30 P_GPLL10_OUT_MAIN,
31 P_GPLL11_OUT_MAIN,
32 P_GPLL3_OUT_EARLY,
33 P_GPLL4_OUT_MAIN,
34 P_GPLL6_OUT_EARLY,
35 P_GPLL6_OUT_MAIN,
36 P_GPLL7_OUT_MAIN,
37 P_GPLL8_OUT_EARLY,
38 P_GPLL8_OUT_MAIN,
39 P_GPLL9_OUT_EARLY,
40 P_GPLL9_OUT_MAIN,
41 P_SLEEP_CLK,
42};
43
44static struct pll_vco default_vco[] = {
45 { 500000000, 1000000000, 2 },
46};
47
48static struct pll_vco gpll9_vco[] = {
49 { 500000000, 1250000000, 0 },
50};
51
52static struct pll_vco gpll10_vco[] = {
53 { 750000000, 1500000000, 1 },
54};
55
56static struct clk_alpha_pll gpll0 = {
57 .offset = 0x0,
58 .vco_table = default_vco,
59 .num_vco = ARRAY_SIZE(default_vco),
60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
61 .clkr = {
62 .enable_reg = 0x79000,
63 .enable_mask = BIT(0),
64 .hw.init = &(struct clk_init_data){
65 .name = "gpll0",
66 .parent_data = &(const struct clk_parent_data){
67 .fw_name = "bi_tcxo",
68 },
69 .num_parents = 1,
70 .ops = &clk_alpha_pll_ops,
71 },
72 },
73};
74
75static const struct clk_div_table post_div_table_gpll0_out_aux2[] = {
76 { 0x1, 2 },
77 { }
78};
79
80static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
81 .offset = 0x0,
82 .post_div_shift = 8,
83 .post_div_table = post_div_table_gpll0_out_aux2,
84 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
85 .width = 4,
86 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
87 .clkr.hw.init = &(struct clk_init_data){
88 .name = "gpll0_out_aux2",
89 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
90 .num_parents = 1,
91 .ops = &clk_alpha_pll_postdiv_ro_ops,
92 },
93};
94
95
96static const u8 clk_gpll9_regs[PLL_OFF_MAX_REGS] = {
97 [PLL_OFF_L_VAL] = 0x04,
98 [PLL_OFF_ALPHA_VAL] = 0x08,
99 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
100 [PLL_OFF_TEST_CTL] = 0x10,
101 [PLL_OFF_TEST_CTL_U] = 0x14,
102 [PLL_OFF_USER_CTL] = 0x18,
103 [PLL_OFF_CONFIG_CTL] = 0x1C,
104 [PLL_OFF_STATUS] = 0x20,
105};
106
107static const struct clk_div_table post_div_table_gpll0_out_main[] = {
108 { 0x0, 1 },
109 { }
110};
111
112static struct clk_alpha_pll_postdiv gpll0_out_main = {
113 .offset = 0x0,
114 .post_div_shift = 8,
115 .post_div_table = post_div_table_gpll0_out_main,
116 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
117 .width = 4,
118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
119 .clkr.hw.init = &(struct clk_init_data){
120 .name = "gpll0_out_main",
121 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
122 .num_parents = 1,
123 .ops = &clk_alpha_pll_postdiv_ro_ops,
124 },
125};
126
127
128static const struct alpha_pll_config gpll10_config = {
129 .l = 0x3c,
130 .vco_val = 0x1 << 20,
131 .vco_mask = GENMASK(21, 20),
132 .main_output_mask = BIT(0),
133 .config_ctl_val = 0x4001055b,
134};
135
136static struct clk_alpha_pll gpll10 = {
137 .offset = 0xa000,
138 .vco_table = gpll10_vco,
139 .num_vco = ARRAY_SIZE(gpll10_vco),
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
141 .clkr = {
142 .enable_reg = 0x79000,
143 .enable_mask = BIT(10),
144 .hw.init = &(struct clk_init_data){
145 .name = "gpll10",
146 .parent_data = &(const struct clk_parent_data){
147 .fw_name = "bi_tcxo",
148 },
149 .num_parents = 1,
150 .ops = &clk_alpha_pll_ops,
151 },
152 },
153};
154
155static const struct clk_div_table post_div_table_gpll10_out_main[] = {
156 { 0x0, 1 },
157 { }
158};
159
160static struct clk_alpha_pll_postdiv gpll10_out_main = {
161 .offset = 0xa000,
162 .post_div_shift = 8,
163 .post_div_table = post_div_table_gpll10_out_main,
164 .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
165 .width = 4,
166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
167 .clkr.hw.init = &(struct clk_init_data){
168 .name = "gpll10_out_main",
169 .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
170 .num_parents = 1,
171 .flags = CLK_SET_RATE_PARENT,
172 .ops = &clk_alpha_pll_postdiv_ops,
173 },
174};
175
176
177static const struct alpha_pll_config gpll11_config = {
178 .l = 0x1F,
179 .alpha = 0x0,
180 .alpha_hi = 0x40,
181 .alpha_en_mask = BIT(24),
182 .vco_val = 0x2 << 20,
183 .vco_mask = GENMASK(21, 20),
184 .config_ctl_val = 0x4001055b,
185};
186
187static struct clk_alpha_pll gpll11 = {
188 .offset = 0xb000,
189 .vco_table = default_vco,
190 .num_vco = ARRAY_SIZE(default_vco),
191 .flags = SUPPORTS_DYNAMIC_UPDATE,
192 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
193 .clkr = {
194 .enable_reg = 0x79000,
195 .enable_mask = BIT(11),
196 .hw.init = &(struct clk_init_data){
197 .name = "gpll11",
198 .parent_data = &(const struct clk_parent_data){
199 .fw_name = "bi_tcxo",
200 },
201 .num_parents = 1,
202 .ops = &clk_alpha_pll_ops,
203 },
204 },
205};
206
207static const struct clk_div_table post_div_table_gpll11_out_main[] = {
208 { 0x0, 1 },
209 { }
210};
211
212static struct clk_alpha_pll_postdiv gpll11_out_main = {
213 .offset = 0xb000,
214 .post_div_shift = 8,
215 .post_div_table = post_div_table_gpll11_out_main,
216 .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
217 .width = 4,
218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
219 .clkr.hw.init = &(struct clk_init_data){
220 .name = "gpll11_out_main",
221 .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
222 .num_parents = 1,
223 .flags = CLK_SET_RATE_PARENT,
224 .ops = &clk_alpha_pll_postdiv_ops,
225 },
226};
227
228static struct clk_alpha_pll gpll3 = {
229 .offset = 0x3000,
230 .vco_table = default_vco,
231 .num_vco = ARRAY_SIZE(default_vco),
232 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
233 .clkr = {
234 .enable_reg = 0x79000,
235 .enable_mask = BIT(3),
236 .hw.init = &(struct clk_init_data){
237 .name = "gpll3",
238 .parent_data = &(const struct clk_parent_data){
239 .fw_name = "bi_tcxo",
240 },
241 .num_parents = 1,
242 .ops = &clk_alpha_pll_ops,
243 },
244 },
245};
246
247static struct clk_alpha_pll gpll4 = {
248 .offset = 0x4000,
249 .vco_table = default_vco,
250 .num_vco = ARRAY_SIZE(default_vco),
251 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
252 .clkr = {
253 .enable_reg = 0x79000,
254 .enable_mask = BIT(4),
255 .hw.init = &(struct clk_init_data){
256 .name = "gpll4",
257 .parent_data = &(const struct clk_parent_data){
258 .fw_name = "bi_tcxo",
259 },
260 .num_parents = 1,
261 .ops = &clk_alpha_pll_ops,
262 },
263 },
264};
265
266static const struct clk_div_table post_div_table_gpll4_out_main[] = {
267 { 0x0, 1 },
268 { }
269};
270
271static struct clk_alpha_pll_postdiv gpll4_out_main = {
272 .offset = 0x4000,
273 .post_div_shift = 8,
274 .post_div_table = post_div_table_gpll4_out_main,
275 .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
276 .width = 4,
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "gpll4_out_main",
280 .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
281 .num_parents = 1,
282 .ops = &clk_alpha_pll_postdiv_ro_ops,
283 },
284};
285
286static struct clk_alpha_pll gpll6 = {
287 .offset = 0x6000,
288 .vco_table = default_vco,
289 .num_vco = ARRAY_SIZE(default_vco),
290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
291 .clkr = {
292 .enable_reg = 0x79000,
293 .enable_mask = BIT(6),
294 .hw.init = &(struct clk_init_data){
295 .name = "gpll6",
296 .parent_data = &(const struct clk_parent_data){
297 .fw_name = "bi_tcxo",
298 },
299 .num_parents = 1,
300 .ops = &clk_alpha_pll_ops,
301 },
302 },
303};
304
305static const struct clk_div_table post_div_table_gpll6_out_main[] = {
306 { 0x1, 2 },
307 { }
308};
309
310static struct clk_alpha_pll_postdiv gpll6_out_main = {
311 .offset = 0x6000,
312 .post_div_shift = 8,
313 .post_div_table = post_div_table_gpll6_out_main,
314 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
315 .width = 4,
316 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
317 .clkr.hw.init = &(struct clk_init_data){
318 .name = "gpll6_out_main",
319 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
320 .num_parents = 1,
321 .ops = &clk_alpha_pll_postdiv_ro_ops,
322 },
323};
324
325static struct clk_alpha_pll gpll7 = {
326 .offset = 0x7000,
327 .vco_table = default_vco,
328 .num_vco = ARRAY_SIZE(default_vco),
329 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
330 .clkr = {
331 .enable_reg = 0x79000,
332 .enable_mask = BIT(7),
333 .hw.init = &(struct clk_init_data){
334 .name = "gpll7",
335 .parent_data = &(const struct clk_parent_data){
336 .fw_name = "bi_tcxo",
337 },
338 .num_parents = 1,
339 .ops = &clk_alpha_pll_ops,
340 },
341 },
342};
343
344static const struct clk_div_table post_div_table_gpll7_out_main[] = {
345 { 0x0, 1 },
346 { }
347};
348
349static struct clk_alpha_pll_postdiv gpll7_out_main = {
350 .offset = 0x7000,
351 .post_div_shift = 8,
352 .post_div_table = post_div_table_gpll7_out_main,
353 .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
354 .width = 4,
355 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
356 .clkr.hw.init = &(struct clk_init_data){
357 .name = "gpll7_out_main",
358 .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
359 .num_parents = 1,
360 .ops = &clk_alpha_pll_postdiv_ro_ops,
361 },
362};
363
364
365static const struct alpha_pll_config gpll8_config = {
366 .l = 0x29,
367 .alpha = 0xAAAAAAAA,
368 .alpha_hi = 0xAA,
369 .alpha_en_mask = BIT(24),
370 .vco_val = 0x2 << 20,
371 .vco_mask = GENMASK(21, 20),
372 .main_output_mask = BIT(0),
373 .early_output_mask = BIT(3),
374 .post_div_val = 0x1 << 8,
375 .post_div_mask = GENMASK(11, 8),
376 .config_ctl_val = 0x4001055b,
377};
378
379static struct clk_alpha_pll gpll8 = {
380 .offset = 0x8000,
381 .vco_table = default_vco,
382 .num_vco = ARRAY_SIZE(default_vco),
383 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
384 .flags = SUPPORTS_DYNAMIC_UPDATE,
385 .clkr = {
386 .enable_reg = 0x79000,
387 .enable_mask = BIT(8),
388 .hw.init = &(struct clk_init_data){
389 .name = "gpll8",
390 .parent_data = &(const struct clk_parent_data){
391 .fw_name = "bi_tcxo",
392 },
393 .num_parents = 1,
394 .ops = &clk_alpha_pll_ops,
395 },
396 },
397};
398
399static const struct clk_div_table post_div_table_gpll8_out_main[] = {
400 { 0x1, 2 },
401 { }
402};
403
404static struct clk_alpha_pll_postdiv gpll8_out_main = {
405 .offset = 0x8000,
406 .post_div_shift = 8,
407 .post_div_table = post_div_table_gpll8_out_main,
408 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
409 .width = 4,
410 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "gpll8_out_main",
413 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
414 .num_parents = 1,
415 .flags = CLK_SET_RATE_PARENT,
416 .ops = &clk_alpha_pll_postdiv_ro_ops,
417 },
418};
419
420
421static const struct alpha_pll_config gpll9_config = {
422 .l = 0x3C,
423 .alpha = 0x0,
424 .post_div_val = 0x1 << 8,
425 .post_div_mask = GENMASK(9, 8),
426 .main_output_mask = BIT(0),
427 .config_ctl_val = 0x00004289,
428};
429
430static struct clk_alpha_pll gpll9 = {
431 .offset = 0x9000,
432 .vco_table = gpll9_vco,
433 .num_vco = ARRAY_SIZE(gpll9_vco),
434 .regs = clk_gpll9_regs,
435 .clkr = {
436 .enable_reg = 0x79000,
437 .enable_mask = BIT(9),
438 .hw.init = &(struct clk_init_data){
439 .name = "gpll9",
440 .parent_data = &(const struct clk_parent_data){
441 .fw_name = "bi_tcxo",
442 },
443 .num_parents = 1,
444 .ops = &clk_alpha_pll_ops,
445 },
446 },
447};
448
449static const struct clk_div_table post_div_table_gpll9_out_main[] = {
450 { 0x1, 2 },
451 { }
452};
453
454static struct clk_alpha_pll_postdiv gpll9_out_main = {
455 .offset = 0x9000,
456 .post_div_shift = 8,
457 .post_div_table = post_div_table_gpll9_out_main,
458 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
459 .width = 2,
460 .regs = clk_gpll9_regs,
461 .clkr.hw.init = &(struct clk_init_data){
462 .name = "gpll9_out_main",
463 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
464 .num_parents = 1,
465 .flags = CLK_SET_RATE_PARENT,
466 .ops = &clk_alpha_pll_postdiv_ops,
467 },
468};
469
470static const struct parent_map gcc_parent_map_0[] = {
471 { P_BI_TCXO, 0 },
472 { P_GPLL0_OUT_EARLY, 1 },
473 { P_GPLL0_OUT_AUX2, 2 },
474};
475
476static const struct clk_parent_data gcc_parents_0[] = {
477 { .fw_name = "bi_tcxo" },
478 { .hw = &gpll0.clkr.hw },
479 { .hw = &gpll0_out_aux2.clkr.hw },
480};
481
482static const struct parent_map gcc_parent_map_1[] = {
483 { P_BI_TCXO, 0 },
484 { P_GPLL0_OUT_EARLY, 1 },
485 { P_GPLL0_OUT_AUX2, 2 },
486 { P_GPLL6_OUT_MAIN, 4 },
487};
488
489static const struct clk_parent_data gcc_parents_1[] = {
490 { .fw_name = "bi_tcxo" },
491 { .hw = &gpll0.clkr.hw },
492 { .hw = &gpll0_out_aux2.clkr.hw },
493 { .hw = &gpll6_out_main.clkr.hw },
494};
495
496static const struct parent_map gcc_parent_map_2[] = {
497 { P_BI_TCXO, 0 },
498 { P_GPLL0_OUT_EARLY, 1 },
499 { P_GPLL0_OUT_AUX2, 2 },
500 { P_SLEEP_CLK, 5 },
501};
502
503static const struct clk_parent_data gcc_parents_2[] = {
504 { .fw_name = "bi_tcxo" },
505 { .hw = &gpll0.clkr.hw },
506 { .hw = &gpll0_out_aux2.clkr.hw },
507 { .fw_name = "sleep_clk" },
508};
509
510static const struct parent_map gcc_parent_map_3[] = {
511 { P_BI_TCXO, 0 },
512 { P_GPLL0_OUT_EARLY, 1 },
513 { P_GPLL9_OUT_EARLY, 2 },
514 { P_GPLL10_OUT_MAIN, 3 },
515 { P_GPLL9_OUT_MAIN, 5 },
516};
517
518static const struct clk_parent_data gcc_parents_3[] = {
519 { .fw_name = "bi_tcxo" },
520 { .hw = &gpll0.clkr.hw },
521 { .hw = &gpll9.clkr.hw },
522 { .hw = &gpll10_out_main.clkr.hw },
523 { .hw = &gpll9_out_main.clkr.hw },
524};
525
526static const struct parent_map gcc_parent_map_4[] = {
527 { P_BI_TCXO, 0 },
528 { P_GPLL0_OUT_EARLY, 1 },
529 { P_GPLL0_OUT_AUX2, 2 },
530 { P_GPLL4_OUT_MAIN, 5 },
531};
532
533static const struct clk_parent_data gcc_parents_4[] = {
534 { .fw_name = "bi_tcxo" },
535 { .hw = &gpll0.clkr.hw },
536 { .hw = &gpll0_out_aux2.clkr.hw },
537 { .hw = &gpll4_out_main.clkr.hw },
538};
539
540static const struct parent_map gcc_parent_map_5[] = {
541 { P_BI_TCXO, 0 },
542 { P_GPLL0_OUT_EARLY, 1 },
543 { P_GPLL8_OUT_EARLY, 2 },
544 { P_GPLL10_OUT_MAIN, 3 },
545 { P_GPLL8_OUT_MAIN, 4 },
546 { P_GPLL9_OUT_MAIN, 5 },
547};
548
549static const struct clk_parent_data gcc_parents_5[] = {
550 { .fw_name = "bi_tcxo" },
551 { .hw = &gpll0.clkr.hw },
552 { .hw = &gpll8.clkr.hw },
553 { .hw = &gpll10_out_main.clkr.hw },
554 { .hw = &gpll8_out_main.clkr.hw },
555 { .hw = &gpll9_out_main.clkr.hw },
556};
557
558static const struct parent_map gcc_parent_map_6[] = {
559 { P_BI_TCXO, 0 },
560 { P_GPLL0_OUT_EARLY, 1 },
561 { P_GPLL8_OUT_EARLY, 2 },
562 { P_GPLL10_OUT_MAIN, 3 },
563 { P_GPLL6_OUT_MAIN, 4 },
564 { P_GPLL9_OUT_MAIN, 5 },
565 { P_GPLL3_OUT_EARLY, 6 },
566};
567
568static const struct clk_parent_data gcc_parents_6[] = {
569 { .fw_name = "bi_tcxo" },
570 { .hw = &gpll0.clkr.hw },
571 { .hw = &gpll8.clkr.hw },
572 { .hw = &gpll10_out_main.clkr.hw },
573 { .hw = &gpll6_out_main.clkr.hw },
574 { .hw = &gpll9_out_main.clkr.hw },
575 { .hw = &gpll3.clkr.hw },
576};
577
578static const struct parent_map gcc_parent_map_7[] = {
579 { P_BI_TCXO, 0 },
580 { P_GPLL0_OUT_EARLY, 1 },
581 { P_GPLL0_OUT_AUX2, 2 },
582 { P_GPLL10_OUT_MAIN, 3 },
583 { P_GPLL4_OUT_MAIN, 5 },
584 { P_GPLL3_OUT_EARLY, 6 },
585};
586
587static const struct clk_parent_data gcc_parents_7[] = {
588 { .fw_name = "bi_tcxo" },
589 { .hw = &gpll0.clkr.hw },
590 { .hw = &gpll0_out_aux2.clkr.hw },
591 { .hw = &gpll10_out_main.clkr.hw },
592 { .hw = &gpll4_out_main.clkr.hw },
593 { .hw = &gpll3.clkr.hw },
594};
595
596static const struct parent_map gcc_parent_map_8[] = {
597 { P_BI_TCXO, 0 },
598 { P_GPLL0_OUT_EARLY, 1 },
599 { P_GPLL8_OUT_EARLY, 2 },
600 { P_GPLL10_OUT_MAIN, 3 },
601 { P_GPLL8_OUT_MAIN, 4 },
602 { P_GPLL9_OUT_MAIN, 5 },
603 { P_GPLL3_OUT_EARLY, 6 },
604};
605
606static const struct clk_parent_data gcc_parents_8[] = {
607 { .fw_name = "bi_tcxo" },
608 { .hw = &gpll0.clkr.hw },
609 { .hw = &gpll8.clkr.hw },
610 { .hw = &gpll10_out_main.clkr.hw },
611 { .hw = &gpll8_out_main.clkr.hw },
612 { .hw = &gpll9_out_main.clkr.hw },
613 { .hw = &gpll3.clkr.hw },
614};
615
616static const struct parent_map gcc_parent_map_9[] = {
617 { P_BI_TCXO, 0 },
618 { P_GPLL0_OUT_EARLY, 1 },
619 { P_GPLL0_OUT_AUX2, 2 },
620 { P_GPLL10_OUT_MAIN, 3 },
621 { P_GPLL8_OUT_MAIN, 4 },
622 { P_GPLL9_OUT_MAIN, 5 },
623 { P_GPLL3_OUT_EARLY, 6 },
624};
625
626static const struct clk_parent_data gcc_parents_9[] = {
627 { .fw_name = "bi_tcxo" },
628 { .hw = &gpll0.clkr.hw },
629 { .hw = &gpll0_out_aux2.clkr.hw },
630 { .hw = &gpll10_out_main.clkr.hw },
631 { .hw = &gpll8_out_main.clkr.hw },
632 { .hw = &gpll9_out_main.clkr.hw },
633 { .hw = &gpll3.clkr.hw },
634};
635
636static const struct parent_map gcc_parent_map_10[] = {
637 { P_BI_TCXO, 0 },
638 { P_GPLL0_OUT_EARLY, 1 },
639 { P_GPLL8_OUT_EARLY, 2 },
640 { P_GPLL10_OUT_MAIN, 3 },
641 { P_GPLL6_OUT_EARLY, 4 },
642 { P_GPLL9_OUT_MAIN, 5 },
643};
644
645static const struct clk_parent_data gcc_parents_10[] = {
646 { .fw_name = "bi_tcxo" },
647 { .hw = &gpll0.clkr.hw },
648 { .hw = &gpll8.clkr.hw },
649 { .hw = &gpll10_out_main.clkr.hw },
650 { .hw = &gpll6.clkr.hw },
651 { .hw = &gpll9_out_main.clkr.hw },
652};
653
654static const struct parent_map gcc_parent_map_11[] = {
655 { P_BI_TCXO, 0 },
656 { P_GPLL0_OUT_EARLY, 1 },
657 { P_GPLL0_OUT_AUX2, 2 },
658 { P_GPLL7_OUT_MAIN, 3 },
659 { P_GPLL4_OUT_MAIN, 5 },
660};
661
662static const struct clk_parent_data gcc_parents_11[] = {
663 { .fw_name = "bi_tcxo" },
664 { .hw = &gpll0.clkr.hw },
665 { .hw = &gpll0_out_aux2.clkr.hw },
666 { .hw = &gpll7_out_main.clkr.hw },
667 { .hw = &gpll4_out_main.clkr.hw },
668};
669
670static const struct parent_map gcc_parent_map_12[] = {
671 { P_BI_TCXO, 0 },
672 { P_SLEEP_CLK, 5 },
673};
674
675static const struct clk_parent_data gcc_parents_12[] = {
676 { .fw_name = "bi_tcxo" },
677 { .fw_name = "sleep_clk" },
678};
679
680static const struct parent_map gcc_parent_map_13[] = {
681 { P_BI_TCXO, 0 },
682 { P_GPLL11_OUT_MAIN, 1 },
683};
684
685static const struct clk_parent_data gcc_parents_13[] = {
686 { .fw_name = "bi_tcxo" },
687 { .hw = &gpll11_out_main.clkr.hw },
688};
689
690static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
691 F(19200000, P_BI_TCXO, 1, 0, 0),
692 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
693 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
694 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
695 { }
696};
697
698static struct clk_rcg2 gcc_camss_axi_clk_src = {
699 .cmd_rcgr = 0x5802c,
700 .mnd_width = 0,
701 .hid_width = 5,
702 .parent_map = gcc_parent_map_7,
703 .freq_tbl = ftbl_gcc_camss_axi_clk_src,
704 .clkr.hw.init = &(struct clk_init_data){
705 .name = "gcc_camss_axi_clk_src",
706 .parent_data = gcc_parents_7,
707 .num_parents = ARRAY_SIZE(gcc_parents_7),
708 .flags = CLK_SET_RATE_PARENT,
709 .ops = &clk_rcg2_ops,
710 },
711};
712
713static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
714 F(19200000, P_BI_TCXO, 1, 0, 0),
715 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
716 { }
717};
718
719static struct clk_rcg2 gcc_camss_cci_clk_src = {
720 .cmd_rcgr = 0x56000,
721 .mnd_width = 0,
722 .hid_width = 5,
723 .parent_map = gcc_parent_map_9,
724 .freq_tbl = ftbl_gcc_camss_cci_clk_src,
725 .clkr.hw.init = &(struct clk_init_data){
726 .name = "gcc_camss_cci_clk_src",
727 .parent_data = gcc_parents_9,
728 .num_parents = ARRAY_SIZE(gcc_parents_9),
729 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
730 .ops = &clk_rcg2_ops,
731 },
732};
733
734static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
735 F(19200000, P_BI_TCXO, 1, 0, 0),
736 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
737 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
738 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
739 { }
740};
741
742static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
743 .cmd_rcgr = 0x59000,
744 .mnd_width = 0,
745 .hid_width = 5,
746 .parent_map = gcc_parent_map_4,
747 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
748 .clkr.hw.init = &(struct clk_init_data){
749 .name = "gcc_camss_csi0phytimer_clk_src",
750 .parent_data = gcc_parents_4,
751 .num_parents = ARRAY_SIZE(gcc_parents_4),
752 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
753 .ops = &clk_rcg2_ops,
754 },
755};
756
757static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
758 .cmd_rcgr = 0x5901c,
759 .mnd_width = 0,
760 .hid_width = 5,
761 .parent_map = gcc_parent_map_4,
762 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "gcc_camss_csi1phytimer_clk_src",
765 .parent_data = gcc_parents_4,
766 .num_parents = ARRAY_SIZE(gcc_parents_4),
767 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
768 .ops = &clk_rcg2_ops,
769 },
770};
771
772static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
773 .cmd_rcgr = 0x59038,
774 .mnd_width = 0,
775 .hid_width = 5,
776 .parent_map = gcc_parent_map_4,
777 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
778 .clkr.hw.init = &(struct clk_init_data){
779 .name = "gcc_camss_csi2phytimer_clk_src",
780 .parent_data = gcc_parents_4,
781 .num_parents = ARRAY_SIZE(gcc_parents_4),
782 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
783 .ops = &clk_rcg2_ops,
784 },
785};
786
787static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
788 F(19200000, P_BI_TCXO, 1, 0, 0),
789 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
790 F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9),
791 { }
792};
793
794static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
795 .cmd_rcgr = 0x51000,
796 .mnd_width = 8,
797 .hid_width = 5,
798 .parent_map = gcc_parent_map_3,
799 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "gcc_camss_mclk0_clk_src",
802 .parent_data = gcc_parents_3,
803 .num_parents = ARRAY_SIZE(gcc_parents_3),
804 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
810 .cmd_rcgr = 0x5101c,
811 .mnd_width = 8,
812 .hid_width = 5,
813 .parent_map = gcc_parent_map_3,
814 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "gcc_camss_mclk1_clk_src",
817 .parent_data = gcc_parents_3,
818 .num_parents = ARRAY_SIZE(gcc_parents_3),
819 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
820 .ops = &clk_rcg2_ops,
821 },
822};
823
824static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
825 .cmd_rcgr = 0x51038,
826 .mnd_width = 8,
827 .hid_width = 5,
828 .parent_map = gcc_parent_map_3,
829 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
830 .clkr.hw.init = &(struct clk_init_data){
831 .name = "gcc_camss_mclk2_clk_src",
832 .parent_data = gcc_parents_3,
833 .num_parents = ARRAY_SIZE(gcc_parents_3),
834 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
835 .ops = &clk_rcg2_ops,
836 },
837};
838
839static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
840 .cmd_rcgr = 0x51054,
841 .mnd_width = 8,
842 .hid_width = 5,
843 .parent_map = gcc_parent_map_3,
844 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
845 .clkr.hw.init = &(struct clk_init_data){
846 .name = "gcc_camss_mclk3_clk_src",
847 .parent_data = gcc_parents_3,
848 .num_parents = ARRAY_SIZE(gcc_parents_3),
849 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
850 .ops = &clk_rcg2_ops,
851 },
852};
853
854static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
855 F(19200000, P_BI_TCXO, 1, 0, 0),
856 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
857 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
858 { }
859};
860
861static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
862 .cmd_rcgr = 0x55024,
863 .mnd_width = 0,
864 .hid_width = 5,
865 .parent_map = gcc_parent_map_8,
866 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
867 .clkr.hw.init = &(struct clk_init_data){
868 .name = "gcc_camss_ope_ahb_clk_src",
869 .parent_data = gcc_parents_8,
870 .num_parents = ARRAY_SIZE(gcc_parents_8),
871 .flags = CLK_SET_RATE_PARENT,
872 .ops = &clk_rcg2_ops,
873 },
874};
875
876static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
877 F(19200000, P_BI_TCXO, 1, 0, 0),
878 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
879 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
880 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
881 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
882 { }
883};
884
885static struct clk_rcg2 gcc_camss_ope_clk_src = {
886 .cmd_rcgr = 0x55004,
887 .mnd_width = 0,
888 .hid_width = 5,
889 .parent_map = gcc_parent_map_8,
890 .freq_tbl = ftbl_gcc_camss_ope_clk_src,
891 .clkr.hw.init = &(struct clk_init_data){
892 .name = "gcc_camss_ope_clk_src",
893 .parent_data = gcc_parents_8,
894 .num_parents = ARRAY_SIZE(gcc_parents_8),
895 .flags = CLK_SET_RATE_PARENT,
896 .ops = &clk_rcg2_ops,
897 },
898};
899
900static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
901 F(19200000, P_BI_TCXO, 1, 0, 0),
902 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
903 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
904 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
905 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
906 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
907 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
908 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
909 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
910 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
911 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
912 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
913 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
914 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
915 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
916 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
917 { }
918};
919
920static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
921 .cmd_rcgr = 0x52004,
922 .mnd_width = 8,
923 .hid_width = 5,
924 .parent_map = gcc_parent_map_5,
925 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
926 .clkr.hw.init = &(struct clk_init_data){
927 .name = "gcc_camss_tfe_0_clk_src",
928 .parent_data = gcc_parents_5,
929 .num_parents = ARRAY_SIZE(gcc_parents_5),
930 .flags = CLK_SET_RATE_PARENT,
931 .ops = &clk_rcg2_ops,
932 },
933};
934
935static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
936 F(19200000, P_BI_TCXO, 1, 0, 0),
937 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
938 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
939 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
940 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
941 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
942 { }
943};
944
945static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
946 .cmd_rcgr = 0x52094,
947 .mnd_width = 0,
948 .hid_width = 5,
949 .parent_map = gcc_parent_map_6,
950 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
951 .clkr.hw.init = &(struct clk_init_data){
952 .name = "gcc_camss_tfe_0_csid_clk_src",
953 .parent_data = gcc_parents_6,
954 .num_parents = ARRAY_SIZE(gcc_parents_6),
955 .flags = CLK_SET_RATE_PARENT,
956 .ops = &clk_rcg2_ops,
957 },
958};
959
960static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
961 .cmd_rcgr = 0x52024,
962 .mnd_width = 8,
963 .hid_width = 5,
964 .parent_map = gcc_parent_map_5,
965 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
966 .clkr.hw.init = &(struct clk_init_data){
967 .name = "gcc_camss_tfe_1_clk_src",
968 .parent_data = gcc_parents_5,
969 .num_parents = ARRAY_SIZE(gcc_parents_5),
970 .flags = CLK_SET_RATE_PARENT,
971 .ops = &clk_rcg2_ops,
972 },
973};
974
975static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
976 .cmd_rcgr = 0x520b4,
977 .mnd_width = 0,
978 .hid_width = 5,
979 .parent_map = gcc_parent_map_6,
980 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
981 .clkr.hw.init = &(struct clk_init_data){
982 .name = "gcc_camss_tfe_1_csid_clk_src",
983 .parent_data = gcc_parents_6,
984 .num_parents = ARRAY_SIZE(gcc_parents_6),
985 .flags = CLK_SET_RATE_PARENT,
986 .ops = &clk_rcg2_ops,
987 },
988};
989
990static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {
991 .cmd_rcgr = 0x52044,
992 .mnd_width = 8,
993 .hid_width = 5,
994 .parent_map = gcc_parent_map_5,
995 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
996 .clkr.hw.init = &(struct clk_init_data){
997 .name = "gcc_camss_tfe_2_clk_src",
998 .parent_data = gcc_parents_5,
999 .num_parents = ARRAY_SIZE(gcc_parents_5),
1000 .flags = CLK_SET_RATE_PARENT,
1001 .ops = &clk_rcg2_ops,
1002 },
1003};
1004
1005static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {
1006 .cmd_rcgr = 0x520d4,
1007 .mnd_width = 0,
1008 .hid_width = 5,
1009 .parent_map = gcc_parent_map_6,
1010 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
1011 .clkr.hw.init = &(struct clk_init_data){
1012 .name = "gcc_camss_tfe_2_csid_clk_src",
1013 .parent_data = gcc_parents_6,
1014 .num_parents = ARRAY_SIZE(gcc_parents_6),
1015 .flags = CLK_SET_RATE_PARENT,
1016 .ops = &clk_rcg2_ops,
1017 },
1018};
1019
1020static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
1021 F(19200000, P_BI_TCXO, 1, 0, 0),
1022 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1023 F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9),
1024 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
1025 { }
1026};
1027
1028static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
1029 .cmd_rcgr = 0x52064,
1030 .mnd_width = 16,
1031 .hid_width = 5,
1032 .parent_map = gcc_parent_map_10,
1033 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
1034 .clkr.hw.init = &(struct clk_init_data){
1035 .name = "gcc_camss_tfe_cphy_rx_clk_src",
1036 .parent_data = gcc_parents_10,
1037 .num_parents = ARRAY_SIZE(gcc_parents_10),
1038 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1039 .ops = &clk_rcg2_ops,
1040 },
1041};
1042
1043static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
1044 F(19200000, P_BI_TCXO, 1, 0, 0),
1045 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1046 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
1047 { }
1048};
1049
1050static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
1051 .cmd_rcgr = 0x58010,
1052 .mnd_width = 0,
1053 .hid_width = 5,
1054 .parent_map = gcc_parent_map_7,
1055 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
1056 .clkr.hw.init = &(struct clk_init_data){
1057 .name = "gcc_camss_top_ahb_clk_src",
1058 .parent_data = gcc_parents_7,
1059 .num_parents = ARRAY_SIZE(gcc_parents_7),
1060 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1061 .ops = &clk_rcg2_ops,
1062 },
1063};
1064
1065static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
1066 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1067 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1068 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1069 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
1070 { }
1071};
1072
1073static struct clk_rcg2 gcc_gp1_clk_src = {
1074 .cmd_rcgr = 0x4d004,
1075 .mnd_width = 8,
1076 .hid_width = 5,
1077 .parent_map = gcc_parent_map_2,
1078 .freq_tbl = ftbl_gcc_gp1_clk_src,
1079 .clkr.hw.init = &(struct clk_init_data){
1080 .name = "gcc_gp1_clk_src",
1081 .parent_data = gcc_parents_2,
1082 .num_parents = ARRAY_SIZE(gcc_parents_2),
1083 .ops = &clk_rcg2_ops,
1084 },
1085};
1086
1087static struct clk_rcg2 gcc_gp2_clk_src = {
1088 .cmd_rcgr = 0x4e004,
1089 .mnd_width = 8,
1090 .hid_width = 5,
1091 .parent_map = gcc_parent_map_2,
1092 .freq_tbl = ftbl_gcc_gp1_clk_src,
1093 .clkr.hw.init = &(struct clk_init_data){
1094 .name = "gcc_gp2_clk_src",
1095 .parent_data = gcc_parents_2,
1096 .num_parents = ARRAY_SIZE(gcc_parents_2),
1097 .ops = &clk_rcg2_ops,
1098 },
1099};
1100
1101static struct clk_rcg2 gcc_gp3_clk_src = {
1102 .cmd_rcgr = 0x4f004,
1103 .mnd_width = 8,
1104 .hid_width = 5,
1105 .parent_map = gcc_parent_map_2,
1106 .freq_tbl = ftbl_gcc_gp1_clk_src,
1107 .clkr.hw.init = &(struct clk_init_data){
1108 .name = "gcc_gp3_clk_src",
1109 .parent_data = gcc_parents_2,
1110 .num_parents = ARRAY_SIZE(gcc_parents_2),
1111 .ops = &clk_rcg2_ops,
1112 },
1113};
1114
1115static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1116 F(19200000, P_BI_TCXO, 1, 0, 0),
1117 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1118 { }
1119};
1120
1121static struct clk_rcg2 gcc_pdm2_clk_src = {
1122 .cmd_rcgr = 0x20010,
1123 .mnd_width = 0,
1124 .hid_width = 5,
1125 .parent_map = gcc_parent_map_0,
1126 .freq_tbl = ftbl_gcc_pdm2_clk_src,
1127 .clkr.hw.init = &(struct clk_init_data){
1128 .name = "gcc_pdm2_clk_src",
1129 .parent_data = gcc_parents_0,
1130 .num_parents = ARRAY_SIZE(gcc_parents_0),
1131 .ops = &clk_rcg2_ops,
1132 },
1133};
1134
1135static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1136 F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
1137 F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
1138 F(19200000, P_BI_TCXO, 1, 0, 0),
1139 F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
1140 F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
1141 F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
1142 F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
1143 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1144 F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
1145 F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
1146 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1147 F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
1148 F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
1149 F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
1150 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1151 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1152 { }
1153};
1154
1155static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1156 .name = "gcc_qupv3_wrap0_s0_clk_src",
1157 .parent_data = gcc_parents_1,
1158 .num_parents = ARRAY_SIZE(gcc_parents_1),
1159 .ops = &clk_rcg2_ops,
1160};
1161
1162static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1163 .cmd_rcgr = 0x1f148,
1164 .mnd_width = 16,
1165 .hid_width = 5,
1166 .parent_map = gcc_parent_map_1,
1167 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1168 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1169};
1170
1171static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1172 .name = "gcc_qupv3_wrap0_s1_clk_src",
1173 .parent_data = gcc_parents_1,
1174 .num_parents = ARRAY_SIZE(gcc_parents_1),
1175 .ops = &clk_rcg2_ops,
1176};
1177
1178static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1179 .cmd_rcgr = 0x1f278,
1180 .mnd_width = 16,
1181 .hid_width = 5,
1182 .parent_map = gcc_parent_map_1,
1183 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1184 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1185};
1186
1187static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1188 .name = "gcc_qupv3_wrap0_s2_clk_src",
1189 .parent_data = gcc_parents_1,
1190 .num_parents = ARRAY_SIZE(gcc_parents_1),
1191 .ops = &clk_rcg2_ops,
1192};
1193
1194static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1195 .cmd_rcgr = 0x1f3a8,
1196 .mnd_width = 16,
1197 .hid_width = 5,
1198 .parent_map = gcc_parent_map_1,
1199 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1200 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1201};
1202
1203static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1204 .name = "gcc_qupv3_wrap0_s3_clk_src",
1205 .parent_data = gcc_parents_1,
1206 .num_parents = ARRAY_SIZE(gcc_parents_1),
1207 .ops = &clk_rcg2_ops,
1208};
1209
1210static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1211 .cmd_rcgr = 0x1f4d8,
1212 .mnd_width = 16,
1213 .hid_width = 5,
1214 .parent_map = gcc_parent_map_1,
1215 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1216 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1217};
1218
1219static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1220 .name = "gcc_qupv3_wrap0_s4_clk_src",
1221 .parent_data = gcc_parents_1,
1222 .num_parents = ARRAY_SIZE(gcc_parents_1),
1223 .ops = &clk_rcg2_ops,
1224};
1225
1226static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1227 .cmd_rcgr = 0x1f608,
1228 .mnd_width = 16,
1229 .hid_width = 5,
1230 .parent_map = gcc_parent_map_1,
1231 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1232 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1233};
1234
1235static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1236 .name = "gcc_qupv3_wrap0_s5_clk_src",
1237 .parent_data = gcc_parents_1,
1238 .num_parents = ARRAY_SIZE(gcc_parents_1),
1239 .ops = &clk_rcg2_ops,
1240};
1241
1242static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1243 .cmd_rcgr = 0x1f738,
1244 .mnd_width = 16,
1245 .hid_width = 5,
1246 .parent_map = gcc_parent_map_1,
1247 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1248 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1249};
1250
1251static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1252 F(144000, P_BI_TCXO, 16, 3, 25),
1253 F(400000, P_BI_TCXO, 12, 1, 4),
1254 F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
1255 F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
1256 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1257 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1258 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1259 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1260 { }
1261};
1262
1263static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1264 .cmd_rcgr = 0x38028,
1265 .mnd_width = 8,
1266 .hid_width = 5,
1267 .parent_map = gcc_parent_map_1,
1268 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1269 .clkr.hw.init = &(struct clk_init_data){
1270 .name = "gcc_sdcc1_apps_clk_src",
1271 .parent_data = gcc_parents_1,
1272 .num_parents = ARRAY_SIZE(gcc_parents_1),
1273 .ops = &clk_rcg2_ops,
1274 },
1275};
1276
1277static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1278 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1279 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1280 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1281 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1282 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1283 { }
1284};
1285
1286static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1287 .cmd_rcgr = 0x38010,
1288 .mnd_width = 0,
1289 .hid_width = 5,
1290 .parent_map = gcc_parent_map_0,
1291 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1292 .clkr.hw.init = &(struct clk_init_data){
1293 .name = "gcc_sdcc1_ice_core_clk_src",
1294 .parent_data = gcc_parents_0,
1295 .num_parents = ARRAY_SIZE(gcc_parents_0),
1296 .ops = &clk_rcg2_ops,
1297 },
1298};
1299
1300static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1301 F(400000, P_BI_TCXO, 12, 1, 4),
1302 F(19200000, P_BI_TCXO, 1, 0, 0),
1303 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1304 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1305 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1306 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1307 { }
1308};
1309
1310static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1311 .cmd_rcgr = 0x1e00c,
1312 .mnd_width = 8,
1313 .hid_width = 5,
1314 .parent_map = gcc_parent_map_11,
1315 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1316 .clkr.hw.init = &(struct clk_init_data){
1317 .name = "gcc_sdcc2_apps_clk_src",
1318 .parent_data = gcc_parents_11,
1319 .num_parents = ARRAY_SIZE(gcc_parents_11),
1320 .ops = &clk_rcg2_ops,
1321 .flags = CLK_OPS_PARENT_ENABLE,
1322 },
1323};
1324
1325static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1326 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1327 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1328 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1329 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1330 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1331 { }
1332};
1333
1334static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1335 .cmd_rcgr = 0x45020,
1336 .mnd_width = 8,
1337 .hid_width = 5,
1338 .parent_map = gcc_parent_map_0,
1339 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1340 .clkr.hw.init = &(struct clk_init_data){
1341 .name = "gcc_ufs_phy_axi_clk_src",
1342 .parent_data = gcc_parents_0,
1343 .num_parents = ARRAY_SIZE(gcc_parents_0),
1344 .ops = &clk_rcg2_ops,
1345 },
1346};
1347
1348static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1349 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1350 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1351 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1352 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1353 { }
1354};
1355
1356static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1357 .cmd_rcgr = 0x45048,
1358 .mnd_width = 0,
1359 .hid_width = 5,
1360 .parent_map = gcc_parent_map_0,
1361 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1362 .clkr.hw.init = &(struct clk_init_data){
1363 .name = "gcc_ufs_phy_ice_core_clk_src",
1364 .parent_data = gcc_parents_0,
1365 .num_parents = ARRAY_SIZE(gcc_parents_0),
1366 .ops = &clk_rcg2_ops,
1367 },
1368};
1369
1370static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1371 F(9600000, P_BI_TCXO, 2, 0, 0),
1372 F(19200000, P_BI_TCXO, 1, 0, 0),
1373 { }
1374};
1375
1376static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1377 .cmd_rcgr = 0x4507c,
1378 .mnd_width = 0,
1379 .hid_width = 5,
1380 .parent_map = gcc_parent_map_0,
1381 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1382 .clkr.hw.init = &(struct clk_init_data){
1383 .name = "gcc_ufs_phy_phy_aux_clk_src",
1384 .parent_data = gcc_parents_0,
1385 .num_parents = ARRAY_SIZE(gcc_parents_0),
1386 .ops = &clk_rcg2_ops,
1387 },
1388};
1389
1390static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1391 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1392 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1393 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1394 { }
1395};
1396
1397static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1398 .cmd_rcgr = 0x45060,
1399 .mnd_width = 0,
1400 .hid_width = 5,
1401 .parent_map = gcc_parent_map_0,
1402 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1403 .clkr.hw.init = &(struct clk_init_data){
1404 .name = "gcc_ufs_phy_unipro_core_clk_src",
1405 .parent_data = gcc_parents_0,
1406 .num_parents = ARRAY_SIZE(gcc_parents_0),
1407 .ops = &clk_rcg2_ops,
1408 },
1409};
1410
1411static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1412 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1413 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1414 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1415 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1416 { }
1417};
1418
1419static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1420 .cmd_rcgr = 0x1a01c,
1421 .mnd_width = 8,
1422 .hid_width = 5,
1423 .parent_map = gcc_parent_map_0,
1424 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1425 .clkr.hw.init = &(struct clk_init_data){
1426 .name = "gcc_usb30_prim_master_clk_src",
1427 .parent_data = gcc_parents_0,
1428 .num_parents = ARRAY_SIZE(gcc_parents_0),
1429 .ops = &clk_rcg2_ops,
1430 },
1431};
1432
1433static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1434 F(19200000, P_BI_TCXO, 1, 0, 0),
1435 { }
1436};
1437
1438static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1439 .cmd_rcgr = 0x1a034,
1440 .mnd_width = 0,
1441 .hid_width = 5,
1442 .parent_map = gcc_parent_map_0,
1443 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1444 .clkr.hw.init = &(struct clk_init_data){
1445 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1446 .parent_data = gcc_parents_0,
1447 .num_parents = ARRAY_SIZE(gcc_parents_0),
1448 .ops = &clk_rcg2_ops,
1449 },
1450};
1451
1452static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1453 .reg = 0x1a04c,
1454 .shift = 0,
1455 .width = 2,
1456 .clkr.hw.init = &(struct clk_init_data) {
1457 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1458 .parent_hws = (const struct clk_hw *[]) {
1459 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
1460 .num_parents = 1,
1461 .ops = &clk_regmap_div_ro_ops,
1462 },
1463};
1464
1465static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1466 .cmd_rcgr = 0x1a060,
1467 .mnd_width = 0,
1468 .hid_width = 5,
1469 .parent_map = gcc_parent_map_12,
1470 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1471 .clkr.hw.init = &(struct clk_init_data){
1472 .name = "gcc_usb3_prim_phy_aux_clk_src",
1473 .parent_data = gcc_parents_12,
1474 .num_parents = ARRAY_SIZE(gcc_parents_12),
1475 .ops = &clk_rcg2_ops,
1476 },
1477};
1478
1479static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
1480 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1481 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1482 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1483 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1484 { }
1485};
1486
1487static struct clk_rcg2 gcc_video_venus_clk_src = {
1488 .cmd_rcgr = 0x58060,
1489 .mnd_width = 0,
1490 .hid_width = 5,
1491 .parent_map = gcc_parent_map_13,
1492 .freq_tbl = ftbl_gcc_video_venus_clk_src,
1493 .clkr.hw.init = &(struct clk_init_data){
1494 .name = "gcc_video_venus_clk_src",
1495 .parent_data = gcc_parents_13,
1496 .num_parents = ARRAY_SIZE(gcc_parents_13),
1497 .flags = CLK_SET_RATE_PARENT,
1498 .ops = &clk_rcg2_ops,
1499 },
1500};
1501
1502static struct clk_branch gcc_ahb2phy_csi_clk = {
1503 .halt_reg = 0x1d004,
1504 .halt_check = BRANCH_HALT,
1505 .hwcg_reg = 0x1d004,
1506 .hwcg_bit = 1,
1507 .clkr = {
1508 .enable_reg = 0x1d004,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data){
1511 .name = "gcc_ahb2phy_csi_clk",
1512 .ops = &clk_branch2_ops,
1513 },
1514 },
1515};
1516
1517static struct clk_branch gcc_ahb2phy_usb_clk = {
1518 .halt_reg = 0x1d008,
1519 .halt_check = BRANCH_HALT,
1520 .hwcg_reg = 0x1d008,
1521 .hwcg_bit = 1,
1522 .clkr = {
1523 .enable_reg = 0x1d008,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1526 .name = "gcc_ahb2phy_usb_clk",
1527 .ops = &clk_branch2_ops,
1528 },
1529 },
1530};
1531
1532static struct clk_branch gcc_bimc_gpu_axi_clk = {
1533 .halt_reg = 0x71154,
1534 .halt_check = BRANCH_HALT_DELAY,
1535 .hwcg_reg = 0x71154,
1536 .hwcg_bit = 1,
1537 .clkr = {
1538 .enable_reg = 0x71154,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "gcc_bimc_gpu_axi_clk",
1542 .ops = &clk_branch2_ops,
1543 },
1544 },
1545};
1546
1547static struct clk_branch gcc_boot_rom_ahb_clk = {
1548 .halt_reg = 0x23004,
1549 .halt_check = BRANCH_HALT_VOTED,
1550 .hwcg_reg = 0x23004,
1551 .hwcg_bit = 1,
1552 .clkr = {
1553 .enable_reg = 0x79004,
1554 .enable_mask = BIT(10),
1555 .hw.init = &(struct clk_init_data){
1556 .name = "gcc_boot_rom_ahb_clk",
1557 .ops = &clk_branch2_ops,
1558 },
1559 },
1560};
1561
1562static struct clk_branch gcc_cam_throttle_nrt_clk = {
1563 .halt_reg = 0x17070,
1564 .halt_check = BRANCH_HALT_VOTED,
1565 .hwcg_reg = 0x17070,
1566 .hwcg_bit = 1,
1567 .clkr = {
1568 .enable_reg = 0x79004,
1569 .enable_mask = BIT(27),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "gcc_cam_throttle_nrt_clk",
1572 .ops = &clk_branch2_ops,
1573 },
1574 },
1575};
1576
1577static struct clk_branch gcc_cam_throttle_rt_clk = {
1578 .halt_reg = 0x1706c,
1579 .halt_check = BRANCH_HALT_VOTED,
1580 .hwcg_reg = 0x1706c,
1581 .hwcg_bit = 1,
1582 .clkr = {
1583 .enable_reg = 0x79004,
1584 .enable_mask = BIT(26),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "gcc_cam_throttle_rt_clk",
1587 .ops = &clk_branch2_ops,
1588 },
1589 },
1590};
1591
1592static struct clk_branch gcc_camera_ahb_clk = {
1593 .halt_reg = 0x17008,
1594 .halt_check = BRANCH_HALT_DELAY,
1595 .hwcg_reg = 0x17008,
1596 .hwcg_bit = 1,
1597 .clkr = {
1598 .enable_reg = 0x17008,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "gcc_camera_ahb_clk",
1602 .flags = CLK_IS_CRITICAL,
1603 .ops = &clk_branch2_ops,
1604 },
1605 },
1606};
1607
1608static struct clk_branch gcc_camera_xo_clk = {
1609 .halt_reg = 0x17028,
1610 .halt_check = BRANCH_HALT,
1611 .clkr = {
1612 .enable_reg = 0x17028,
1613 .enable_mask = BIT(0),
1614 .hw.init = &(struct clk_init_data){
1615 .name = "gcc_camera_xo_clk",
1616 .flags = CLK_IS_CRITICAL,
1617 .ops = &clk_branch2_ops,
1618 },
1619 },
1620};
1621
1622static struct clk_branch gcc_camss_axi_clk = {
1623 .halt_reg = 0x58044,
1624 .halt_check = BRANCH_HALT,
1625 .clkr = {
1626 .enable_reg = 0x58044,
1627 .enable_mask = BIT(0),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "gcc_camss_axi_clk",
1630 .parent_hws = (const struct clk_hw *[]){
1631 &gcc_camss_axi_clk_src.clkr.hw,
1632 },
1633 .num_parents = 1,
1634 .flags = CLK_SET_RATE_PARENT,
1635 .ops = &clk_branch2_ops,
1636 },
1637 },
1638};
1639
1640static struct clk_branch gcc_camss_camnoc_atb_clk = {
1641 .halt_reg = 0x5804c,
1642 .halt_check = BRANCH_HALT_DELAY,
1643 .hwcg_reg = 0x5804c,
1644 .hwcg_bit = 1,
1645 .clkr = {
1646 .enable_reg = 0x5804c,
1647 .enable_mask = BIT(0),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "gcc_camss_camnoc_atb_clk",
1650 .ops = &clk_branch2_ops,
1651 },
1652 },
1653};
1654
1655static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {
1656 .halt_reg = 0x58050,
1657 .halt_check = BRANCH_HALT_DELAY,
1658 .hwcg_reg = 0x58050,
1659 .hwcg_bit = 1,
1660 .clkr = {
1661 .enable_reg = 0x58050,
1662 .enable_mask = BIT(0),
1663 .hw.init = &(struct clk_init_data){
1664 .name = "gcc_camss_camnoc_nts_xo_clk",
1665 .ops = &clk_branch2_ops,
1666 },
1667 },
1668};
1669
1670static struct clk_branch gcc_camss_cci_0_clk = {
1671 .halt_reg = 0x56018,
1672 .halt_check = BRANCH_HALT,
1673 .clkr = {
1674 .enable_reg = 0x56018,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "gcc_camss_cci_0_clk",
1678 .parent_hws = (const struct clk_hw *[]){
1679 &gcc_camss_cci_clk_src.clkr.hw,
1680 },
1681 .num_parents = 1,
1682 .flags = CLK_SET_RATE_PARENT,
1683 .ops = &clk_branch2_ops,
1684 },
1685 },
1686};
1687
1688static struct clk_branch gcc_camss_cphy_0_clk = {
1689 .halt_reg = 0x52088,
1690 .halt_check = BRANCH_HALT,
1691 .clkr = {
1692 .enable_reg = 0x52088,
1693 .enable_mask = BIT(0),
1694 .hw.init = &(struct clk_init_data){
1695 .name = "gcc_camss_cphy_0_clk",
1696 .parent_hws = (const struct clk_hw *[]){
1697 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1698 },
1699 .num_parents = 1,
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1702 },
1703 },
1704};
1705
1706static struct clk_branch gcc_camss_cphy_1_clk = {
1707 .halt_reg = 0x5208c,
1708 .halt_check = BRANCH_HALT,
1709 .clkr = {
1710 .enable_reg = 0x5208c,
1711 .enable_mask = BIT(0),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "gcc_camss_cphy_1_clk",
1714 .parent_hws = (const struct clk_hw *[]){
1715 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1716 },
1717 .num_parents = 1,
1718 .flags = CLK_SET_RATE_PARENT,
1719 .ops = &clk_branch2_ops,
1720 },
1721 },
1722};
1723
1724static struct clk_branch gcc_camss_cphy_2_clk = {
1725 .halt_reg = 0x52090,
1726 .halt_check = BRANCH_HALT,
1727 .clkr = {
1728 .enable_reg = 0x52090,
1729 .enable_mask = BIT(0),
1730 .hw.init = &(struct clk_init_data){
1731 .name = "gcc_camss_cphy_2_clk",
1732 .parent_hws = (const struct clk_hw *[]){
1733 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1734 },
1735 .num_parents = 1,
1736 .flags = CLK_SET_RATE_PARENT,
1737 .ops = &clk_branch2_ops,
1738 },
1739 },
1740};
1741
1742static struct clk_branch gcc_camss_csi0phytimer_clk = {
1743 .halt_reg = 0x59018,
1744 .halt_check = BRANCH_HALT,
1745 .clkr = {
1746 .enable_reg = 0x59018,
1747 .enable_mask = BIT(0),
1748 .hw.init = &(struct clk_init_data){
1749 .name = "gcc_camss_csi0phytimer_clk",
1750 .parent_hws = (const struct clk_hw *[]){
1751 &gcc_camss_csi0phytimer_clk_src.clkr.hw,
1752 },
1753 .num_parents = 1,
1754 .flags = CLK_SET_RATE_PARENT,
1755 .ops = &clk_branch2_ops,
1756 },
1757 },
1758};
1759
1760static struct clk_branch gcc_camss_csi1phytimer_clk = {
1761 .halt_reg = 0x59034,
1762 .halt_check = BRANCH_HALT,
1763 .clkr = {
1764 .enable_reg = 0x59034,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "gcc_camss_csi1phytimer_clk",
1768 .parent_hws = (const struct clk_hw *[]){
1769 &gcc_camss_csi1phytimer_clk_src.clkr.hw,
1770 },
1771 .num_parents = 1,
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776};
1777
1778static struct clk_branch gcc_camss_csi2phytimer_clk = {
1779 .halt_reg = 0x59050,
1780 .halt_check = BRANCH_HALT,
1781 .clkr = {
1782 .enable_reg = 0x59050,
1783 .enable_mask = BIT(0),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "gcc_camss_csi2phytimer_clk",
1786 .parent_hws = (const struct clk_hw *[]){
1787 &gcc_camss_csi2phytimer_clk_src.clkr.hw,
1788 },
1789 .num_parents = 1,
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1792 },
1793 },
1794};
1795
1796static struct clk_branch gcc_camss_mclk0_clk = {
1797 .halt_reg = 0x51018,
1798 .halt_check = BRANCH_HALT,
1799 .clkr = {
1800 .enable_reg = 0x51018,
1801 .enable_mask = BIT(0),
1802 .hw.init = &(struct clk_init_data){
1803 .name = "gcc_camss_mclk0_clk",
1804 .parent_hws = (const struct clk_hw *[]){
1805 &gcc_camss_mclk0_clk_src.clkr.hw,
1806 },
1807 .num_parents = 1,
1808 .flags = CLK_SET_RATE_PARENT,
1809 .ops = &clk_branch2_ops,
1810 },
1811 },
1812};
1813
1814static struct clk_branch gcc_camss_mclk1_clk = {
1815 .halt_reg = 0x51034,
1816 .halt_check = BRANCH_HALT,
1817 .clkr = {
1818 .enable_reg = 0x51034,
1819 .enable_mask = BIT(0),
1820 .hw.init = &(struct clk_init_data){
1821 .name = "gcc_camss_mclk1_clk",
1822 .parent_hws = (const struct clk_hw *[]){
1823 &gcc_camss_mclk1_clk_src.clkr.hw,
1824 },
1825 .num_parents = 1,
1826 .flags = CLK_SET_RATE_PARENT,
1827 .ops = &clk_branch2_ops,
1828 },
1829 },
1830};
1831
1832static struct clk_branch gcc_camss_mclk2_clk = {
1833 .halt_reg = 0x51050,
1834 .halt_check = BRANCH_HALT,
1835 .clkr = {
1836 .enable_reg = 0x51050,
1837 .enable_mask = BIT(0),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "gcc_camss_mclk2_clk",
1840 .parent_hws = (const struct clk_hw *[]){
1841 &gcc_camss_mclk2_clk_src.clkr.hw,
1842 },
1843 .num_parents = 1,
1844 .flags = CLK_SET_RATE_PARENT,
1845 .ops = &clk_branch2_ops,
1846 },
1847 },
1848};
1849
1850static struct clk_branch gcc_camss_mclk3_clk = {
1851 .halt_reg = 0x5106c,
1852 .halt_check = BRANCH_HALT,
1853 .clkr = {
1854 .enable_reg = 0x5106c,
1855 .enable_mask = BIT(0),
1856 .hw.init = &(struct clk_init_data){
1857 .name = "gcc_camss_mclk3_clk",
1858 .parent_hws = (const struct clk_hw *[]){
1859 &gcc_camss_mclk3_clk_src.clkr.hw,
1860 },
1861 .num_parents = 1,
1862 .flags = CLK_SET_RATE_PARENT,
1863 .ops = &clk_branch2_ops,
1864 },
1865 },
1866};
1867
1868static struct clk_branch gcc_camss_nrt_axi_clk = {
1869 .halt_reg = 0x58054,
1870 .halt_check = BRANCH_HALT,
1871 .clkr = {
1872 .enable_reg = 0x58054,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_camss_nrt_axi_clk",
1876 .ops = &clk_branch2_ops,
1877 },
1878 },
1879};
1880
1881static struct clk_branch gcc_camss_ope_ahb_clk = {
1882 .halt_reg = 0x5503c,
1883 .halt_check = BRANCH_HALT,
1884 .clkr = {
1885 .enable_reg = 0x5503c,
1886 .enable_mask = BIT(0),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "gcc_camss_ope_ahb_clk",
1889 .parent_hws = (const struct clk_hw *[]){
1890 &gcc_camss_ope_ahb_clk_src.clkr.hw,
1891 },
1892 .num_parents = 1,
1893 .flags = CLK_SET_RATE_PARENT,
1894 .ops = &clk_branch2_ops,
1895 },
1896 },
1897};
1898
1899static struct clk_branch gcc_camss_ope_clk = {
1900 .halt_reg = 0x5501c,
1901 .halt_check = BRANCH_HALT,
1902 .clkr = {
1903 .enable_reg = 0x5501c,
1904 .enable_mask = BIT(0),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "gcc_camss_ope_clk",
1907 .parent_hws = (const struct clk_hw *[]){
1908 &gcc_camss_ope_clk_src.clkr.hw,
1909 },
1910 .num_parents = 1,
1911 .flags = CLK_SET_RATE_PARENT,
1912 .ops = &clk_branch2_ops,
1913 },
1914 },
1915};
1916
1917static struct clk_branch gcc_camss_rt_axi_clk = {
1918 .halt_reg = 0x5805c,
1919 .halt_check = BRANCH_HALT,
1920 .clkr = {
1921 .enable_reg = 0x5805c,
1922 .enable_mask = BIT(0),
1923 .hw.init = &(struct clk_init_data){
1924 .name = "gcc_camss_rt_axi_clk",
1925 .ops = &clk_branch2_ops,
1926 },
1927 },
1928};
1929
1930static struct clk_branch gcc_camss_tfe_0_clk = {
1931 .halt_reg = 0x5201c,
1932 .halt_check = BRANCH_HALT,
1933 .clkr = {
1934 .enable_reg = 0x5201c,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_camss_tfe_0_clk",
1938 .parent_hws = (const struct clk_hw *[]){
1939 &gcc_camss_tfe_0_clk_src.clkr.hw,
1940 },
1941 .num_parents = 1,
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1944 },
1945 },
1946};
1947
1948static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
1949 .halt_reg = 0x5207c,
1950 .halt_check = BRANCH_HALT,
1951 .clkr = {
1952 .enable_reg = 0x5207c,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_camss_tfe_0_cphy_rx_clk",
1956 .parent_hws = (const struct clk_hw *[]){
1957 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1958 },
1959 .num_parents = 1,
1960 .flags = CLK_SET_RATE_PARENT,
1961 .ops = &clk_branch2_ops,
1962 },
1963 },
1964};
1965
1966static struct clk_branch gcc_camss_tfe_0_csid_clk = {
1967 .halt_reg = 0x520ac,
1968 .halt_check = BRANCH_HALT,
1969 .clkr = {
1970 .enable_reg = 0x520ac,
1971 .enable_mask = BIT(0),
1972 .hw.init = &(struct clk_init_data){
1973 .name = "gcc_camss_tfe_0_csid_clk",
1974 .parent_hws = (const struct clk_hw *[]){
1975 &gcc_camss_tfe_0_csid_clk_src.clkr.hw,
1976 },
1977 .num_parents = 1,
1978 .flags = CLK_SET_RATE_PARENT,
1979 .ops = &clk_branch2_ops,
1980 },
1981 },
1982};
1983
1984static struct clk_branch gcc_camss_tfe_1_clk = {
1985 .halt_reg = 0x5203c,
1986 .halt_check = BRANCH_HALT,
1987 .clkr = {
1988 .enable_reg = 0x5203c,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "gcc_camss_tfe_1_clk",
1992 .parent_hws = (const struct clk_hw *[]){
1993 &gcc_camss_tfe_1_clk_src.clkr.hw,
1994 },
1995 .num_parents = 1,
1996 .flags = CLK_SET_RATE_PARENT,
1997 .ops = &clk_branch2_ops,
1998 },
1999 },
2000};
2001
2002static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
2003 .halt_reg = 0x52080,
2004 .halt_check = BRANCH_HALT,
2005 .clkr = {
2006 .enable_reg = 0x52080,
2007 .enable_mask = BIT(0),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "gcc_camss_tfe_1_cphy_rx_clk",
2010 .parent_hws = (const struct clk_hw *[]){
2011 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2012 },
2013 .num_parents = 1,
2014 .flags = CLK_SET_RATE_PARENT,
2015 .ops = &clk_branch2_ops,
2016 },
2017 },
2018};
2019
2020static struct clk_branch gcc_camss_tfe_1_csid_clk = {
2021 .halt_reg = 0x520cc,
2022 .halt_check = BRANCH_HALT,
2023 .clkr = {
2024 .enable_reg = 0x520cc,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gcc_camss_tfe_1_csid_clk",
2028 .parent_hws = (const struct clk_hw *[]){
2029 &gcc_camss_tfe_1_csid_clk_src.clkr.hw,
2030 },
2031 .num_parents = 1,
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_camss_tfe_2_clk = {
2039 .halt_reg = 0x5205c,
2040 .halt_check = BRANCH_HALT,
2041 .clkr = {
2042 .enable_reg = 0x5205c,
2043 .enable_mask = BIT(0),
2044 .hw.init = &(struct clk_init_data){
2045 .name = "gcc_camss_tfe_2_clk",
2046 .parent_hws = (const struct clk_hw *[]){
2047 &gcc_camss_tfe_2_clk_src.clkr.hw,
2048 },
2049 .num_parents = 1,
2050 .flags = CLK_SET_RATE_PARENT,
2051 .ops = &clk_branch2_ops,
2052 },
2053 },
2054};
2055
2056static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {
2057 .halt_reg = 0x52084,
2058 .halt_check = BRANCH_HALT,
2059 .clkr = {
2060 .enable_reg = 0x52084,
2061 .enable_mask = BIT(0),
2062 .hw.init = &(struct clk_init_data){
2063 .name = "gcc_camss_tfe_2_cphy_rx_clk",
2064 .parent_hws = (const struct clk_hw *[]){
2065 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2066 },
2067 .num_parents = 1,
2068 .flags = CLK_SET_RATE_PARENT,
2069 .ops = &clk_branch2_ops,
2070 },
2071 },
2072};
2073
2074static struct clk_branch gcc_camss_tfe_2_csid_clk = {
2075 .halt_reg = 0x520ec,
2076 .halt_check = BRANCH_HALT,
2077 .clkr = {
2078 .enable_reg = 0x520ec,
2079 .enable_mask = BIT(0),
2080 .hw.init = &(struct clk_init_data){
2081 .name = "gcc_camss_tfe_2_csid_clk",
2082 .parent_hws = (const struct clk_hw *[]){
2083 &gcc_camss_tfe_2_csid_clk_src.clkr.hw,
2084 },
2085 .num_parents = 1,
2086 .flags = CLK_SET_RATE_PARENT,
2087 .ops = &clk_branch2_ops,
2088 },
2089 },
2090};
2091
2092static struct clk_branch gcc_camss_top_ahb_clk = {
2093 .halt_reg = 0x58028,
2094 .halt_check = BRANCH_HALT,
2095 .clkr = {
2096 .enable_reg = 0x58028,
2097 .enable_mask = BIT(0),
2098 .hw.init = &(struct clk_init_data){
2099 .name = "gcc_camss_top_ahb_clk",
2100 .parent_hws = (const struct clk_hw *[]){
2101 &gcc_camss_top_ahb_clk_src.clkr.hw,
2102 },
2103 .num_parents = 1,
2104 .flags = CLK_SET_RATE_PARENT,
2105 .ops = &clk_branch2_ops,
2106 },
2107 },
2108};
2109
2110static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2111 .halt_reg = 0x1a084,
2112 .halt_check = BRANCH_HALT,
2113 .hwcg_reg = 0x1a084,
2114 .hwcg_bit = 1,
2115 .clkr = {
2116 .enable_reg = 0x1a084,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
2120 .parent_hws = (const struct clk_hw *[]){
2121 &gcc_usb30_prim_master_clk_src.clkr.hw,
2122 },
2123 .num_parents = 1,
2124 .flags = CLK_SET_RATE_PARENT,
2125 .ops = &clk_branch2_ops,
2126 },
2127 },
2128};
2129
2130static struct clk_branch gcc_cpuss_gnoc_clk = {
2131 .halt_reg = 0x2b004,
2132 .halt_check = BRANCH_HALT_VOTED,
2133 .hwcg_reg = 0x2b004,
2134 .hwcg_bit = 1,
2135 .clkr = {
2136 .enable_reg = 0x79004,
2137 .enable_mask = BIT(22),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_cpuss_gnoc_clk",
2140 .flags = CLK_IS_CRITICAL,
2141 .ops = &clk_branch2_ops,
2142 },
2143 },
2144};
2145
2146static struct clk_branch gcc_disp_ahb_clk = {
2147 .halt_reg = 0x1700c,
2148 .halt_check = BRANCH_HALT,
2149 .hwcg_reg = 0x1700c,
2150 .hwcg_bit = 1,
2151 .clkr = {
2152 .enable_reg = 0x1700c,
2153 .enable_mask = BIT(0),
2154 .hw.init = &(struct clk_init_data){
2155 .name = "gcc_disp_ahb_clk",
2156 .flags = CLK_IS_CRITICAL,
2157 .ops = &clk_branch2_ops,
2158 },
2159 },
2160};
2161
2162static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
2163 .reg = 0x17058,
2164 .shift = 0,
2165 .width = 2,
2166 .clkr.hw.init = &(struct clk_init_data) {
2167 .name = "gcc_disp_gpll0_clk_src",
2168 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2169 .num_parents = 1,
2170 .ops = &clk_regmap_div_ops,
2171 },
2172};
2173
2174static struct clk_branch gcc_disp_gpll0_div_clk_src = {
2175 .halt_check = BRANCH_HALT_DELAY,
2176 .clkr = {
2177 .enable_reg = 0x79004,
2178 .enable_mask = BIT(20),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "gcc_disp_gpll0_div_clk_src",
2181 .parent_hws = (const struct clk_hw *[]){
2182 &gcc_disp_gpll0_clk_src.clkr.hw,
2183 },
2184 .num_parents = 1,
2185 .flags = CLK_SET_RATE_PARENT,
2186 .ops = &clk_branch2_ops,
2187 },
2188 },
2189};
2190
2191static struct clk_branch gcc_disp_hf_axi_clk = {
2192 .halt_reg = 0x17020,
2193 .halt_check = BRANCH_HALT,
2194 .hwcg_reg = 0x17020,
2195 .hwcg_bit = 1,
2196 .clkr = {
2197 .enable_reg = 0x17020,
2198 .enable_mask = BIT(0),
2199 .hw.init = &(struct clk_init_data){
2200 .name = "gcc_disp_hf_axi_clk",
2201 .ops = &clk_branch2_ops,
2202 },
2203 },
2204};
2205
2206static struct clk_branch gcc_disp_throttle_core_clk = {
2207 .halt_reg = 0x17064,
2208 .halt_check = BRANCH_HALT_VOTED,
2209 .hwcg_reg = 0x17064,
2210 .hwcg_bit = 1,
2211 .clkr = {
2212 .enable_reg = 0x7900c,
2213 .enable_mask = BIT(5),
2214 .hw.init = &(struct clk_init_data){
2215 .name = "gcc_disp_throttle_core_clk",
2216 .ops = &clk_branch2_ops,
2217 },
2218 },
2219};
2220
2221static struct clk_branch gcc_disp_xo_clk = {
2222 .halt_reg = 0x1702c,
2223 .halt_check = BRANCH_HALT,
2224 .clkr = {
2225 .enable_reg = 0x1702c,
2226 .enable_mask = BIT(0),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "gcc_disp_xo_clk",
2229 .flags = CLK_IS_CRITICAL,
2230 .ops = &clk_branch2_ops,
2231 },
2232 },
2233};
2234
2235static struct clk_branch gcc_gp1_clk = {
2236 .halt_reg = 0x4d000,
2237 .halt_check = BRANCH_HALT,
2238 .clkr = {
2239 .enable_reg = 0x4d000,
2240 .enable_mask = BIT(0),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "gcc_gp1_clk",
2243 .parent_hws = (const struct clk_hw *[]){
2244 &gcc_gp1_clk_src.clkr.hw,
2245 },
2246 .num_parents = 1,
2247 .flags = CLK_SET_RATE_PARENT,
2248 .ops = &clk_branch2_ops,
2249 },
2250 },
2251};
2252
2253static struct clk_branch gcc_gp2_clk = {
2254 .halt_reg = 0x4e000,
2255 .halt_check = BRANCH_HALT,
2256 .clkr = {
2257 .enable_reg = 0x4e000,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "gcc_gp2_clk",
2261 .parent_hws = (const struct clk_hw *[]){
2262 &gcc_gp2_clk_src.clkr.hw,
2263 },
2264 .num_parents = 1,
2265 .flags = CLK_SET_RATE_PARENT,
2266 .ops = &clk_branch2_ops,
2267 },
2268 },
2269};
2270
2271static struct clk_branch gcc_gp3_clk = {
2272 .halt_reg = 0x4f000,
2273 .halt_check = BRANCH_HALT,
2274 .clkr = {
2275 .enable_reg = 0x4f000,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "gcc_gp3_clk",
2279 .parent_hws = (const struct clk_hw *[]){
2280 &gcc_gp3_clk_src.clkr.hw,
2281 },
2282 .num_parents = 1,
2283 .flags = CLK_SET_RATE_PARENT,
2284 .ops = &clk_branch2_ops,
2285 },
2286 },
2287};
2288
2289static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2290 .halt_reg = 0x36004,
2291 .halt_check = BRANCH_HALT,
2292 .hwcg_reg = 0x36004,
2293 .hwcg_bit = 1,
2294 .clkr = {
2295 .enable_reg = 0x36004,
2296 .enable_mask = BIT(0),
2297 .hw.init = &(struct clk_init_data){
2298 .name = "gcc_gpu_cfg_ahb_clk",
2299 .flags = CLK_IS_CRITICAL,
2300 .ops = &clk_branch2_ops,
2301 },
2302 },
2303};
2304
2305static struct clk_branch gcc_gpu_gpll0_clk_src = {
2306 .halt_check = BRANCH_HALT_DELAY,
2307 .clkr = {
2308 .enable_reg = 0x79004,
2309 .enable_mask = BIT(15),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gcc_gpu_gpll0_clk_src",
2312 .parent_hws = (const struct clk_hw *[]){
2313 &gpll0.clkr.hw,
2314 },
2315 .num_parents = 1,
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2318 },
2319 },
2320};
2321
2322static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2323 .halt_check = BRANCH_HALT_DELAY,
2324 .clkr = {
2325 .enable_reg = 0x79004,
2326 .enable_mask = BIT(16),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gcc_gpu_gpll0_div_clk_src",
2329 .parent_hws = (const struct clk_hw *[]){
2330 &gpll0_out_aux2.clkr.hw,
2331 },
2332 .num_parents = 1,
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2335 },
2336 },
2337};
2338
2339static struct clk_branch gcc_gpu_iref_clk = {
2340 .halt_reg = 0x36100,
2341 .halt_check = BRANCH_HALT_DELAY,
2342 .clkr = {
2343 .enable_reg = 0x36100,
2344 .enable_mask = BIT(0),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "gcc_gpu_iref_clk",
2347 .ops = &clk_branch2_ops,
2348 },
2349 },
2350};
2351
2352static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2353 .halt_reg = 0x3600c,
2354 .halt_check = BRANCH_VOTED,
2355 .hwcg_reg = 0x3600c,
2356 .hwcg_bit = 1,
2357 .clkr = {
2358 .enable_reg = 0x3600c,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(struct clk_init_data){
2361 .name = "gcc_gpu_memnoc_gfx_clk",
2362 .ops = &clk_branch2_ops,
2363 },
2364 },
2365};
2366
2367static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2368 .halt_reg = 0x36018,
2369 .halt_check = BRANCH_HALT,
2370 .clkr = {
2371 .enable_reg = 0x36018,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "gcc_gpu_snoc_dvm_gfx_clk",
2375 .ops = &clk_branch2_ops,
2376 },
2377 },
2378};
2379
2380static struct clk_branch gcc_gpu_throttle_core_clk = {
2381 .halt_reg = 0x36048,
2382 .halt_check = BRANCH_HALT_VOTED,
2383 .hwcg_reg = 0x36048,
2384 .hwcg_bit = 1,
2385 .clkr = {
2386 .enable_reg = 0x79004,
2387 .enable_mask = BIT(31),
2388 .hw.init = &(struct clk_init_data){
2389 .name = "gcc_gpu_throttle_core_clk",
2390 .ops = &clk_branch2_ops,
2391 },
2392 },
2393};
2394
2395static struct clk_branch gcc_pdm2_clk = {
2396 .halt_reg = 0x2000c,
2397 .halt_check = BRANCH_HALT,
2398 .clkr = {
2399 .enable_reg = 0x2000c,
2400 .enable_mask = BIT(0),
2401 .hw.init = &(struct clk_init_data){
2402 .name = "gcc_pdm2_clk",
2403 .parent_hws = (const struct clk_hw *[]){
2404 &gcc_pdm2_clk_src.clkr.hw,
2405 },
2406 .num_parents = 1,
2407 .flags = CLK_SET_RATE_PARENT,
2408 .ops = &clk_branch2_ops,
2409 },
2410 },
2411};
2412
2413static struct clk_branch gcc_pdm_ahb_clk = {
2414 .halt_reg = 0x20004,
2415 .halt_check = BRANCH_HALT,
2416 .hwcg_reg = 0x20004,
2417 .hwcg_bit = 1,
2418 .clkr = {
2419 .enable_reg = 0x20004,
2420 .enable_mask = BIT(0),
2421 .hw.init = &(struct clk_init_data){
2422 .name = "gcc_pdm_ahb_clk",
2423 .ops = &clk_branch2_ops,
2424 },
2425 },
2426};
2427
2428static struct clk_branch gcc_pdm_xo4_clk = {
2429 .halt_reg = 0x20008,
2430 .halt_check = BRANCH_HALT,
2431 .clkr = {
2432 .enable_reg = 0x20008,
2433 .enable_mask = BIT(0),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "gcc_pdm_xo4_clk",
2436 .ops = &clk_branch2_ops,
2437 },
2438 },
2439};
2440
2441static struct clk_branch gcc_prng_ahb_clk = {
2442 .halt_reg = 0x21004,
2443 .halt_check = BRANCH_HALT_VOTED,
2444 .hwcg_reg = 0x21004,
2445 .hwcg_bit = 1,
2446 .clkr = {
2447 .enable_reg = 0x79004,
2448 .enable_mask = BIT(13),
2449 .hw.init = &(struct clk_init_data){
2450 .name = "gcc_prng_ahb_clk",
2451 .ops = &clk_branch2_ops,
2452 },
2453 },
2454};
2455
2456static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2457 .halt_reg = 0x17014,
2458 .halt_check = BRANCH_HALT_VOTED,
2459 .hwcg_reg = 0x17014,
2460 .hwcg_bit = 1,
2461 .clkr = {
2462 .enable_reg = 0x7900c,
2463 .enable_mask = BIT(0),
2464 .hw.init = &(struct clk_init_data){
2465 .name = "gcc_qmip_camera_nrt_ahb_clk",
2466 .ops = &clk_branch2_ops,
2467 },
2468 },
2469};
2470
2471static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2472 .halt_reg = 0x17060,
2473 .halt_check = BRANCH_HALT_VOTED,
2474 .hwcg_reg = 0x17060,
2475 .hwcg_bit = 1,
2476 .clkr = {
2477 .enable_reg = 0x7900c,
2478 .enable_mask = BIT(2),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "gcc_qmip_camera_rt_ahb_clk",
2481 .ops = &clk_branch2_ops,
2482 },
2483 },
2484};
2485
2486static struct clk_branch gcc_qmip_disp_ahb_clk = {
2487 .halt_reg = 0x17018,
2488 .halt_check = BRANCH_HALT_VOTED,
2489 .hwcg_reg = 0x17018,
2490 .hwcg_bit = 1,
2491 .clkr = {
2492 .enable_reg = 0x7900c,
2493 .enable_mask = BIT(1),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "gcc_qmip_disp_ahb_clk",
2496 .ops = &clk_branch2_ops,
2497 },
2498 },
2499};
2500
2501static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2502 .halt_reg = 0x36040,
2503 .halt_check = BRANCH_HALT_VOTED,
2504 .hwcg_reg = 0x36040,
2505 .hwcg_bit = 1,
2506 .clkr = {
2507 .enable_reg = 0x7900c,
2508 .enable_mask = BIT(4),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_qmip_gpu_cfg_ahb_clk",
2511 .ops = &clk_branch2_ops,
2512 },
2513 },
2514};
2515
2516static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2517 .halt_reg = 0x17010,
2518 .halt_check = BRANCH_HALT_VOTED,
2519 .hwcg_reg = 0x17010,
2520 .hwcg_bit = 1,
2521 .clkr = {
2522 .enable_reg = 0x79004,
2523 .enable_mask = BIT(25),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "gcc_qmip_video_vcodec_ahb_clk",
2526 .ops = &clk_branch2_ops,
2527 },
2528 },
2529};
2530
2531static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2532 .halt_reg = 0x1f014,
2533 .halt_check = BRANCH_HALT_VOTED,
2534 .clkr = {
2535 .enable_reg = 0x7900c,
2536 .enable_mask = BIT(9),
2537 .hw.init = &(struct clk_init_data){
2538 .name = "gcc_qupv3_wrap0_core_2x_clk",
2539 .ops = &clk_branch2_ops,
2540 },
2541 },
2542};
2543
2544static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2545 .halt_reg = 0x1f00c,
2546 .halt_check = BRANCH_HALT_VOTED,
2547 .clkr = {
2548 .enable_reg = 0x7900c,
2549 .enable_mask = BIT(8),
2550 .hw.init = &(struct clk_init_data){
2551 .name = "gcc_qupv3_wrap0_core_clk",
2552 .ops = &clk_branch2_ops,
2553 },
2554 },
2555};
2556
2557static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2558 .halt_reg = 0x1f144,
2559 .halt_check = BRANCH_HALT_VOTED,
2560 .clkr = {
2561 .enable_reg = 0x7900c,
2562 .enable_mask = BIT(10),
2563 .hw.init = &(struct clk_init_data){
2564 .name = "gcc_qupv3_wrap0_s0_clk",
2565 .parent_hws = (const struct clk_hw *[]){
2566 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2567 },
2568 .num_parents = 1,
2569 .flags = CLK_SET_RATE_PARENT,
2570 .ops = &clk_branch2_ops,
2571 },
2572 },
2573};
2574
2575static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2576 .halt_reg = 0x1f274,
2577 .halt_check = BRANCH_HALT_VOTED,
2578 .clkr = {
2579 .enable_reg = 0x7900c,
2580 .enable_mask = BIT(11),
2581 .hw.init = &(struct clk_init_data){
2582 .name = "gcc_qupv3_wrap0_s1_clk",
2583 .parent_hws = (const struct clk_hw *[]){
2584 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2585 },
2586 .num_parents = 1,
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2589 },
2590 },
2591};
2592
2593static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2594 .halt_reg = 0x1f3a4,
2595 .halt_check = BRANCH_HALT_VOTED,
2596 .clkr = {
2597 .enable_reg = 0x7900c,
2598 .enable_mask = BIT(12),
2599 .hw.init = &(struct clk_init_data){
2600 .name = "gcc_qupv3_wrap0_s2_clk",
2601 .parent_hws = (const struct clk_hw *[]){
2602 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2603 },
2604 .num_parents = 1,
2605 .flags = CLK_SET_RATE_PARENT,
2606 .ops = &clk_branch2_ops,
2607 },
2608 },
2609};
2610
2611static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2612 .halt_reg = 0x1f4d4,
2613 .halt_check = BRANCH_HALT_VOTED,
2614 .clkr = {
2615 .enable_reg = 0x7900c,
2616 .enable_mask = BIT(13),
2617 .hw.init = &(struct clk_init_data){
2618 .name = "gcc_qupv3_wrap0_s3_clk",
2619 .parent_hws = (const struct clk_hw *[]){
2620 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2621 },
2622 .num_parents = 1,
2623 .flags = CLK_SET_RATE_PARENT,
2624 .ops = &clk_branch2_ops,
2625 },
2626 },
2627};
2628
2629static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2630 .halt_reg = 0x1f604,
2631 .halt_check = BRANCH_HALT_VOTED,
2632 .clkr = {
2633 .enable_reg = 0x7900c,
2634 .enable_mask = BIT(14),
2635 .hw.init = &(struct clk_init_data){
2636 .name = "gcc_qupv3_wrap0_s4_clk",
2637 .parent_hws = (const struct clk_hw *[]){
2638 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2639 },
2640 .num_parents = 1,
2641 .flags = CLK_SET_RATE_PARENT,
2642 .ops = &clk_branch2_ops,
2643 },
2644 },
2645};
2646
2647static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2648 .halt_reg = 0x1f734,
2649 .halt_check = BRANCH_HALT_VOTED,
2650 .clkr = {
2651 .enable_reg = 0x7900c,
2652 .enable_mask = BIT(15),
2653 .hw.init = &(struct clk_init_data){
2654 .name = "gcc_qupv3_wrap0_s5_clk",
2655 .parent_hws = (const struct clk_hw *[]){
2656 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2657 },
2658 .num_parents = 1,
2659 .flags = CLK_SET_RATE_PARENT,
2660 .ops = &clk_branch2_ops,
2661 },
2662 },
2663};
2664
2665static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2666 .halt_reg = 0x1f004,
2667 .halt_check = BRANCH_HALT_VOTED,
2668 .hwcg_reg = 0x1f004,
2669 .hwcg_bit = 1,
2670 .clkr = {
2671 .enable_reg = 0x7900c,
2672 .enable_mask = BIT(6),
2673 .hw.init = &(struct clk_init_data){
2674 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2675 .ops = &clk_branch2_ops,
2676 },
2677 },
2678};
2679
2680static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2681 .halt_reg = 0x1f008,
2682 .halt_check = BRANCH_HALT_VOTED,
2683 .hwcg_reg = 0x1f008,
2684 .hwcg_bit = 1,
2685 .clkr = {
2686 .enable_reg = 0x7900c,
2687 .enable_mask = BIT(7),
2688 .hw.init = &(struct clk_init_data){
2689 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2690 .ops = &clk_branch2_ops,
2691 },
2692 },
2693};
2694
2695static struct clk_branch gcc_sdcc1_ahb_clk = {
2696 .halt_reg = 0x38008,
2697 .halt_check = BRANCH_HALT,
2698 .clkr = {
2699 .enable_reg = 0x38008,
2700 .enable_mask = BIT(0),
2701 .hw.init = &(struct clk_init_data){
2702 .name = "gcc_sdcc1_ahb_clk",
2703 .ops = &clk_branch2_ops,
2704 },
2705 },
2706};
2707
2708static struct clk_branch gcc_sdcc1_apps_clk = {
2709 .halt_reg = 0x38004,
2710 .halt_check = BRANCH_HALT,
2711 .clkr = {
2712 .enable_reg = 0x38004,
2713 .enable_mask = BIT(0),
2714 .hw.init = &(struct clk_init_data){
2715 .name = "gcc_sdcc1_apps_clk",
2716 .parent_hws = (const struct clk_hw *[]){
2717 &gcc_sdcc1_apps_clk_src.clkr.hw,
2718 },
2719 .num_parents = 1,
2720 .flags = CLK_SET_RATE_PARENT ,
2721 .ops = &clk_branch2_ops,
2722 },
2723 },
2724};
2725
2726static struct clk_branch gcc_sdcc1_ice_core_clk = {
2727 .halt_reg = 0x3800c,
2728 .halt_check = BRANCH_HALT,
2729 .hwcg_reg = 0x3800c,
2730 .hwcg_bit = 1,
2731 .clkr = {
2732 .enable_reg = 0x3800c,
2733 .enable_mask = BIT(0),
2734 .hw.init = &(struct clk_init_data){
2735 .name = "gcc_sdcc1_ice_core_clk",
2736 .parent_hws = (const struct clk_hw *[]){
2737 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2738 },
2739 .num_parents = 1,
2740 .flags = CLK_SET_RATE_PARENT,
2741 .ops = &clk_branch2_ops,
2742 },
2743 },
2744};
2745
2746static struct clk_branch gcc_sdcc2_ahb_clk = {
2747 .halt_reg = 0x1e008,
2748 .halt_check = BRANCH_HALT,
2749 .clkr = {
2750 .enable_reg = 0x1e008,
2751 .enable_mask = BIT(0),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "gcc_sdcc2_ahb_clk",
2754 .ops = &clk_branch2_ops,
2755 },
2756 },
2757};
2758
2759static struct clk_branch gcc_sdcc2_apps_clk = {
2760 .halt_reg = 0x1e004,
2761 .halt_check = BRANCH_HALT,
2762 .clkr = {
2763 .enable_reg = 0x1e004,
2764 .enable_mask = BIT(0),
2765 .hw.init = &(struct clk_init_data){
2766 .name = "gcc_sdcc2_apps_clk",
2767 .parent_hws = (const struct clk_hw *[]){
2768 &gcc_sdcc2_apps_clk_src.clkr.hw,
2769 },
2770 .num_parents = 1,
2771 .flags = CLK_SET_RATE_PARENT,
2772 .ops = &clk_branch2_ops,
2773 },
2774 },
2775};
2776
2777static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2778 .halt_reg = 0x2b06c,
2779 .halt_check = BRANCH_HALT_VOTED,
2780 .hwcg_reg = 0x2b06c,
2781 .hwcg_bit = 1,
2782 .clkr = {
2783 .enable_reg = 0x79004,
2784 .enable_mask = BIT(0),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "gcc_sys_noc_cpuss_ahb_clk",
2787 .flags = CLK_IS_CRITICAL,
2788 .ops = &clk_branch2_ops,
2789 },
2790 },
2791};
2792
2793static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
2794 .halt_reg = 0x45098,
2795 .halt_check = BRANCH_HALT,
2796 .clkr = {
2797 .enable_reg = 0x45098,
2798 .enable_mask = BIT(0),
2799 .hw.init = &(struct clk_init_data){
2800 .name = "gcc_sys_noc_ufs_phy_axi_clk",
2801 .parent_hws = (const struct clk_hw *[]){
2802 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2803 },
2804 .num_parents = 1,
2805 .flags = CLK_SET_RATE_PARENT,
2806 .ops = &clk_branch2_ops,
2807 },
2808 },
2809};
2810
2811static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
2812 .halt_reg = 0x1a080,
2813 .halt_check = BRANCH_HALT,
2814 .hwcg_reg = 0x1a080,
2815 .hwcg_bit = 1,
2816 .clkr = {
2817 .enable_reg = 0x1a080,
2818 .enable_mask = BIT(0),
2819 .hw.init = &(struct clk_init_data){
2820 .name = "gcc_sys_noc_usb3_prim_axi_clk",
2821 .parent_hws = (const struct clk_hw *[]){
2822 &gcc_usb30_prim_master_clk_src.clkr.hw,
2823 },
2824 .num_parents = 1,
2825 .flags = CLK_SET_RATE_PARENT,
2826 .ops = &clk_branch2_ops,
2827 },
2828 },
2829};
2830
2831static struct clk_branch gcc_ufs_clkref_clk = {
2832 .halt_reg = 0x8c000,
2833 .halt_check = BRANCH_HALT,
2834 .clkr = {
2835 .enable_reg = 0x8c000,
2836 .enable_mask = BIT(0),
2837 .hw.init = &(struct clk_init_data){
2838 .name = "gcc_ufs_clkref_clk",
2839 .ops = &clk_branch2_ops,
2840 },
2841 },
2842};
2843
2844static struct clk_branch gcc_ufs_phy_ahb_clk = {
2845 .halt_reg = 0x45014,
2846 .halt_check = BRANCH_HALT,
2847 .hwcg_reg = 0x45014,
2848 .hwcg_bit = 1,
2849 .clkr = {
2850 .enable_reg = 0x45014,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "gcc_ufs_phy_ahb_clk",
2854 .ops = &clk_branch2_ops,
2855 },
2856 },
2857};
2858
2859static struct clk_branch gcc_ufs_phy_axi_clk = {
2860 .halt_reg = 0x45010,
2861 .halt_check = BRANCH_HALT,
2862 .hwcg_reg = 0x45010,
2863 .hwcg_bit = 1,
2864 .clkr = {
2865 .enable_reg = 0x45010,
2866 .enable_mask = BIT(0),
2867 .hw.init = &(struct clk_init_data){
2868 .name = "gcc_ufs_phy_axi_clk",
2869 .parent_hws = (const struct clk_hw *[]){
2870 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2871 },
2872 .num_parents = 1,
2873 .flags = CLK_SET_RATE_PARENT,
2874 .ops = &clk_branch2_ops,
2875 },
2876 },
2877};
2878
2879static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2880 .halt_reg = 0x45044,
2881 .halt_check = BRANCH_HALT,
2882 .hwcg_reg = 0x45044,
2883 .hwcg_bit = 1,
2884 .clkr = {
2885 .enable_reg = 0x45044,
2886 .enable_mask = BIT(0),
2887 .hw.init = &(struct clk_init_data){
2888 .name = "gcc_ufs_phy_ice_core_clk",
2889 .parent_hws = (const struct clk_hw *[]){
2890 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2891 },
2892 .num_parents = 1,
2893 .flags = CLK_SET_RATE_PARENT,
2894 .ops = &clk_branch2_ops,
2895 },
2896 },
2897};
2898
2899static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2900 .halt_reg = 0x45078,
2901 .halt_check = BRANCH_HALT,
2902 .hwcg_reg = 0x45078,
2903 .hwcg_bit = 1,
2904 .clkr = {
2905 .enable_reg = 0x45078,
2906 .enable_mask = BIT(0),
2907 .hw.init = &(struct clk_init_data){
2908 .name = "gcc_ufs_phy_phy_aux_clk",
2909 .parent_hws = (const struct clk_hw *[]){
2910 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2911 },
2912 .num_parents = 1,
2913 .flags = CLK_SET_RATE_PARENT,
2914 .ops = &clk_branch2_ops,
2915 },
2916 },
2917};
2918
2919static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2920 .halt_reg = 0x4501c,
2921 .halt_check = BRANCH_HALT_SKIP,
2922 .clkr = {
2923 .enable_reg = 0x4501c,
2924 .enable_mask = BIT(0),
2925 .hw.init = &(struct clk_init_data){
2926 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2927 .ops = &clk_branch2_ops,
2928 },
2929 },
2930};
2931
2932static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2933 .halt_reg = 0x45018,
2934 .halt_check = BRANCH_HALT_SKIP,
2935 .clkr = {
2936 .enable_reg = 0x45018,
2937 .enable_mask = BIT(0),
2938 .hw.init = &(struct clk_init_data){
2939 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2940 .ops = &clk_branch2_ops,
2941 },
2942 },
2943};
2944
2945static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2946 .halt_reg = 0x45040,
2947 .halt_check = BRANCH_HALT,
2948 .hwcg_reg = 0x45040,
2949 .hwcg_bit = 1,
2950 .clkr = {
2951 .enable_reg = 0x45040,
2952 .enable_mask = BIT(0),
2953 .hw.init = &(struct clk_init_data){
2954 .name = "gcc_ufs_phy_unipro_core_clk",
2955 .parent_hws = (const struct clk_hw *[]){
2956 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2957 },
2958 .num_parents = 1,
2959 .flags = CLK_SET_RATE_PARENT,
2960 .ops = &clk_branch2_ops,
2961 },
2962 },
2963};
2964
2965static struct clk_branch gcc_usb30_prim_master_clk = {
2966 .halt_reg = 0x1a010,
2967 .halt_check = BRANCH_HALT,
2968 .clkr = {
2969 .enable_reg = 0x1a010,
2970 .enable_mask = BIT(0),
2971 .hw.init = &(struct clk_init_data){
2972 .name = "gcc_usb30_prim_master_clk",
2973 .parent_hws = (const struct clk_hw *[]){
2974 &gcc_usb30_prim_master_clk_src.clkr.hw,
2975 },
2976 .num_parents = 1,
2977 .flags = CLK_SET_RATE_PARENT,
2978 .ops = &clk_branch2_ops,
2979 },
2980 },
2981};
2982
2983static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2984 .halt_reg = 0x1a018,
2985 .halt_check = BRANCH_HALT,
2986 .clkr = {
2987 .enable_reg = 0x1a018,
2988 .enable_mask = BIT(0),
2989 .hw.init = &(struct clk_init_data){
2990 .name = "gcc_usb30_prim_mock_utmi_clk",
2991 .parent_hws = (const struct clk_hw *[]){
2992 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2993 },
2994 .num_parents = 1,
2995 .flags = CLK_SET_RATE_PARENT,
2996 .ops = &clk_branch2_ops,
2997 },
2998 },
2999};
3000
3001static struct clk_branch gcc_usb30_prim_sleep_clk = {
3002 .halt_reg = 0x1a014,
3003 .halt_check = BRANCH_HALT,
3004 .clkr = {
3005 .enable_reg = 0x1a014,
3006 .enable_mask = BIT(0),
3007 .hw.init = &(struct clk_init_data){
3008 .name = "gcc_usb30_prim_sleep_clk",
3009 .ops = &clk_branch2_ops,
3010 },
3011 },
3012};
3013
3014static struct clk_branch gcc_usb3_prim_clkref_clk = {
3015 .halt_reg = 0x9f000,
3016 .halt_check = BRANCH_HALT,
3017 .clkr = {
3018 .enable_reg = 0x9f000,
3019 .enable_mask = BIT(0),
3020 .hw.init = &(struct clk_init_data){
3021 .name = "gcc_usb3_prim_clkref_clk",
3022 .ops = &clk_branch2_ops,
3023 },
3024 },
3025};
3026
3027static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3028 .halt_reg = 0x1a054,
3029 .halt_check = BRANCH_HALT,
3030 .clkr = {
3031 .enable_reg = 0x1a054,
3032 .enable_mask = BIT(0),
3033 .hw.init = &(struct clk_init_data){
3034 .name = "gcc_usb3_prim_phy_com_aux_clk",
3035 .parent_hws = (const struct clk_hw *[]){
3036 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3037 },
3038 .num_parents = 1,
3039 .flags = CLK_SET_RATE_PARENT,
3040 .ops = &clk_branch2_ops,
3041 },
3042 },
3043};
3044
3045static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3046 .halt_reg = 0x1a058,
3047 .halt_check = BRANCH_HALT_SKIP,
3048 .hwcg_reg = 0x1a058,
3049 .hwcg_bit = 1,
3050 .clkr = {
3051 .enable_reg = 0x1a058,
3052 .enable_mask = BIT(0),
3053 .hw.init = &(struct clk_init_data){
3054 .name = "gcc_usb3_prim_phy_pipe_clk",
3055 .ops = &clk_branch2_ops,
3056 },
3057 },
3058};
3059
3060static struct clk_branch gcc_vcodec0_axi_clk = {
3061 .halt_reg = 0x6e008,
3062 .halt_check = BRANCH_HALT,
3063 .clkr = {
3064 .enable_reg = 0x6e008,
3065 .enable_mask = BIT(0),
3066 .hw.init = &(struct clk_init_data){
3067 .name = "gcc_vcodec0_axi_clk",
3068 .ops = &clk_branch2_ops,
3069 },
3070 },
3071};
3072
3073static struct clk_branch gcc_venus_ahb_clk = {
3074 .halt_reg = 0x6e010,
3075 .halt_check = BRANCH_HALT,
3076 .clkr = {
3077 .enable_reg = 0x6e010,
3078 .enable_mask = BIT(0),
3079 .hw.init = &(struct clk_init_data){
3080 .name = "gcc_venus_ahb_clk",
3081 .ops = &clk_branch2_ops,
3082 },
3083 },
3084};
3085
3086static struct clk_branch gcc_venus_ctl_axi_clk = {
3087 .halt_reg = 0x6e004,
3088 .halt_check = BRANCH_HALT,
3089 .clkr = {
3090 .enable_reg = 0x6e004,
3091 .enable_mask = BIT(0),
3092 .hw.init = &(struct clk_init_data){
3093 .name = "gcc_venus_ctl_axi_clk",
3094 .ops = &clk_branch2_ops,
3095 },
3096 },
3097};
3098
3099static struct clk_branch gcc_video_ahb_clk = {
3100 .halt_reg = 0x17004,
3101 .halt_check = BRANCH_HALT,
3102 .hwcg_reg = 0x17004,
3103 .hwcg_bit = 1,
3104 .clkr = {
3105 .enable_reg = 0x17004,
3106 .enable_mask = BIT(0),
3107 .hw.init = &(struct clk_init_data){
3108 .name = "gcc_video_ahb_clk",
3109 .ops = &clk_branch2_ops,
3110 },
3111 },
3112};
3113
3114static struct clk_branch gcc_video_axi0_clk = {
3115 .halt_reg = 0x1701c,
3116 .halt_check = BRANCH_HALT,
3117 .hwcg_reg = 0x1701c,
3118 .hwcg_bit = 1,
3119 .clkr = {
3120 .enable_reg = 0x1701c,
3121 .enable_mask = BIT(0),
3122 .hw.init = &(struct clk_init_data){
3123 .name = "gcc_video_axi0_clk",
3124 .ops = &clk_branch2_ops,
3125 },
3126 },
3127};
3128
3129static struct clk_branch gcc_video_throttle_core_clk = {
3130 .halt_reg = 0x17068,
3131 .halt_check = BRANCH_HALT_VOTED,
3132 .hwcg_reg = 0x17068,
3133 .hwcg_bit = 1,
3134 .clkr = {
3135 .enable_reg = 0x79004,
3136 .enable_mask = BIT(28),
3137 .hw.init = &(struct clk_init_data){
3138 .name = "gcc_video_throttle_core_clk",
3139 .ops = &clk_branch2_ops,
3140 },
3141 },
3142};
3143
3144static struct clk_branch gcc_video_vcodec0_sys_clk = {
3145 .halt_reg = 0x580a4,
3146 .halt_check = BRANCH_HALT_DELAY,
3147 .hwcg_reg = 0x580a4,
3148 .hwcg_bit = 1,
3149 .clkr = {
3150 .enable_reg = 0x580a4,
3151 .enable_mask = BIT(0),
3152 .hw.init = &(struct clk_init_data){
3153 .name = "gcc_video_vcodec0_sys_clk",
3154 .parent_hws = (const struct clk_hw *[]){
3155 &gcc_video_venus_clk_src.clkr.hw,
3156 },
3157 .num_parents = 1,
3158 .flags = CLK_SET_RATE_PARENT,
3159 .ops = &clk_branch2_ops,
3160 },
3161 },
3162};
3163
3164static struct clk_branch gcc_video_venus_ctl_clk = {
3165 .halt_reg = 0x5808c,
3166 .halt_check = BRANCH_HALT,
3167 .clkr = {
3168 .enable_reg = 0x5808c,
3169 .enable_mask = BIT(0),
3170 .hw.init = &(struct clk_init_data){
3171 .name = "gcc_video_venus_ctl_clk",
3172 .parent_hws = (const struct clk_hw *[]){
3173 &gcc_video_venus_clk_src.clkr.hw,
3174 },
3175 .num_parents = 1,
3176 .flags = CLK_SET_RATE_PARENT,
3177 .ops = &clk_branch2_ops,
3178 },
3179 },
3180};
3181
3182static struct clk_branch gcc_video_xo_clk = {
3183 .halt_reg = 0x17024,
3184 .halt_check = BRANCH_HALT,
3185 .clkr = {
3186 .enable_reg = 0x17024,
3187 .enable_mask = BIT(0),
3188 .hw.init = &(struct clk_init_data){
3189 .name = "gcc_video_xo_clk",
3190 .ops = &clk_branch2_ops,
3191 },
3192 },
3193};
3194
3195static struct gdsc gcc_camss_top_gdsc = {
3196 .gdscr = 0x58004,
3197 .pd = {
3198 .name = "gcc_camss_top",
3199 },
3200 .pwrsts = PWRSTS_OFF_ON,
3201};
3202
3203static struct gdsc gcc_ufs_phy_gdsc = {
3204 .gdscr = 0x45004,
3205 .pd = {
3206 .name = "gcc_ufs_phy",
3207 },
3208 .pwrsts = PWRSTS_OFF_ON,
3209};
3210
3211static struct gdsc gcc_usb30_prim_gdsc = {
3212 .gdscr = 0x1a004,
3213 .pd = {
3214 .name = "gcc_usb30_prim",
3215 },
3216 .pwrsts = PWRSTS_OFF_ON,
3217};
3218
3219static struct gdsc gcc_vcodec0_gdsc = {
3220 .gdscr = 0x58098,
3221 .pd = {
3222 .name = "gcc_vcodec0",
3223 },
3224 .pwrsts = PWRSTS_OFF_ON,
3225};
3226
3227static struct gdsc gcc_venus_gdsc = {
3228 .gdscr = 0x5807c,
3229 .pd = {
3230 .name = "gcc_venus",
3231 },
3232 .pwrsts = PWRSTS_OFF_ON,
3233};
3234
3235static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3236 .gdscr = 0x7d060,
3237 .pd = {
3238 .name = "hlos1_vote_turing_mmu_tbu1",
3239 },
3240 .pwrsts = PWRSTS_OFF_ON,
3241 .flags = VOTABLE,
3242};
3243
3244static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3245 .gdscr = 0x7d07c,
3246 .pd = {
3247 .name = "hlos1_vote_turing_mmu_tbu0",
3248 },
3249 .pwrsts = PWRSTS_OFF_ON,
3250 .flags = VOTABLE,
3251};
3252
3253static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
3254 .gdscr = 0x7d074,
3255 .pd = {
3256 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt",
3257 },
3258 .pwrsts = PWRSTS_OFF_ON,
3259 .flags = VOTABLE,
3260};
3261
3262static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
3263 .gdscr = 0x7d078,
3264 .pd = {
3265 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt",
3266 },
3267 .pwrsts = PWRSTS_OFF_ON,
3268 .flags = VOTABLE,
3269};
3270
3271static struct clk_regmap *gcc_sm6115_clocks[] = {
3272 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
3273 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
3274 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
3275 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3276 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
3277 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
3278 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3279 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3280 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
3281 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
3282 [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
3283 [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,
3284 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
3285 [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
3286 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
3287 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
3288 [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr,
3289 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3290 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
3291 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3292 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
3293 [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
3294 [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
3295 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3296 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
3297 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3298 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
3299 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3300 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
3301 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
3302 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
3303 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
3304 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
3305 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
3306 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
3307 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
3308 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
3309 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
3310 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
3311 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
3312 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
3313 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
3314 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
3315 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
3316 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
3317 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
3318 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
3319 [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr,
3320 [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr,
3321 [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr,
3322 [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr,
3323 [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr,
3324 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
3325 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3326 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
3327 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3328 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3329 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3330 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3331 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3332 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3333 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
3334 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3335 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3336 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3337 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3338 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3339 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3340 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3341 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3342 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3343 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3344 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3345 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3346 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3347 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
3348 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3349 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3350 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3351 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3352 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3353 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3354 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3355 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3356 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
3357 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3358 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3359 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3360 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3361 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3362 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3363 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3364 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3365 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3366 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3367 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3368 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3369 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3370 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3371 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3372 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3373 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3374 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3375 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3376 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3377 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3378 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3379 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3380 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3381 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3382 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3383 [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
3384 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
3385 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3386 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3387 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3388 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3389 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3390 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3391 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3392 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3393 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3394 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3395 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3396 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3397 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3398 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3399 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3400 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3401 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3402 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3403 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3404 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3405 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3406 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3407 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3408 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3409 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3410 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
3411 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
3412 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
3413 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3414 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3415 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
3416 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
3417 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
3418 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
3419 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3420 [GPLL0] = &gpll0.clkr,
3421 [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr,
3422 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
3423 [GPLL10] = &gpll10.clkr,
3424 [GPLL10_OUT_MAIN] = &gpll10_out_main.clkr,
3425 [GPLL11] = &gpll11.clkr,
3426 [GPLL11_OUT_MAIN] = &gpll11_out_main.clkr,
3427 [GPLL3] = &gpll3.clkr,
3428 [GPLL4] = &gpll4.clkr,
3429 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
3430 [GPLL6] = &gpll6.clkr,
3431 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
3432 [GPLL7] = &gpll7.clkr,
3433 [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr,
3434 [GPLL8] = &gpll8.clkr,
3435 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
3436 [GPLL9] = &gpll9.clkr,
3437 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
3438};
3439
3440static const struct qcom_reset_map gcc_sm6115_resets[] = {
3441 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3442 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3443 [GCC_SDCC1_BCR] = { 0x38000 },
3444 [GCC_SDCC2_BCR] = { 0x1e000 },
3445 [GCC_UFS_PHY_BCR] = { 0x45000 },
3446 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
3447 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3448 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
3449 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3450 [GCC_VCODEC0_BCR] = { 0x58094 },
3451 [GCC_VENUS_BCR] = { 0x58078 },
3452 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3453};
3454
3455static struct gdsc *gcc_sm6115_gdscs[] = {
3456 [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc,
3457 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3458 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3459 [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,
3460 [GCC_VENUS_GDSC] = &gcc_venus_gdsc,
3461 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3462 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3463 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
3464 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
3465};
3466
3467static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3468 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3469 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3470 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3471 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3472 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3473 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3474};
3475
3476static const struct regmap_config gcc_sm6115_regmap_config = {
3477 .reg_bits = 32,
3478 .reg_stride = 4,
3479 .val_bits = 32,
3480 .max_register = 0xc7000,
3481 .fast_io = true,
3482};
3483
3484static const struct qcom_cc_desc gcc_sm6115_desc = {
3485 .config = &gcc_sm6115_regmap_config,
3486 .clks = gcc_sm6115_clocks,
3487 .num_clks = ARRAY_SIZE(gcc_sm6115_clocks),
3488 .resets = gcc_sm6115_resets,
3489 .num_resets = ARRAY_SIZE(gcc_sm6115_resets),
3490 .gdscs = gcc_sm6115_gdscs,
3491 .num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs),
3492};
3493
3494static const struct of_device_id gcc_sm6115_match_table[] = {
3495 { .compatible = "qcom,gcc-sm6115" },
3496 { }
3497};
3498MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table);
3499
3500static int gcc_sm6115_probe(struct platform_device *pdev)
3501{
3502 struct regmap *regmap;
3503 int ret;
3504
3505 regmap = qcom_cc_map(pdev, &gcc_sm6115_desc);
3506 if (IS_ERR(regmap))
3507 return PTR_ERR(regmap);
3508
3509 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3510 ARRAY_SIZE(gcc_dfs_clocks));
3511 if (ret)
3512 return ret;
3513
3514 clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
3515 clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
3516 clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
3517 clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
3518
3519 return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap);
3520}
3521
3522static struct platform_driver gcc_sm6115_driver = {
3523 .probe = gcc_sm6115_probe,
3524 .driver = {
3525 .name = "gcc-sm6115",
3526 .of_match_table = gcc_sm6115_match_table,
3527 },
3528};
3529
3530static int __init gcc_sm6115_init(void)
3531{
3532 return platform_driver_register(&gcc_sm6115_driver);
3533}
3534subsys_initcall(gcc_sm6115_init);
3535
3536static void __exit gcc_sm6115_exit(void)
3537{
3538 platform_driver_unregister(&gcc_sm6115_driver);
3539}
3540module_exit(gcc_sm6115_exit);
3541
3542MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver");
3543MODULE_LICENSE("GPL v2");
3544MODULE_ALIAS("platform:gcc-sm6115");
3545