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8#include <linux/clk-provider.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/kernel.h>
12
13#include <dt-bindings/clock/r9a07g044-cpg.h>
14
15#include "rzg2l-cpg.h"
16
17enum clk_ids {
18
19 LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
20
21
22 CLK_EXTAL,
23
24
25 CLK_OSC_DIV1000,
26 CLK_PLL1,
27 CLK_PLL2,
28 CLK_PLL2_DIV2,
29 CLK_PLL2_DIV16,
30 CLK_PLL2_DIV20,
31 CLK_PLL3,
32 CLK_PLL3_DIV2,
33 CLK_PLL3_DIV2_4,
34 CLK_PLL3_DIV2_4_2,
35 CLK_PLL3_DIV4,
36 CLK_PLL4,
37 CLK_PLL5,
38 CLK_PLL5_DIV2,
39 CLK_PLL6,
40 CLK_P1_DIV2,
41
42
43 MOD_CLK_BASE,
44};
45
46
47static const struct clk_div_table dtable_1_32[] = {
48 {0, 1},
49 {1, 2},
50 {2, 4},
51 {3, 8},
52 {4, 32},
53 {0, 0},
54};
55
56static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
57
58 DEF_INPUT("extal", CLK_EXTAL),
59
60
61 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
62 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
63 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
64 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
65 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
66
67 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
68 DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
69 DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
70
71 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
72 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
73 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
74 DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
75
76
77 DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
78 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
79 dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
80 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
81 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
82 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
83 DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
84 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
85 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
86 DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
87};
88
89static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
90 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
91 0x514, 0),
92 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
93 0x518, 0),
94 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
95 0x518, 1),
96 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
97 0x52c, 0),
98 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
99 0x52c, 1),
100 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
101 0x570, 0),
102 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
103 0x570, 1),
104 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
105 0x570, 2),
106 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
107 0x570, 3),
108 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
109 0x570, 4),
110 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
111 0x570, 5),
112 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
113 0x570, 6),
114 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
115 0x570, 7),
116 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
117 0x578, 0),
118 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
119 0x578, 1),
120 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
121 0x578, 2),
122 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
123 0x578, 3),
124 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
125 0x580, 0),
126 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
127 0x580, 1),
128 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
129 0x580, 2),
130 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
131 0x580, 3),
132 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
133 0x584, 0),
134 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
135 0x584, 1),
136 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
137 0x584, 2),
138 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
139 0x584, 3),
140 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
141 0x584, 4),
142 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
143 0x588, 0),
144 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
145 0x594, 0),
146 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
147 0x598, 0),
148 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
149 0x5a8, 0),
150 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
151 0x5a8, 1),
152};
153
154static struct rzg2l_reset r9a07g044_resets[] = {
155 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
156 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
157 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
158 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
159 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
160 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
161 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
162 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
163 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
164 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
165 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
166 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
167 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
168 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
169 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
170 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
171 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
172 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
173 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
174 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
175 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
176 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
177 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
178 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
179 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
180 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
181 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
182 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
183 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
184 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
185};
186
187static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
188 MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
189 MOD_CLK_BASE + R9A07G044_IA55_CLK,
190 MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
191};
192
193const struct rzg2l_cpg_info r9a07g044_cpg_info = {
194
195 .core_clks = r9a07g044_core_clks,
196 .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
197 .last_dt_core_clk = LAST_DT_CORE_CLK,
198 .num_total_core_clks = MOD_CLK_BASE,
199
200
201 .crit_mod_clks = r9a07g044_crit_mod_clks,
202 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
203
204
205 .mod_clks = r9a07g044_mod_clks,
206 .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
207 .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
208
209
210 .resets = r9a07g044_resets,
211 .num_resets = ARRAY_SIZE(r9a07g044_resets),
212};
213
