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32#include <linux/of.h>
33#include <linux/slab.h>
34#include <linux/io.h>
35#include <linux/clk.h>
36#include <linux/clk-provider.h>
37#include "clk.h"
38
39
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41
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47
48
49
50
51
52struct rockchip_cpuclk {
53 struct clk_hw hw;
54 struct clk *alt_parent;
55 void __iomem *reg_base;
56 struct notifier_block clk_nb;
57 unsigned int rate_count;
58 struct rockchip_cpuclk_rate_table *rate_table;
59 const struct rockchip_cpuclk_reg_data *reg_data;
60 spinlock_t *lock;
61};
62
63#define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw)
64#define to_rockchip_cpuclk_nb(nb) \
65 container_of(nb, struct rockchip_cpuclk, clk_nb)
66
67static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings(
68 struct rockchip_cpuclk *cpuclk, unsigned long rate)
69{
70 const struct rockchip_cpuclk_rate_table *rate_table =
71 cpuclk->rate_table;
72 int i;
73
74 for (i = 0; i < cpuclk->rate_count; i++) {
75 if (rate == rate_table[i].prate)
76 return &rate_table[i];
77 }
78
79 return NULL;
80}
81
82static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,
83 unsigned long parent_rate)
84{
85 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
86 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
87 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
88
89 clksel0 >>= reg_data->div_core_shift[0];
90 clksel0 &= reg_data->div_core_mask[0];
91 return parent_rate / (clksel0 + 1);
92}
93
94static const struct clk_ops rockchip_cpuclk_ops = {
95 .recalc_rate = rockchip_cpuclk_recalc_rate,
96};
97
98static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
99 const struct rockchip_cpuclk_rate_table *rate)
100{
101 int i;
102
103
104 for (i = 0; i < ARRAY_SIZE(rate->divs); i++) {
105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i];
106
107 if (!clksel->reg)
108 continue;
109
110 pr_debug("%s: setting reg 0x%x to 0x%x\n",
111 __func__, clksel->reg, clksel->val);
112 writel(clksel->val, cpuclk->reg_base + clksel->reg);
113 }
114}
115
116static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
117 struct clk_notifier_data *ndata)
118{
119 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
120 const struct rockchip_cpuclk_rate_table *rate;
121 unsigned long alt_prate, alt_div;
122 unsigned long flags;
123 int i = 0;
124
125
126 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
127 if (!rate) {
128 pr_err("%s: Invalid rate : %lu for cpuclk\n",
129 __func__, ndata->new_rate);
130 return -EINVAL;
131 }
132
133 alt_prate = clk_get_rate(cpuclk->alt_parent);
134
135 spin_lock_irqsave(cpuclk->lock, flags);
136
137
138
139
140
141
142
143 if (alt_prate > ndata->old_rate) {
144
145 alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
146 if (alt_div > reg_data->div_core_mask[0]) {
147 pr_warn("%s: limiting alt-divider %lu to %d\n",
148 __func__, alt_div, reg_data->div_core_mask[0]);
149 alt_div = reg_data->div_core_mask[0];
150 }
151
152
153
154
155
156
157
158
159 pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
160 __func__, alt_div, alt_prate, ndata->old_rate);
161
162 for (i = 0; i < reg_data->num_cores; i++) {
163 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
164 reg_data->div_core_shift[i]),
165 cpuclk->reg_base + reg_data->core_reg[i]);
166 }
167 }
168
169 writel(HIWORD_UPDATE(reg_data->mux_core_alt,
170 reg_data->mux_core_mask,
171 reg_data->mux_core_shift),
172 cpuclk->reg_base + reg_data->core_reg[0]);
173
174 spin_unlock_irqrestore(cpuclk->lock, flags);
175 return 0;
176}
177
178static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
179 struct clk_notifier_data *ndata)
180{
181 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
182 const struct rockchip_cpuclk_rate_table *rate;
183 unsigned long flags;
184 int i = 0;
185
186 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
187 if (!rate) {
188 pr_err("%s: Invalid rate : %lu for cpuclk\n",
189 __func__, ndata->new_rate);
190 return -EINVAL;
191 }
192
193 spin_lock_irqsave(cpuclk->lock, flags);
194
195 if (ndata->old_rate < ndata->new_rate)
196 rockchip_cpuclk_set_dividers(cpuclk, rate);
197
198
199
200
201
202
203
204
205 writel(HIWORD_UPDATE(reg_data->mux_core_main,
206 reg_data->mux_core_mask,
207 reg_data->mux_core_shift),
208 cpuclk->reg_base + reg_data->core_reg[0]);
209
210
211 for (i = 0; i < reg_data->num_cores; i++) {
212 writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
213 reg_data->div_core_shift[i]),
214 cpuclk->reg_base + reg_data->core_reg[i]);
215 }
216
217 if (ndata->old_rate > ndata->new_rate)
218 rockchip_cpuclk_set_dividers(cpuclk, rate);
219
220 spin_unlock_irqrestore(cpuclk->lock, flags);
221 return 0;
222}
223
224
225
226
227
228
229
230static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb,
231 unsigned long event, void *data)
232{
233 struct clk_notifier_data *ndata = data;
234 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
235 int ret = 0;
236
237 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
238 __func__, event, ndata->old_rate, ndata->new_rate);
239 if (event == PRE_RATE_CHANGE)
240 ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);
241 else if (event == POST_RATE_CHANGE)
242 ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);
243
244 return notifier_from_errno(ret);
245}
246
247struct clk *rockchip_clk_register_cpuclk(const char *name,
248 const char *const *parent_names, u8 num_parents,
249 const struct rockchip_cpuclk_reg_data *reg_data,
250 const struct rockchip_cpuclk_rate_table *rates,
251 int nrates, void __iomem *reg_base, spinlock_t *lock)
252{
253 struct rockchip_cpuclk *cpuclk;
254 struct clk_init_data init;
255 struct clk *clk, *cclk;
256 int ret;
257
258 if (num_parents < 2) {
259 pr_err("%s: needs at least two parent clocks\n", __func__);
260 return ERR_PTR(-EINVAL);
261 }
262
263 cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
264 if (!cpuclk)
265 return ERR_PTR(-ENOMEM);
266
267 init.name = name;
268 init.parent_names = &parent_names[reg_data->mux_core_main];
269 init.num_parents = 1;
270 init.ops = &rockchip_cpuclk_ops;
271
272
273 init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0;
274
275
276 init.flags |= CLK_SET_RATE_NO_REPARENT;
277
278 init.flags |= CLK_GET_RATE_NOCACHE;
279
280 cpuclk->reg_base = reg_base;
281 cpuclk->lock = lock;
282 cpuclk->reg_data = reg_data;
283 cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
284 cpuclk->hw.init = &init;
285
286 cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
287 if (!cpuclk->alt_parent) {
288 pr_err("%s: could not lookup alternate parent: (%d)\n",
289 __func__, reg_data->mux_core_alt);
290 ret = -EINVAL;
291 goto free_cpuclk;
292 }
293
294 ret = clk_prepare_enable(cpuclk->alt_parent);
295 if (ret) {
296 pr_err("%s: could not enable alternate parent\n",
297 __func__);
298 goto free_cpuclk;
299 }
300
301 clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
302 if (!clk) {
303 pr_err("%s: could not lookup parent clock: (%d) %s\n",
304 __func__, reg_data->mux_core_main,
305 parent_names[reg_data->mux_core_main]);
306 ret = -EINVAL;
307 goto free_alt_parent;
308 }
309
310 ret = clk_notifier_register(clk, &cpuclk->clk_nb);
311 if (ret) {
312 pr_err("%s: failed to register clock notifier for %s\n",
313 __func__, name);
314 goto free_alt_parent;
315 }
316
317 if (nrates > 0) {
318 cpuclk->rate_count = nrates;
319 cpuclk->rate_table = kmemdup(rates,
320 sizeof(*rates) * nrates,
321 GFP_KERNEL);
322 if (!cpuclk->rate_table) {
323 ret = -ENOMEM;
324 goto unregister_notifier;
325 }
326 }
327
328 cclk = clk_register(NULL, &cpuclk->hw);
329 if (IS_ERR(cclk)) {
330 pr_err("%s: could not register cpuclk %s\n", __func__, name);
331 ret = PTR_ERR(cclk);
332 goto free_rate_table;
333 }
334
335 return cclk;
336
337free_rate_table:
338 kfree(cpuclk->rate_table);
339unregister_notifier:
340 clk_notifier_unregister(clk, &cpuclk->clk_nb);
341free_alt_parent:
342 clk_disable_unprepare(cpuclk->alt_parent);
343free_cpuclk:
344 kfree(cpuclk);
345 return ERR_PTR(ret);
346}
347