LXR linux/drivers/clk/sifive/fu540-prci.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2018-2019 SiFive, Inc.
   4 * Copyright (C) 2018-2019 Wesley Terpstra
   5 * Copyright (C) 2018-2019 Paul Walmsley
   6 * Copyright (C) 2020 Zong Li
   7 *
   8 * The FU540 PRCI implements clock and reset control for the SiFive
   9 * FU540-C000 chip.  This driver assumes that it has sole control
  10 * over all PRCI resources.
  11 *
  12 * This driver is based on the PRCI driver written by Wesley Terpstra:
  13 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
  14 *
  15 * References:
  16 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
  17 */
  18
  19#include <linux/module.h>
  20
  21#include <dt-bindings/clock/sifive-fu540-prci.h>
  22
  23#include "fu540-prci.h"
  24#include "sifive-prci.h"
  25
  26/* PRCI integration data for each WRPLL instance */
  27
  28static struct __prci_wrpll_data __prci_corepll_data = {
  29        .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
  30        .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
  31        .enable_bypass = sifive_prci_coreclksel_use_hfclk,
  32        .disable_bypass = sifive_prci_coreclksel_use_corepll,
  33};
  34
  35static struct __prci_wrpll_data __prci_ddrpll_data = {
  36        .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
  37        .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
  38};
  39
  40static struct __prci_wrpll_data __prci_gemgxlpll_data = {
  41        .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
  42        .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
  43};
  44
  45/* Linux clock framework integration */
  46
  47static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
  48        .set_rate = sifive_prci_wrpll_set_rate,
  49        .round_rate = sifive_prci_wrpll_round_rate,
  50        .recalc_rate = sifive_prci_wrpll_recalc_rate,
  51        .enable = sifive_prci_clock_enable,
  52        .disable = sifive_prci_clock_disable,
  53        .is_enabled = sifive_clk_is_enabled,
  54};
  55
  56static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
  57        .recalc_rate = sifive_prci_wrpll_recalc_rate,
  58};
  59
  60static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
  61        .recalc_rate = sifive_prci_tlclksel_recalc_rate,
  62};
  63
  64/* List of clock controls provided by the PRCI */
  65struct __prci_clock __prci_init_clocks_fu540[] = {
  66        [PRCI_CLK_COREPLL] = {
  67                .name = "corepll",
  68                .parent_name = "hfclk",
  69                .ops = &sifive_fu540_prci_wrpll_clk_ops,
  70                .pwd = &__prci_corepll_data,
  71        },
  72        [PRCI_CLK_DDRPLL] = {
  73                .name = "ddrpll",
  74                .parent_name = "hfclk",
  75                .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
  76                .pwd = &__prci_ddrpll_data,
  77        },
  78        [PRCI_CLK_GEMGXLPLL] = {
  79                .name = "gemgxlpll",
  80                .parent_name = "hfclk",
  81                .ops = &sifive_fu540_prci_wrpll_clk_ops,
  82                .pwd = &__prci_gemgxlpll_data,
  83        },
  84        [PRCI_CLK_TLCLK] = {
  85                .name = "tlclk",
  86                .parent_name = "corepll",
  87                .ops = &sifive_fu540_prci_tlclksel_clk_ops,
  88        },
  89};
  90