LXR linux/drivers/clk/socfpga/stratix10-clk.h

   1/* SPDX-License-Identifier:    GPL-2.0 */
   2/*
   3 * Copyright (C) 2017, Intel Corporation
   4 */
   5
   6#ifndef __STRATIX10_CLK_H
   7#define __STRATIX10_CLK_H
   8
   9struct stratix10_clock_data {
  10        struct clk_hw_onecell_data      clk_data;
  11        void __iomem            *base;
  12};
  13
  14struct stratix10_pll_clock {
  15        unsigned int            id;
  16        const char              *name;
  17        const struct clk_parent_data    *parent_data;
  18        u8                      num_parents;
  19        unsigned long           flags;
  20        unsigned long           offset;
  21};
  22
  23struct stratix10_perip_c_clock {
  24        unsigned int            id;
  25        const char              *name;
  26        const char              *parent_name;
  27        const struct clk_parent_data    *parent_data;
  28        u8                      num_parents;
  29        unsigned long           flags;
  30        unsigned long           offset;
  31};
  32
  33struct n5x_perip_c_clock {
  34        unsigned int            id;
  35        const char              *name;
  36        const char              *parent_name;
  37        const char              *const *parent_names;
  38        u8                      num_parents;
  39        unsigned long           flags;
  40        unsigned long           offset;
  41        unsigned long           shift;
  42};
  43
  44struct stratix10_perip_cnt_clock {
  45        unsigned int            id;
  46        const char              *name;
  47        const char              *parent_name;
  48        const struct clk_parent_data    *parent_data;
  49        u8                      num_parents;
  50        unsigned long           flags;
  51        unsigned long           offset;
  52        u8                      fixed_divider;
  53        unsigned long           bypass_reg;
  54        unsigned long           bypass_shift;
  55};
  56
  57struct stratix10_gate_clock {
  58        unsigned int            id;
  59        const char              *name;
  60        const char              *parent_name;
  61        const struct clk_parent_data    *parent_data;
  62        u8                      num_parents;
  63        unsigned long           flags;
  64        unsigned long           gate_reg;
  65        u8                      gate_idx;
  66        unsigned long           div_reg;
  67        u8                      div_offset;
  68        u8                      div_width;
  69        unsigned long           bypass_reg;
  70        u8                      bypass_shift;
  71        u8                      fixed_div;
  72};
  73
  74struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
  75                             void __iomem *reg);
  76struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
  77                                void __iomem *reg);
  78struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
  79                             void __iomem *reg);
  80struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
  81                                void __iomem *reg);
  82struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
  83                                void __iomem *reg);
  84struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
  85                                    void __iomem *reg);
  86struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
  87                              void __iomem *reg);
  88struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
  89                              void __iomem *reg);
  90#endif  /* __STRATIX10_CLK_H */
  91