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5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/of_address.h>
9#include <linux/platform_device.h>
10
11#include "ccu_common.h"
12#include "ccu_reset.h"
13
14#include "ccu_div.h"
15#include "ccu_gate.h"
16#include "ccu_mp.h"
17#include "ccu_nm.h"
18
19#include "ccu-sun50i-a100-r.h"
20
21static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
22 "iosc", "pll-periph0" };
23static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
24 { .index = 3, .shift = 0, .width = 5 },
25};
26
27static struct ccu_div r_cpus_clk = {
28 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
29
30 .mux = {
31 .shift = 24,
32 .width = 2,
33
34 .var_predivs = cpus_r_apb2_predivs,
35 .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
36 },
37
38 .common = {
39 .reg = 0x000,
40 .features = CCU_FEATURE_VARIABLE_PREDIV,
41 .hw.init = CLK_HW_INIT_PARENTS("cpus",
42 cpus_r_apb2_parents,
43 &ccu_div_ops,
44 0),
45 },
46};
47
48static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
49
50static struct ccu_div r_apb1_clk = {
51 .div = _SUNXI_CCU_DIV(0, 2),
52
53 .common = {
54 .reg = 0x00c,
55 .hw.init = CLK_HW_INIT("r-apb1",
56 "r-ahb",
57 &ccu_div_ops,
58 0),
59 },
60};
61
62static struct ccu_div r_apb2_clk = {
63 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
64
65 .mux = {
66 .shift = 24,
67 .width = 2,
68
69 .var_predivs = cpus_r_apb2_predivs,
70 .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
71 },
72
73 .common = {
74 .reg = 0x010,
75 .features = CCU_FEATURE_VARIABLE_PREDIV,
76 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
77 cpus_r_apb2_parents,
78 &ccu_div_ops,
79 0),
80 },
81};
82
83static const struct clk_parent_data clk_parent_r_apb1[] = {
84 { .hw = &r_apb1_clk.common.hw },
85};
86
87static const struct clk_parent_data clk_parent_r_apb2[] = {
88 { .hw = &r_apb2_clk.common.hw },
89};
90
91static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
92 0x11c, BIT(0), 0);
93
94static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
95 0x12c, BIT(0), 0);
96
97static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
98 "iosc" };
99static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents,
100 0x130, 24, 2, 0);
101
102static SUNXI_CCU_GATE_DATA(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm",
103 clk_parent_r_apb1, 0x13c, BIT(0), 0);
104
105static SUNXI_CCU_GATE_DATA(r_apb1_ppu_clk, "r-apb1-ppu", clk_parent_r_apb1,
106 0x17c, BIT(0), 0);
107
108static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2,
109 0x18c, BIT(0), 0);
110
111static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2,
112 0x19c, BIT(0), 0);
113
114static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2,
115 0x19c, BIT(1), 0);
116
117static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };
118static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",
119 r_apb1_ir_rx_parents, 0x1c0,
120 0, 5,
121 8, 2,
122 24, 1,
123 BIT(31),
124 0);
125
126static SUNXI_CCU_GATE_DATA(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx",
127 clk_parent_r_apb1, 0x1cc, BIT(0), 0);
128
129static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
130 0x20c, BIT(0), 0);
131
132static struct ccu_common *sun50i_a100_r_ccu_clks[] = {
133 &r_cpus_clk.common,
134 &r_apb1_clk.common,
135 &r_apb2_clk.common,
136 &r_apb1_timer_clk.common,
137 &r_apb1_twd_clk.common,
138 &r_apb1_pwm_clk.common,
139 &r_apb1_bus_pwm_clk.common,
140 &r_apb1_ppu_clk.common,
141 &r_apb2_uart_clk.common,
142 &r_apb2_i2c0_clk.common,
143 &r_apb2_i2c1_clk.common,
144 &r_apb1_ir_rx_clk.common,
145 &r_apb1_bus_ir_rx_clk.common,
146 &r_ahb_bus_rtc_clk.common,
147};
148
149static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
150 .hws = {
151 [CLK_R_CPUS] = &r_cpus_clk.common.hw,
152 [CLK_R_AHB] = &r_ahb_clk.hw,
153 [CLK_R_APB1] = &r_apb1_clk.common.hw,
154 [CLK_R_APB2] = &r_apb2_clk.common.hw,
155 [CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
156 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
157 [CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
158 [CLK_R_APB1_BUS_PWM] = &r_apb1_bus_pwm_clk.common.hw,
159 [CLK_R_APB1_PPU] = &r_apb1_ppu_clk.common.hw,
160 [CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
161 [CLK_R_APB2_I2C0] = &r_apb2_i2c0_clk.common.hw,
162 [CLK_R_APB2_I2C1] = &r_apb2_i2c1_clk.common.hw,
163 [CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw,
164 [CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw,
165 [CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
166 },
167 .num = CLK_NUMBER,
168};
169
170static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
171 [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
172 [RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
173 [RST_R_APB1_PPU] = { 0x17c, BIT(16) },
174 [RST_R_APB2_UART] = { 0x18c, BIT(16) },
175 [RST_R_APB2_I2C0] = { 0x19c, BIT(16) },
176 [RST_R_APB2_I2C1] = { 0x19c, BIT(17) },
177 [RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) },
178 [RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
179};
180
181static const struct sunxi_ccu_desc sun50i_a100_r_ccu_desc = {
182 .ccu_clks = sun50i_a100_r_ccu_clks,
183 .num_ccu_clks = ARRAY_SIZE(sun50i_a100_r_ccu_clks),
184
185 .hw_clks = &sun50i_a100_r_hw_clks,
186
187 .resets = sun50i_a100_r_ccu_resets,
188 .num_resets = ARRAY_SIZE(sun50i_a100_r_ccu_resets),
189};
190
191static int sun50i_a100_r_ccu_probe(struct platform_device *pdev)
192{
193 void __iomem *reg;
194
195 reg = devm_platform_ioremap_resource(pdev, 0);
196 if (IS_ERR(reg))
197 return PTR_ERR(reg);
198
199 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a100_r_ccu_desc);
200}
201
202static const struct of_device_id sun50i_a100_r_ccu_ids[] = {
203 { .compatible = "allwinner,sun50i-a100-r-ccu" },
204 { }
205};
206
207static struct platform_driver sun50i_a100_r_ccu_driver = {
208 .probe = sun50i_a100_r_ccu_probe,
209 .driver = {
210 .name = "sun50i-a100-r-ccu",
211 .of_match_table = sun50i_a100_r_ccu_ids,
212 },
213};
214module_platform_driver(sun50i_a100_r_ccu_driver);
215
